From ca0be9e9c56bdedf2f18426639c5aca79a4e06ae Mon Sep 17 00:00:00 2001 From: Nhut Nguyen Date: Mon, 16 Sep 2024 13:18:49 +0700 Subject: [PATCH] hal: renesas: rz: Initial support RZ FSP hal driver This is the initial hal support for RZ family series. The hal layer support for RZ/G3S will base on RZ/G3S FSP. Signed-off-by: Nhut Nguyen Signed-off-by: Binh Nguyen --- drivers/CMakeLists.txt | 1 + drivers/rz/CMakeLists.txt | 24 + drivers/rz/README | 34 + drivers/rz/fsp/inc/api/r_ioport_api.h | 203 + drivers/rz/fsp/inc/api/r_transfer_api.h | 392 + drivers/rz/fsp/inc/api/r_uart_api.h | 269 + drivers/rz/fsp/inc/fsp_common_api.h | 345 + drivers/rz/fsp/inc/fsp_version.h | 66 + drivers/rz/fsp/inc/instances/rzg/r_ioport.h | 317 + .../rz/fsp/inc/instances/rzg/r_scif_uart.h | 228 + drivers/rz/fsp/src/rzg/CMakeLists.txt | 10 + .../cmsis/Device/RENESAS/Include/R9A08G045S.h | 151 + .../RENESAS/Include/R9A08G045S/iobitmask.h | 40 + .../R9A08G045S/iobitmasks/adc_c_iobitmask.h | 353 + .../R9A08G045S/iobitmasks/canfd_iobitmask.h | 1003 +++ .../R9A08G045S/iobitmasks/cpg_iobitmask.h | 2927 +++++++ .../R9A08G045S/iobitmasks/dmac_b_iobitmask.h | 267 + .../R9A08G045S/iobitmasks/gpio_iobitmask.h | 1959 +++++ .../R9A08G045S/iobitmasks/gpt_iobitmask.h | 505 ++ .../R9A08G045S/iobitmasks/gtm_iobitmask.h | 31 + .../iobitmasks/intc_im33_iobitmask.h | 685 ++ .../R9A08G045S/iobitmasks/mhu_iobitmask.h | 35 + .../R9A08G045S/iobitmasks/poeg_iobitmask.h | 35 + .../R9A08G045S/iobitmasks/riic_iobitmask.h | 342 + .../R9A08G045S/iobitmasks/rspi_iobitmask.h | 149 + .../R9A08G045S/iobitmasks/scifa_iobitmask.h | 127 + .../R9A08G045S/iobitmasks/ssi_iobitmask.h | 109 + .../R9A08G045S/iobitmasks/sysc_iobitmask.h | 656 ++ .../R9A08G045S/iobitmasks/tsu_iobitmask.h | 25 + .../R9A08G045S/iobitmasks/tzc_iobitmask.h | 299 + .../R9A08G045S/iobitmasks/wdt_iobitmask.h | 35 + .../R9A08G045S/iobitmasks/xspi_iobitmask.h | 269 + .../RENESAS/Include/R9A08G045S/iodefine.h | 40 + .../R9A08G045S/iodefines/adc_c_iodefine.h | 377 + .../R9A08G045S/iodefines/canfd_iodefine.h | 1699 ++++ .../R9A08G045S/iodefines/cpg_iodefine.h | 3815 +++++++++ .../R9A08G045S/iodefines/dmac_b_iodefine.h | 393 + .../R9A08G045S/iodefines/gpio_iodefine.h | 6964 +++++++++++++++++ .../R9A08G045S/iodefines/gpt_iodefine.h | 667 ++ .../R9A08G045S/iodefines/gtm_iodefine.h | 116 + .../R9A08G045S/iodefines/intc_im33_iodefine.h | 570 ++ .../R9A08G045S/iodefines/mhu_iodefine.h | 163 + .../R9A08G045S/iodefines/poeg_iodefine.h | 65 + .../R9A08G045S/iodefines/riic_iodefine.h | 280 + .../R9A08G045S/iodefines/rspi_iodefine.h | 291 + .../R9A08G045S/iodefines/scifa_iodefine.h | 230 + .../R9A08G045S/iodefines/ssi_iodefine.h | 190 + .../R9A08G045S/iodefines/sysc_iodefine.h | 1169 +++ .../R9A08G045S/iodefines/tsu_iodefine.h | 69 + .../R9A08G045S/iodefines/tzc_iodefine.h | 909 +++ .../R9A08G045S/iodefines/wdt_iodefine.h | 120 + .../R9A08G045S/iodefines/xspi_iodefine.h | 485 ++ .../cmsis/Device/RENESAS/Include/renesas.h | 81 + .../bsp/cmsis/Device/RENESAS/Include/system.h | 88 + .../src/rzg/bsp/mcu/all/bsp_address_convert.c | 82 + .../src/rzg/bsp/mcu/all/bsp_address_convert.h | 37 + .../rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.c | 957 +++ .../rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.h | 464 ++ .../rz/fsp/src/rzg/bsp/mcu/all/bsp_common.c | 188 + .../rzg/bsp/mcu/all/bsp_compiler_support.h | 92 + .../rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.c | 144 + .../rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.h | 55 + .../fsp/src/rzg/bsp/mcu/all/bsp_group_irq.c | 56 + .../fsp/src/rzg/bsp/mcu/all/bsp_group_irq.h | 46 + .../rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.c | 12 + .../rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.h | 26 + drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.c | 27 + drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.h | 841 ++ drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irq.c | 46 + drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.c | 68 + drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.h | 33 + .../rz/fsp/src/rzg/bsp/mcu/all/bsp_mcu_api.h | 20 + .../fsp/src/rzg/bsp/mcu/all/bsp_module_stop.h | 131 + drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_sbrk.c | 92 + .../rz/fsp/src/rzg/bsp/mcu/all/bsp_security.c | 160 + .../rz/fsp/src/rzg/bsp/mcu/all/bsp_security.h | 268 + .../rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_dmac.h | 563 ++ .../fsp/src/rzg/bsp/mcu/rzg3s/bsp_feature.h | 198 + .../rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_irq_id.h | 582 ++ .../fsp/src/rzg/bsp/mcu/rzg3s/bsp_mcu_info.h | 53 + .../src/rzg/bsp/mcu/rzg3s/bsp_multi_core.h | 42 + .../fsp/src/rzg/bsp/mcu/rzg3s/bsp_override.h | 761 ++ .../rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_reset.h | 44 + .../src/rzg/bsp/mcu/rzg3s/bsp_slave_address.h | 81 + drivers/rz/fsp/src/rzg/r_ioport/r_ioport.c | 1290 +++ .../rz/fsp/src/rzg/r_scif_uart/r_scif_uart.c | 2036 +++++ zephyr/CMakeLists.txt | 1 + zephyr/rz/CMakeLists.txt | 4 + zephyr/rz/portable/bsp_api.h | 89 + zephyr/rz/portable/bsp_common.h | 288 + zephyr/rz/portable/bsp_irq.h | 217 + zephyr/rz/portable/fsp_features.h | 234 + zephyr/rz/rz_cfg/CMakeLists.txt | 7 + zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_cfg.h | 27 + .../rz_cfg/fsp_cfg/bsp/rzg3s/bsp_clock_cfg.h | 58 + .../fsp_cfg/bsp/rzg3s/bsp_mcu_device_cfg.h | 10 + .../fsp_cfg/bsp/rzg3s/bsp_mcu_device_pn_cfg.h | 14 + .../fsp_cfg/bsp/rzg3s/bsp_mcu_family_cfg.h | 59 + zephyr/rz/rz_cfg/fsp_cfg/rzg/r_ioport_cfg.h | 18 + .../rz/rz_cfg/fsp_cfg/rzg/r_scif_uart_cfg.h | 12 + 100 files changed, 41205 insertions(+) create mode 100644 drivers/rz/CMakeLists.txt create mode 100644 drivers/rz/README create mode 100644 drivers/rz/fsp/inc/api/r_ioport_api.h create mode 100644 drivers/rz/fsp/inc/api/r_transfer_api.h create mode 100644 drivers/rz/fsp/inc/api/r_uart_api.h create mode 100644 drivers/rz/fsp/inc/fsp_common_api.h create mode 100644 drivers/rz/fsp/inc/fsp_version.h create mode 100644 drivers/rz/fsp/inc/instances/rzg/r_ioport.h create mode 100644 drivers/rz/fsp/inc/instances/rzg/r_scif_uart.h create mode 100644 drivers/rz/fsp/src/rzg/CMakeLists.txt create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/adc_c_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/canfd_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/cpg_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/dmac_b_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gpio_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gpt_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gtm_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/intc_im33_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/mhu_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/poeg_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/riic_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/rspi_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/scifa_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/ssi_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/sysc_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/tsu_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/tzc_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/wdt_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/xspi_iobitmask.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/adc_c_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/canfd_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/cpg_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/dmac_b_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gpio_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gpt_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gtm_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/intc_im33_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/mhu_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/poeg_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/riic_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/rspi_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/scifa_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/ssi_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/sysc_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/tsu_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/tzc_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/wdt_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/xspi_iodefine.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/renesas.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/system.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_address_convert.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_address_convert.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_common.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_compiler_support.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_group_irq.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_group_irq.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irq.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_mcu_api.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_module_stop.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_sbrk.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_security.c create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_security.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_dmac.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_feature.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_irq_id.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_mcu_info.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_multi_core.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_override.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_reset.h create mode 100644 drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_slave_address.h create mode 100644 drivers/rz/fsp/src/rzg/r_ioport/r_ioport.c create mode 100644 drivers/rz/fsp/src/rzg/r_scif_uart/r_scif_uart.c create mode 100644 zephyr/rz/CMakeLists.txt create mode 100644 zephyr/rz/portable/bsp_api.h create mode 100644 zephyr/rz/portable/bsp_common.h create mode 100644 zephyr/rz/portable/bsp_irq.h create mode 100644 zephyr/rz/portable/fsp_features.h create mode 100644 zephyr/rz/rz_cfg/CMakeLists.txt create mode 100644 zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_cfg.h create mode 100644 zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_clock_cfg.h create mode 100644 zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_device_cfg.h create mode 100644 zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_device_pn_cfg.h create mode 100644 zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_family_cfg.h create mode 100644 zephyr/rz/rz_cfg/fsp_cfg/rzg/r_ioport_cfg.h create mode 100644 zephyr/rz/rz_cfg/fsp_cfg/rzg/r_scif_uart_cfg.h diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index a6156c37..681a3985 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -1,3 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RA_FSP ra) +add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RZ_FSP rz) diff --git a/drivers/rz/CMakeLists.txt b/drivers/rz/CMakeLists.txt new file mode 100644 index 00000000..c3aedbf5 --- /dev/null +++ b/drivers/rz/CMakeLists.txt @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Extract the RZ family name from CONFIG_SOC_SERIES +string(SUBSTRING ${CONFIG_SOC_SERIES} 0 3 SOC_SERIES_PREFIX) + +add_subdirectory(fsp/src/${SOC_SERIES_PREFIX}) + +set(include_dirs + fsp/inc + fsp/inc/api + fsp/inc/instances/${SOC_SERIES_PREFIX} + fsp/src/${SOC_SERIES_PREFIX}/bsp/mcu/all + fsp/src/${SOC_SERIES_PREFIX}/bsp/cmsis/Device/RENESAS/Include + fsp/src/${SOC_SERIES_PREFIX}/bsp/mcu/${CONFIG_SOC_SERIES} +) + +zephyr_include_directories(${include_dirs}) + +# Optional build base on feature configuration +zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_IOPORT + fsp/src/${SOC_SERIES_PREFIX}/r_ioport/r_ioport.c) + +zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_SCIF_UART + fsp/src/${SOC_SERIES_PREFIX}/r_scif_uart/r_scif_uart.c) diff --git a/drivers/rz/README b/drivers/rz/README new file mode 100644 index 00000000..cc0a0191 --- /dev/null +++ b/drivers/rz/README @@ -0,0 +1,34 @@ +Flexible Software Package (FSP) +############################### + +Origin: + Renesas Electronics Corporation + https://github.com/renesas/rzg-fsp + +Status: + version v2.1.0 + +Purpose: + Flexible Software Package (FSP) for Renesas RZ MPU Family. + +Description: + This package is a snapshot from the RZ FSP software released by Renesas Electronics Corporation + It contain the HAL and a set of CMSIS headers files for the Renesas RZ MPUs + +Dependencies: + None. + +URL: + https://github.com/renesas/rzg-fsp + +Commit: + 8db06f881784144e86361b1266ac4d3c026f6ad8 + +Maintained-by: + Renesas Electronics Corporation + +License: + BSD-3-Clause + +License Link: + https://opensource.org/licenses/BSD-3-Clause diff --git a/drivers/rz/fsp/inc/api/r_ioport_api.h b/drivers/rz/fsp/inc/api/r_ioport_api.h new file mode 100644 index 00000000..84aeac4d --- /dev/null +++ b/drivers/rz/fsp/inc/api/r_ioport_api.h @@ -0,0 +1,203 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup IOPORT_API I/O Port Interface + * @brief Interface for accessing I/O ports and configuring I/O functionality. + * + * @section IOPORT_API_SUMMARY Summary + * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. + * Port and pin direction can be changed. + * + * IOPORT Interface description: @ref IOPORT + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_API_H +#define R_IOPORT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IO port type used with ports */ +typedef uint16_t ioport_size_t; ///< IO port size on this device + +/** PFS writing enable/disable. */ +typedef enum e_ioport_pwpr +{ + IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access + IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access +} ioport_pwpr_t; + +/** Pin identifier and Pin Function Setting (PFS) value */ +typedef struct st_ioport_pin_cfg +{ + uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure + bsp_io_port_pin_t pin; ///< Pin identifier +} ioport_pin_cfg_t; + +/** Multiple pin configuration data for loading into each GPIO register by R_IOPORT_Init() */ +typedef struct st_ioport_cfg +{ + uint16_t number_of_pins; ///< Number of pins for which there is configuration data + ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data + const void * p_extend; ///< Pointer to hardware extend configuration +} ioport_cfg_t; + +/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. + * @par Implemented as + * - ioport_instance_ctrl_t + */ +typedef void ioport_ctrl_t; + +/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ +typedef struct st_ioport_api +{ + /** Initialize internal driver data and initial pin configurations. Called during startup. Do + * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of + * multiple pins. + * @par Implemented as + * - @ref R_IOPORT_Open() + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Close the API. + * @par Implemented as + * - @ref R_IOPORT_Close() + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); + + /** Configure multiple pins. + * @par Implemented as + * - @ref R_IOPORT_PinsCfg() + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Configure settings for an individual pin. + * @par Implemented as + * - @ref R_IOPORT_PinCfg() + * @param[in] pin Pin to be read. + * @param[in] cfg Configuration options for the pin. + */ + fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + + /** Read the event input data of the specified pin and return the level. + * @par Implemented as + * - @ref R_IOPORT_PinEventInputRead() + * @param[in] pin Pin to be read. + * @param[in] p_pin_event Pointer to return the event data. + */ + fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); + + /** Write pin event data. + * @par Implemented as + * - @ref R_IOPORT_PinEventOutputWrite() + * @param[in] pin Pin event data is to be written to. + * @param[in] pin_value Level to be written to pin output event. + */ + fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); + + /** Read level of a pin. + * @par Implemented as + * - @ref R_IOPORT_PinRead() + * @param[in] pin Pin to be read. + * @param[in] p_pin_value Pointer to return the pin level. + */ + fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); + + /** Write specified level to a pin. + * @par Implemented as + * - @ref R_IOPORT_PinWrite() + * @param[in] pin Pin to be written to. + * @param[in] level State to be written to the pin. + */ + fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); + + /** Set the direction of one or more pins on a port. + * @par Implemented as + * - @ref R_IOPORT_PortDirectionSet() + * @param[in] port Port being configured. + * @param[in] direction_values Value controlling direction of pins on port + * (3 - output (input enable), 2 - output (input disable), 1 input, 0 - Hi-Z). + * @param[in] mask Mask controlling which pins on the port are to be configured. + */ + fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, + ioport_size_t mask); + + /** Read captured event data for a port. + * @par Implemented as + * - @ref R_IOPORT_PortEventInputRead() + * @param[in] port Port to be read. + * @param[in] p_event_data Pointer to return the event data. + */ + fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); + + /** Write event output data for a port. + * @par Implemented as + * - @ref R_IOPORT_PortEventOutputWrite() + * @param[in] port Port event data will be written to. + * @param[in] event_data Data to be written as event data to specified port. + * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. + * being written to port. + */ + fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, + ioport_size_t mask_value); + + /** Read states of pins on the specified port. + * @par Implemented as + * - @ref R_IOPORT_PortRead() + * @param[in] port Port to be read. + * @param[in] p_port_value Pointer to return the port value. + */ + fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); + + /** Write to multiple pins on a port. + * @par Implemented as + * - @ref R_IOPORT_PortWrite() + * @param[in] port Port to be written to. + * @param[in] value Value to be written to the port. + * @param[in] mask Mask controlling which pins on the port are written to. + */ + fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); +} ioport_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ioport_instance +{ + ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ioport_api_t const * p_api; ///< Pointer to the API structure for this instance +} ioport_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT_API) + **********************************************************************************************************************/ diff --git a/drivers/rz/fsp/inc/api/r_transfer_api.h b/drivers/rz/fsp/inc/api/r_transfer_api.h new file mode 100644 index 00000000..d25a3083 --- /dev/null +++ b/drivers/rz/fsp/inc/api/r_transfer_api.h @@ -0,0 +1,392 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup TRANSFER_API Transfer Interface + * + * @brief Interface for data transfer functions. + * + * @section TRANSFER_API_SUMMARY Summary + * The transfer interface supports background data transfer (no CPU intervention). + * + * Implemented by: + * - @ref DMAC_B + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_TRANSFER_API_H +#define R_TRANSFER_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define TRANSFER_SETTINGS_MODE_BITS (30U) +#define TRANSFER_SETTINGS_SIZE_BITS (28U) +#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) +#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) +#define TRANSFER_SETTINGS_IRQ_BITS (21U) +#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) +#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. + * @par Implemented as + * - dmac_b_instance_ctrl_t + */ +typedef void transfer_ctrl_t; + +#ifndef BSP_OVERRIDE_TRANSFER_MODE_T + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to + * the destination pointer. The transfer length is decremented and the source and address pointers are + * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests + * will not cause any further transfers. */ + TRANSFER_MODE_NORMAL = 0, + + /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the + * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the + * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats + * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is + * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ + TRANSFER_MODE_REPEAT = 1, + + /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. + * After each individual transfer, the source and destination pointers are updated according to + * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is + * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any + * further transfers. */ + TRANSFER_MODE_BLOCK = 2, + + /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets + * within a block (to split blocks into arrays of their first data, second data, etc.) */ + TRANSFER_MODE_REPEAT_BLOCK = 3 +} transfer_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T + +/** Transfer size specifies the size of each individual transfer. + * Total transfer length = transfer_size_t * transfer_length_t + */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value +} transfer_size_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 0, + + /** Offset is added to the address pointer after each transfer. */ + TRANSFER_ADDR_MODE_OFFSET = 1, + + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 2, + + /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_DECREMENTED = 3 +} transfer_addr_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T + +/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its + * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, + * the selected pointer returns to its original value after each transfer. */ +typedef enum e_transfer_repeat_area +{ + /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_DESTINATION = 0, + + /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_SOURCE = 1 +} transfer_repeat_area_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T + +/** Chain transfer mode options. + * @note Only applies for DTC. */ +typedef enum e_transfer_chain_mode +{ + /** Chain mode not used. */ + TRANSFER_CHAIN_MODE_DISABLED = 0, + + /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ + TRANSFER_CHAIN_MODE_EACH = 2, + + /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ + TRANSFER_CHAIN_MODE_END = 3 +} transfer_chain_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T + +/** Interrupt options. */ +typedef enum e_transfer_irq +{ + /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, + * the interrupt will occur only after subsequent chained transfer(s) are complete. + * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will + * prevent activation source interrupts until the transfer is complete. */ + TRANSFER_IRQ_END = 0, + + /** Interrupt occurs after each transfer. + * @note Not available in all HAL drivers. See HAL driver for details. */ + TRANSFER_IRQ_EACH = 1 +} transfer_irq_t; + +#endif + +/** Driver specific information. */ +typedef struct st_transfer_properties +{ + uint32_t block_count_max; ///< Maximum number of blocks + uint32_t block_count_remaining; ///< Number of blocks remaining + uint32_t transfer_length_max; ///< Maximum number of transfers + uint32_t transfer_length_remaining; ///< Number of transfers remaining +} transfer_properties_t; + +#ifndef BSP_OVERRIDE_TRANSFER_INFO_T + +/** This structure specifies the properties of the transfer. + * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. + * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. + * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must + * have a unique transfer_info_t. + * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this + * structure must remain in scope until the transfer it is used for is closed. + * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ +typedef struct st_transfer_info +{ + union + { + struct + { + uint32_t : 16; + uint32_t : 2; + + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode : 2; + + /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ + transfer_repeat_area_t repeat_area : 1; + + /** Select if interrupts should occur after each individual transfer or after the completion of all planned + * transfers. */ + transfer_irq_t irq : 1; + + /** Select when the chain transfer ends. */ + transfer_chain_mode_t chain_mode : 2; + + uint32_t : 2; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode : 2; + + /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ + transfer_size_t size : 2; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode : 2; + } transfer_settings_word_b; + + uint32_t transfer_settings_word; + }; + + void const * volatile p_src; ///< Source pointer + void * volatile p_dest; ///< Destination pointer + + /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or + * @ref TRANSFER_MODE_REPEAT (DMAC only) or + * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ + volatile uint16_t num_blocks; + + /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, + * and @ref TRANSFER_MODE_REPEAT_BLOCK + * see HAL driver for details. */ + volatile uint16_t length; +} transfer_info_t; + +#endif + +/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be + * initialized. */ +typedef struct st_transfer_cfg +{ + /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to + * an array of chained transfers that will be completed in order. */ + transfer_info_t * p_info; + + void const * p_extend; ///< Extension parameter for hardware specific settings. +} transfer_cfg_t; + +/** Select whether to start single or repeated transfer with software start. */ +typedef enum e_transfer_start_mode +{ + TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. + TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. +} transfer_start_mode_t; + +/** Transfer functions implemented at the HAL layer will follow this API. */ +typedef struct st_transfer_api +{ + /** Initial configuration. + * @par Implemented as + * - @ref R_DMAC_B_Open() + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure + * must be set by user. + */ + fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); + + /** Reconfigure the transfer. + * Enable the transfer if p_info is valid. + * @par Implemented as + * - @ref R_DMAC_B_Reconfigure() + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_info Pointer to a new transfer info structure. + */ + fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); + + /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. + * Enable the transfer if p_src, p_dest, and length are valid. + * @par Implemented as + * - @ref R_DMAC_B_Reset() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, + * resets number of repeats (initially stored in transfer_info_t::num_blocks) in + * repeat mode. Not used in repeat mode for DTC. + */ + fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint16_t const num_transfers); + + /** Enable transfer. Transfers occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source). + * @par Implemented as + * - @ref R_DMAC_B_Enable() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); + + /** Disable transfer. Transfers do not occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source). + * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a + * transfer. + * @par Implemented as + * - @ref R_DMAC_B_Disable() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); + + /** Start transfer in software. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * @note Not supported for DTC. + * @par Implemented as + * - @ref R_DMAC_B_SoftwareStart() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] mode Select mode from @ref transfer_start_mode_t. + */ + fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); + + /** Stop transfer in software. The transfer will stop after completion of the current transfer. + * @note Not supported for DTC. + * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * @par Implemented as + * - @ref R_DMAC_B_SoftwareStop() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); + + /** Provides information about this transfer. + * @par Implemented as + * - @ref R_DMAC_B_InfoGet() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[out] p_properties Driver specific information. + */ + fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); + + /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. + * @par Implemented as + * - @ref R_DMAC_B_Close() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); + + /** To update next transfer information without interruption during transfer. + * Allow further transfer continuation. + * @par Implemented as + * - @ref R_DMAC_B_Reload() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or block mode. + */ + fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint32_t const num_transfers); + +} transfer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_transfer_instance +{ + transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + transfer_api_t const * p_api; ///< Pointer to the API structure for this instance +} transfer_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup TRANSFER_API) + **********************************************************************************************************************/ diff --git a/drivers/rz/fsp/inc/api/r_uart_api.h b/drivers/rz/fsp/inc/api/r_uart_api.h new file mode 100644 index 00000000..41cc78eb --- /dev/null +++ b/drivers/rz/fsp/inc/api/r_uart_api.h @@ -0,0 +1,269 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup UART_API UART Interface + * @brief Interface for UART communications. + * + * @section UART_INTERFACE_SUMMARY Summary + * The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features: + * - Full-duplex UART communication + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code + * - Runtime baud-rate change + * - Hardware resource locking during a transaction + * - CTS/RTS hardware flow control support (with an associated IOPORT pin) + * + * Implemented by: + * - @ref SCIF_UART + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_UART_API_H +#define R_UART_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART Event codes */ +typedef enum e_sf_event +{ + UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event + UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event + UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received + UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event + UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event + UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event + UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event + UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data +} uart_event_t; + +/** UART Data bit length definition */ +typedef enum e_uart_data_bits +{ + UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit + UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit + UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit +} uart_data_bits_t; + +/** UART Parity definition */ +typedef enum e_uart_parity +{ + UART_PARITY_OFF = 0U, ///< No parity + UART_PARITY_EVEN = 2U, ///< Even parity + UART_PARITY_ODD = 3U, ///< Odd parity +} uart_parity_t; + +/** UART Stop bits definition */ +typedef enum e_uart_stop_bits +{ + UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit + UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit +} uart_stop_bits_t; + +/** UART transaction definition */ +typedef enum e_uart_dir +{ + UART_DIR_RX_TX = 3U, ///< Both RX and TX + UART_DIR_RX = 1U, ///< Only RX + UART_DIR_TX = 2U, ///< Only TX +} uart_dir_t; + +/** UART driver specific information */ +typedef struct st_uart_info +{ + /** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */ + uint32_t write_bytes_max; + + /** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */ + uint32_t read_bytes_max; +} uart_info_t; + +/** UART Callback parameter definition */ +typedef struct st_uart_callback_arg +{ + uint32_t channel; ///< Device channel number + uart_event_t event; ///< Event code + + /** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY, + * UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */ + uint32_t data; + void const * p_context; ///< Context provided to user during callback +} uart_callback_args_t; + +/** UART Configuration */ +typedef struct st_uart_cfg +{ + /* UART generic configuration */ + uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware. + uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9) + uart_parity_t parity; ///< Parity type (none or odd or even) + uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2) + uint8_t rxi_ipl; ///< Receive interrupt priority + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + uint8_t txi_ipl; ///< Transmit interrupt priority + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + uint8_t tei_ipl; ///< Transmit end interrupt priority + IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number + uint8_t eri_ipl; ///< Error interrupt priority + IRQn_Type eri_irq; ///< Error interrupt IRQ number + + /** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_rx; + + /** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_tx; + + /* Configuration for UART Event processing */ + void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function + void const * p_context; ///< User defined context passed into callback function + + /* Pointer to UART peripheral specific configuration */ + void const * p_extend; ///< UART hardware dependent configuration +} uart_cfg_t; + +/** UART control block. Allocate an instance specific control block to pass into the UART API calls. + * @par Implemented as + * - scif_uart_instance_ctrl_t + */ +typedef void uart_ctrl_t; + +/** Shared Interface definition for UART */ +typedef struct st_uart_api +{ + /** Open UART device. + * @par Implemented as + * - @ref R_SCIF_UART_Open() + * + * @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here. + * @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + + /** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the + * callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in + * the callback function with event UART_EVENT_RX_CHAR. + * The maximum transfer size is reported by infoGet(). + * @par Implemented as + * - @ref R_SCIF_UART_Read() + * + * @param[in] p_ctrl Pointer to the UART control block for the channel. + * @param[in] p_dest Destination address to read data from. + * @param[in] bytes Read data length. + */ + fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer + * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), + * the callback called with event UART_EVENT_TX_COMPLETE. + * The maximum transfer size is reported by infoGet(). + * @par Implemented as + * - @ref R_SCIF_UART_Write() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_src Source address to write data to. + * @param[in] bytes Write data length. + */ + fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); + + /** Change baud rate. + * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud + * settings have been applied. + * + * @par Implemented as + * - @ref R_SCIF_UART_BaudSet() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate. + */ + fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info); + + /** Get the driver specific information. + * @par Implemented as + * - @ref R_SCIF_UART_InfoGet() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] baudrate Baud rate in bps. + */ + fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); + + /** + * Abort ongoing transfer. + * @par Implemented as + * - @ref R_SCIF_UART_Abort() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] communication_to_abort Type of abort request. + */ + fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_SCIF_Uart_CallbackSet() + * + * @param[in] p_api_ctrl Pointer to the UART control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_api_ctrl, void (* p_callback)(uart_callback_args_t *), + void const * const p_context, uart_callback_args_t * const p_callback_memory); + + /** Close UART device. + * @par Implemented as + * - @ref R_SCIF_UART_Close() + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* close)(uart_ctrl_t * const p_ctrl); + + /** Stop ongoing read and return the number of bytes remaining in the read. + * @par Implemented as + * - @ref R_SCIF_UART_ReadStop() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. + */ + fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); +} uart_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_uart_instance +{ + uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + uart_api_t const * p_api; ///< Pointer to the API structure for this instance +} uart_instance_t; + +/** @} (end defgroup UART_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/drivers/rz/fsp/inc/fsp_common_api.h b/drivers/rz/fsp/inc/fsp_common_api.h new file mode 100644 index 00000000..58bdde61 --- /dev/null +++ b/drivers/rz/fsp/inc/fsp_common_api.h @@ -0,0 +1,345 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_COMMON_API_H +#define FSP_COMMON_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/* Includes FSP version macros. */ +#include "fsp_version.h" + +/*******************************************************************************************************************//** + * @ingroup RENESAS_COMMON + * @defgroup RENESAS_ERROR_CODES Common Error Codes + * All FSP modules share these common error codes. + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing + * about using this implementation is that it does not take any extra RAM or ROM. */ + +#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) + +/** Determine if a C++ compiler is being used. + * If so, ensure that standard C is used to process the API information. */ +#if defined(__cplusplus) + #define FSP_CPP_HEADER extern "C" { + #define FSP_CPP_FOOTER } +#else + #define FSP_CPP_HEADER + #define FSP_CPP_FOOTER +#endif + +/** FSP Header and Footer definitions */ +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically + * defined on the Secure side. */ +#define FSP_SECURE_ARGUMENT (NULL) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common error codes */ +typedef enum e_fsp_err +{ + FSP_SUCCESS = 0, + + FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed + FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location + FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter + FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist + FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode + FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API + FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open + FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy + FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h + FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked + FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP + FSP_ERR_OVERFLOW = 12, ///< Hardware overflow + FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow + FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration + FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result + FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason + FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met + FSP_ERR_ABORTED = 18, ///< An operation was aborted + FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled + FSP_ERR_TIMEOUT = 20, ///< Timeout error + FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied + FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied + FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation + FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed + FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed + FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made + FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition + FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU + FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state + FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed + FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed + FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete + FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found + FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback + FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer + + /* Start of RTOS only error codes */ + FSP_ERR_INTERNAL = 100, ///< Internal error + FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted + + /* Start of UART specific */ + FSP_ERR_FRAMING = 200, ///< Framing error occurs + FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects + FSP_ERR_PARITY = 202, ///< Parity error occurs + FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow + FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue + FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer + FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer + + /* Start of SPI specific */ + FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. + FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. + FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. + FSP_ERR_SPI_PARITY = 303, ///< Parity error. + FSP_ERR_OVERRUN = 304, ///< Overrun error. + + /* Start of CGC Specific */ + FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. + FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. + FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off + FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off + FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled + FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set + FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active + FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit + FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled + FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out + FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode + + /* Start of FLASH Specific */ + FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. + FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state + FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz + FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory + FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed + + /* Start of CAC Specific */ + FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate + + /* Start of GLCD Specific */ + FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock + FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter + FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter + FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found + FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter + FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer + FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update + FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry + FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting + FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter + + /* Start of JPEG Specific */ + FSP_ERR_JPEG_ERR = 1100, ///< JPEG error + FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. + FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. + FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. + FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. + FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. + FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. + FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. + FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. + FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. + FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) + FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. + FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. + FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. + FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough + FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU + + /* Start of touch panel framework specific */ + FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed + + /* Start of IP specific */ + FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device + FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device + FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device + + /* Start of USB specific */ + FSP_ERR_USB_FAILED = 1500, + FSP_ERR_USB_BUSY = 1501, + FSP_ERR_USB_SIZE_SHORT = 1502, + FSP_ERR_USB_SIZE_OVER = 1503, + FSP_ERR_USB_NOT_OPEN = 1504, + FSP_ERR_USB_NOT_SUSPEND = 1505, + FSP_ERR_USB_PARAMETER = 1506, + + /* Start of Message framework specific */ + FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool + FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool + FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid + FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid + FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many + FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found + FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue + FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue + FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal + FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released + + /* Start of 2DG Driver specific */ + FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering + FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering + + /* Start of ETHER Driver specific */ + FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. + FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled + FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty + FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable + FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication + + /* Start of ETHER_PHY Driver specific */ + FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. + FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation + + /* Start of BYTEQ library specific */ + FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data + FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue + + /* Start of CTSU Driver specific */ + FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. + FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. + FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. + + /* Start of SDMMC specific */ + FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. + FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. + FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. + FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. + FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. + FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. + FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. + + /* Start of FX_IO specific */ + FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. + FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. + + /* Start of CAN specific */ + FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. + FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. + FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. + FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. + FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. + FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. + FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. + + /* Start of SF_WIFI Specific */ + FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. + FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. + FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed + FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode + FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. + FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. + + /* Start of SF_CELLULAR Specific */ + FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. + FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. + FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed + FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate + FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed + FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. + FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. + FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed + + /* Start of SF_BLE specific */ + FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed + FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed + FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed + FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled + FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled + + /* Start of SF_BLE_ABS specific */ + FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. + FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. + + /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ + FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function + FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy + FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty + FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index + FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry + FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed + FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened + FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized + FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred + FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter + FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented + FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified + FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred + FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid + FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state + FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened + FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. + FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher + FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, + + /* Start of SF_CRYPTO specific */ + FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened + FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error + FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key + FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold + FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. + FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. + FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. + + /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. + * Refer to sf_cryoto_err.h for Crypto error codes. + */ + + /* Start of Sensor specific */ + FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. + FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. + FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. + + /* Start of COMMS specific */ + FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. +} fsp_err_t; + +/** Common version structure */ +typedef union st_fsp_version +{ + /** Version id */ + uint32_t version_id; + + /** Code version parameters */ + struct + { + uint8_t code_version_minor; ///< Code minor version + uint8_t code_version_major; ///< Code major version + uint8_t api_version_minor; ///< API minor version + uint8_t api_version_major; ///< API major version + }; +} fsp_version_t; + +/** @} */ + +/*********************************************************************************************************************** + * Function prototypes + **********************************************************************************************************************/ + +#endif diff --git a/drivers/rz/fsp/inc/fsp_version.h b/drivers/rz/fsp/inc/fsp_version.h new file mode 100644 index 00000000..2a633e55 --- /dev/null +++ b/drivers/rz/fsp/inc/fsp_version.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_VERSION_H +#define FSP_VERSION_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup RENESAS_COMMON + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** FSP pack major version. */ +#define FSP_VERSION_MAJOR (2U) + +/** FSP pack minor version. */ +#define FSP_VERSION_MINOR (1U) + +/** FSP pack patch version. */ +#define FSP_VERSION_PATCH (0U) + +/** FSP pack version build number (currently unused). */ +#define FSP_VERSION_BUILD (0U) + +/** Public FSP version name. */ +#define FSP_VERSION_STRING ("2.1.0") + +/** Unique FSP version ID. */ +#define FSP_VERSION_BUILD_STRING ("Built with RZ/G Flexible Software Package version 2.1.0") + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** FSP Pack version structure */ +typedef union st_fsp_pack_version +{ + /** Version id */ + uint32_t version_id; + + /** Code version parameters, little endian order. */ + struct + { + uint8_t build; ///< Build version of FSP Pack + uint8_t patch; ///< Patch version of FSP Pack + uint8_t minor; ///< Minor version of FSP Pack + uint8_t major; ///< Major version of FSP Pack + }; +} fsp_pack_version_t; + +/** @} */ + +#endif diff --git a/drivers/rz/fsp/inc/instances/rzg/r_ioport.h b/drivers/rz/fsp/inc/instances/rzg/r_ioport.h new file mode 100644 index 00000000..a4d9da6c --- /dev/null +++ b/drivers/rz/fsp/inc/instances/rzg/r_ioport.h @@ -0,0 +1,317 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_H +#define R_IOPORT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_ioport_api.h" +#include "r_ioport_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define IOPORT_PRV_PFS_PSEL_OFFSET (24) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ +typedef struct st_ioport_instance_ctrl +{ + uint32_t open; + void const * p_context; + ioport_cfg_t const * p_cfg; +} ioport_instance_ctrl_t; + +#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_peripheral +{ + /** Pin will function as a Mode0 peripheral pin */ + IOPORT_PERIPHERAL_MODE0 = (0x0UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode1 peripheral pin */ + IOPORT_PERIPHERAL_MODE1 = (0x1UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode2 peripheral pin */ + IOPORT_PERIPHERAL_MODE2 = (0x2UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode3 peripheral pin */ + IOPORT_PERIPHERAL_MODE3 = (0x3UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode4 peripheral pin */ + IOPORT_PERIPHERAL_MODE4 = (0x4UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode5 peripheral pin */ + IOPORT_PERIPHERAL_MODE5 = (0x5UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode6 peripheral pin */ + IOPORT_PERIPHERAL_MODE6 = (0x6UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode7 peripheral pin */ + IOPORT_PERIPHERAL_MODE7 = (0x7UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode8 peripheral pin */ + IOPORT_PERIPHERAL_MODE8 = (0x8UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode9 peripheral pin */ + IOPORT_PERIPHERAL_MODE9 = (0x9UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode10 peripheral pin */ + IOPORT_PERIPHERAL_MODE10 = (0xAUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode11 peripheral pin */ + IOPORT_PERIPHERAL_MODE11 = (0xBUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode12 peripheral pin */ + IOPORT_PERIPHERAL_MODE12 = (0xCUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode13 peripheral pin */ + IOPORT_PERIPHERAL_MODE13 = (0xDUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode14 peripheral pin */ + IOPORT_PERIPHERAL_MODE14 = (0xEUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode15 peripheral pin */ + IOPORT_PERIPHERAL_MODE15 = (0xFUL << IOPORT_PRV_PFS_PSEL_OFFSET), +} ioport_peripheral_t; + +#endif + +#ifndef BSP_OVERRIDE_IOPORT_OPTIONS_T + +/** Options to configure pin functions */ +typedef enum e_ioport_cfg_options +{ + /* For PM Register */ + IOPORT_CFG_PORT_DIRECTION_HIZ = 0x00000000, ///< Sets the pin direction to Hi-Z (default) + IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000004, ///< Sets the pin direction to input + IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000008, ///< Sets the pin direction to output (input disable) + IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT = 0x0000000C, ///< Sets the pin direction to output (input enable) + + /* For P Register */ + IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low + IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high + + /* For PUPD Register */ + IOPORT_CFG_PULLUP_PULLDOWN_DISABLE = 0x00000000, ///< Disable the pin's internal pull-up and pull-down + IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up + IOPORT_CFG_PULLDOWN_ENABLE = 0x00000020, ///< Enables the pin's internal pull-down + + /* For NOD Register */ + IOPORT_CFG_NOD_DISABLE = 0x00000000, ///< Disable the pin's N-ch open-drain + IOPORT_CFG_NOD_ENABLE = 0x00000040, ///< Enables the pin's N-ch open-drain + + /* For SMT Register */ + IOPORT_CFG_SCHMITT_DISABLE = 0x00000000, ///< Disable the pin's Schmitt-trigger input + IOPORT_CFG_SCHMITT_ENABLE = 0x80000000, ///< Enables the pin's Schmitt-trigger input + + /* For IOLH Register */ + IOPORT_CFG_DRIVE_B00 = 0x00000000, ///< Sets the IOLH register value to b'00 + IOPORT_CFG_DRIVE_B01 = 0x00000400, ///< Sets the IOLH register value to b'01 + IOPORT_CFG_DRIVE_B10 = 0x00000800, ///< Sets the IOLH register value to b'10 + IOPORT_CFG_DRIVE_B11 = 0x00000C00, ///< Sets the IOLH register value to b'11 + + /* For ISEL Register */ + IOPORT_CFG_TINT_DISABLE = 0x00000000, ///< Disable IRQ functionality for a pin + IOPORT_CFG_TINT_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin + + /* For SR Register */ + IOPORT_CFG_SLEW_RATE_SLOW = 0x00000000, ///< Sets the pin slew-rate to slow + IOPORT_CFG_SLEW_RATE_FAST = 0x00020000, ///< Sets the pin slew-rate to fast + + /* For IEN Register */ + IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_DISABLE = 0x00000000, ///< Disable input the pin of special purpose port + IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_ENABLE = 0x00040000, ///< Sets the pin of special purpose port to input + + /* For FILONOFF Register */ + IOPORT_CFG_NOISE_FILTER_OFF = 0x00000000, ///< Noise filter disable + IOPORT_CFG_NOISE_FILTER_ON = 0x00080000, ///< Noise filter enable + + /* For FILNUM Register */ + IOPORT_CFG_NOISE_FILTER_NUM_4STAGE = 0x00000000, ///< Sets the pin noise filter to 4-stage filter + IOPORT_CFG_NOISE_FILTER_NUM_8STAGE = 0x00100000, ///< Sets the pin noise filter to 8-stage filter + IOPORT_CFG_NOISE_FILTER_NUM_12STAGE = 0x00200000, ///< Sets the pin noise filter to 12-stage filter + IOPORT_CFG_NOISE_FILTER_NUM_16STAGE = 0x00300000, ///< Sets the pin noise filter to 16-stage filter + + /* For FILCLKSEL Register */ + IOPORT_CFG_NOISE_FILTER_DIVIDED_B00 = 0x00000000, ///< Sets the FILCLKSEL register value to b'00 + IOPORT_CFG_NOISE_FILTER_DIVIDED_B01 = 0x00400000, ///< Sets the FILCLKSEL register value to b'01 + IOPORT_CFG_NOISE_FILTER_DIVIDED_B10 = 0x00800000, ///< Sets the FILCLKSEL register value to b'10 + IOPORT_CFG_NOISE_FILTER_DIVIDED_B11 = 0x00C00000, ///< Sets the FILCLKSEL register value to b'11 + + /* For PMC Register */ + IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin +} ioport_cfg_options_t; + +#endif + +/** Pin selection for port group + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_pin_selection +{ + IOPORT_EVENT_PIN_SELECTION_NONE = 0x00, ///< No pin selection for port group + IOPORT_EVENT_PIN_SELECTION_PIN_0 = 0x01, ///< Select pin 0 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_1 = 0x02, ///< Select pin 1 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_2 = 0x04, ///< Select pin 2 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_3 = 0x08, ///< Select pin 3 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_4 = 0x10, ///< Select pin 4 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_5 = 0x20, ///< Select pin 5 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_6 = 0x40, ///< Select pin 6 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_7 = 0x80, ///< Select pin 7 to port group +} ioport_event_pin_selection_t; + +/** Port group operation + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_output_operation +{ + IOPORT_EVENT_OUTPUT_OPERATION_LOW = 0x0, ///< Set Low output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_HIGH = 0x1, ///< Set High output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_TOGGLE = 0x2, ///< Set toggle output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_BUFFER = 0x3, ///< Set buffer value output to output operation +} ioport_event_output_operation_t; + +/** Input port group event control + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_control +{ + IOPORT_EVENT_CONTROL_DISABLE = 0x0, ///< Disable function related with event link + IOPORT_EVENT_CONTROL_ENABLE = 0x1, ///< Enable function related with event link +} ioport_event_control_t; + +/** Single port event direction + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_direction +{ + IOPORT_EVENT_DIRECTION_OUTPUT = 0x0, ///< Set output direction to single port + IOPORT_EVENT_DIRECTION_INPUT = 0x1, ///< Set input direction to single port +} ioport_event_direction_t; + +/** Input event edge detection + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_detection +{ + IOPORT_EVENT_DETECTION_RISING_EDGE = 0x0, ///< Set rising edge to event detection for input event + IOPORT_EVENT_DETECTION_FALLING_EDGE = 0x1, ///< Set falling edge to event detection for input event + IOPORT_EVENT_DETECTION_BOTH_EGDE = 0x2, ///< Set both edges to event detection for input event +} ioport_event_detection_t; + +/** Initial value for buffer register + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_initial_buffer_value +{ + IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW = 0U, ///< Set low to initial value of buffer register for input port group + IOPORT_EVENT_INITIAL_BUFFER_VALUE_HIGH = 1U, ///< Set high to initial value of buffer register for input port group +} ioport_event_initial_buffer_value_t; + +/** Single port configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_single +{ + ioport_event_control_t event_control; ///< Event link control for single port + ioport_event_direction_t direction; ///< Event direction for single port + uint16_t port_num; ///< Port number specified to single port + ioport_event_output_operation_t operation; ///< Single port operation select + ioport_event_detection_t edge_detection; ///< Edge detection select +} ioport_event_single_t; + +/** Output port group configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_group_output +{ + uint8_t pin_select; ///< Port number specified to output port group + ioport_event_output_operation_t operation; ///< Port group operation select +} ioport_event_group_output_t; + +/** Input port group configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_group_input +{ + ioport_event_control_t event_control; ///< Event link control for input port group + ioport_event_detection_t edge_detection; ///< Edge detection select + ioport_event_control_t overwrite_control; ///< Buffer register overwrite control + uint8_t pin_select; ///< Port number specified to input port group + uint8_t buffer_init_value; ///< Buffer register initial value +} ioport_event_group_input_t; + +/** IOPORT extended configuration for event link function + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_extend_cfg +{ + ioport_event_group_output_t const * p_port_group_output_cfg; ///< Pointer to output port group configuration + ioport_event_group_input_t const * p_port_group_input_cfg; ///< Pointer to input port group configuration + ioport_event_single_t const * p_single_port_cfg; ///< Pointer to single input port configuration +} ioport_extend_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ioport_api_t g_ioport_on_ioport; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); +fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); +fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); +fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); +fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); +fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); +fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask); +fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); +fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value); +fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); +fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IOPORT_H diff --git a/drivers/rz/fsp/inc/instances/rzg/r_scif_uart.h b/drivers/rz/fsp/inc/instances/rzg/r_scif_uart.h new file mode 100644 index 00000000..d617ff82 --- /dev/null +++ b/drivers/rz/fsp/inc/instances/rzg/r_scif_uart.h @@ -0,0 +1,228 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCIF_UART_H +#define R_SCIF_UART_H + +/*******************************************************************************************************************//** + * @addtogroup SCIF_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_scif_uart_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define SCIF_UART_INVALID_16BIT_PARAM (0xFFFFU) +#define SCIF_UART_INVALID_8BIT_PARAM (0xFFU) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for SCIF clock source */ +typedef enum e_scif_clk_src +{ + SCIF_UART_CLOCK_INT, ///< Use internal clock for baud generation + SCIF_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK + SCIF_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate + SCIF_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate +} scif_clk_src_t; + +/** UART communication mode definition */ +typedef enum e_scif_uart_mode +{ + SCIF_UART_MODE_RS232, ///< Enables RS232 communication mode + SCIF_UART_MODE_RS485_HD, ///< Enables RS485 half duplex communication mode + SCIF_UART_MODE_RS485_FD, ///< Enables RS485 full duplex communication mode +} scif_uart_mode_t; + +/** UART automatic flow control definition */ +typedef enum e_scif_uart_flow_control +{ + SCIF_UART_FLOW_CONTROL_NONE, ///< Disables flow control + SCIF_UART_FLOW_CONTROL_AUTO, ///< Enables automatic RTS/CTS flow control +} scif_uart_flow_control_t; + +/** Noise cancellation configuration. */ +typedef enum e_scif_uart_noise_cancellation +{ + SCIF_UART_NOISE_CANCELLATION_DISABLE, ///< Disable noise cancellation + SCIF_UART_NOISE_CANCELLATION_ENABLE, ///< Enable noise cancellation +} scif_uart_noise_cancellation_t; + +/** RS-485 Enable/Disable. */ +typedef enum e_sci_uart_rs485_enable +{ + SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled. + SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled. +} sci_uart_rs485_enable_t; + +/** The polarity of the RS-485 DE signal. */ +typedef enum e_sci_uart_rs485_de_polarity +{ + SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. + SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. +} sci_uart_rs485_de_polarity_t; + +/** Receive FIFO trigger configuration. */ +typedef enum e_scif_uart_receive_trigger +{ + SCIF_UART_RECEIVE_TRIGGER_ONE, ///< Interrupt at least one byte is in FIFO + SCIF_UART_RECEIVE_TRIGGER_QUARTER, ///< Interrupt at least quarter of FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_HALF, ///< Interrupt at least half of FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_MAX, ///< Interrupt at almost full in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_1, ///< Interrupt at least 1 byte is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_2, ///< Interrupt at least 2 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_3, ///< Interrupt at least 3 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_4, ///< Interrupt at least 4 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_5, ///< Interrupt at least 5 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_6, ///< Interrupt at least 6 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_7, ///< Interrupt at least 7 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_8, ///< Interrupt at least 8 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_9, ///< Interrupt at least 9 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_10, ///< Interrupt at least 10 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_11, ///< Interrupt at least 11 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_12, ///< Interrupt at least 12 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_13, ///< Interrupt at least 13 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_14, ///< Interrupt at least 14 bytes is in FIFO or 15ETU past from last receive + SCIF_UART_RECEIVE_TRIGGER_15, ///< Interrupt at least 15 bytes is in FIFO or 15ETU past from last receive +} scif_uart_receive_trigger_t; + +/** RTS trigger level. */ +typedef enum e_scif_uart_rts_trigger +{ + SCIF_UART_RTS_TRIGGER_1, ///< RTS trigger level = 1 + SCIF_UART_RTS_TRIGGER_4, ///< RTS trigger level = 4 + SCIF_UART_RTS_TRIGGER_6, ///< RTS trigger level = 6 + SCIF_UART_RTS_TRIGGER_8, ///< RTS trigger level = 8 + SCIF_UART_RTS_TRIGGER_10, ///< RTS trigger level = 10 + SCIF_UART_RTS_TRIGGER_12, ///< RTS trigger level = 12 + SCIF_UART_RTS_TRIGGER_14, ///< RTS trigger level = 14 + SCIF_UART_RTS_TRIGGER_15, ///< RTS trigger level = 15 +} scif_uart_rts_trigger_t; + +/** UART instance control block. */ +typedef struct st_scif_uart_instance_ctrl +{ + /* Parameters to control UART peripheral device */ + uint32_t open; // Used to determine if the channel is configured + + bsp_io_port_pin_t driver_enable_pin; + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Base register for this channel */ + R_SCIFA0_Type * p_reg; + + /* Backup SPTR value for writing */ + uint16_t sptr; + + void (* p_callback)(uart_callback_args_t * p_arg); // Pointer to callback + uart_callback_args_t * p_callback_memory; // Pointer to pre-allocated callback argument + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} scif_uart_instance_ctrl_t; + +/** Register settings to achieve a desired baud rate and modulation duty. */ +typedef struct st_scif_baud_setting +{ + struct + { + uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select + uint8_t brme : 1; ///< Bit Rate Modulation Enable + uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select + uint8_t cks : 2; ///< CKS value to get divisor (CKS = N) + } semr_baudrate_bits_b; + uint8_t brr; ///< Bit Rate Register setting + uint8_t mddr; ///< Modulation Duty Register setting +} scif_baud_setting_t; + +/** Configuration settings for controlling the DE signal for RS-485. */ +typedef struct st_sci_uart_rs485_setting +{ + sci_uart_rs485_enable_t enable; ///< Enable the DE signal. + sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. + bsp_io_port_pin_t de_control_pin; ///< UART Driver Enable pin. +} sci_uart_rs485_setting_t; + +/** UART on SCIF device Configuration */ +typedef struct st_scif_uart_extended_cfg +{ + uint8_t bri_ipl; ///< Break interrupt priority + IRQn_Type bri_irq; ///< Break interrupt IRQ number + scif_clk_src_t clock; ///< The source clock for the baud-rate generator. + scif_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting + + scif_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + + scif_uart_receive_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level. + scif_uart_rts_trigger_t rts_fifo_trigger; ///< RTS trigger level. + + scif_uart_mode_t uart_mode; ///< UART communication mode selection + scif_uart_flow_control_t flow_control; ///< CTS/RTS function + sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. +} scif_uart_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_scif; + +/** @endcond */ + +fsp_err_t R_SCIF_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_SCIF_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SCIF_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SCIF_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_SCIF_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); +fsp_err_t R_SCIF_UART_Close(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCIF_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_SCIF_UART_BaudCalculate(uart_ctrl_t * const p_api_ctrl, + uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + scif_baud_setting_t * const p_baud_setting); +fsp_err_t R_SCIF_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t * p_arg), + void const * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_SCIF_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); + +/*******************************************************************************************************************//** + * @} (end addtogroup SCIF_UART) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_SCIF_UART_H */ diff --git a/drivers/rz/fsp/src/rzg/CMakeLists.txt b/drivers/rz/fsp/src/rzg/CMakeLists.txt new file mode 100644 index 00000000..f6edff46 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(srcs + bsp/mcu/all/bsp_clocks.c + bsp/mcu/all/bsp_delay.c + bsp/mcu/all/bsp_irq.c + bsp/mcu/all/bsp_io.c +) + +zephyr_library_sources(${srcs}) diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S.h new file mode 100644 index 00000000..1cd77995 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S.h @@ -0,0 +1,151 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* + * @file R9A08G045S.h + * @brief CMSIS HeaderFile + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R9A08G045S + * @{ + */ + +#ifndef R9A08G045S_H + #define R9A08G045S_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 7 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #if BSP_FEATURE_MCORE_HAS_FPU + #define __FPU_PRESENT 1 /*!< FPU present */ + #else + #define __FPU_PRESENT 0 /*!< FPU present */ + #endif + #define __FPU_DP 0 /*!< Double Precision FPU */ + #if BSP_FEATURE_MCORE_HAS_DSP + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #else + #define __DSP_PRESENT 0 /*!< DSP extension present */ + #endif + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R9A08G045S System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + #include "R9A08G045S/iodefine.h" + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* ========================================= End of section using anonymous unions =============================== */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + #include "R9A08G045S/iobitmask.h" + +/** @} */ /* End of group PosMask_clusters */ + + #ifdef __cplusplus +} + #endif + +#endif /* R9A08G045S_H */ + +/** @} */ /* End of group R9A08G045S */ + +/** @} */ /* End of group Renesas */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmask.h new file mode 100644 index 00000000..fa2c7b2c --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmask.h @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : iobitmask.h + * Version : 1.00 + * Description : iobitmask header + *********************************************************************************************************************/ + +#ifndef __IOBITMASK_HEADER__ +#define __IOBITMASK_HEADER__ + +#include "iobitmasks/adc_c_iobitmask.h" +#include "iobitmasks/cpg_iobitmask.h" +#include "iobitmasks/canfd_iobitmask.h" +#include "iobitmasks/dmac_b_iobitmask.h" +#include "iobitmasks/gpio_iobitmask.h" +#include "iobitmasks/gpt_iobitmask.h" +#include "iobitmasks/gtm_iobitmask.h" +#include "iobitmasks/intc_im33_iobitmask.h" +#include "iobitmasks/mhu_iobitmask.h" +#include "iobitmasks/poeg_iobitmask.h" +#include "iobitmasks/riic_iobitmask.h" +#include "iobitmasks/rspi_iobitmask.h" +#include "iobitmasks/scifa_iobitmask.h" +#include "iobitmasks/ssi_iobitmask.h" +#include "iobitmasks/sysc_iobitmask.h" +#include "iobitmasks/tsu_iobitmask.h" +#include "iobitmasks/tzc_iobitmask.h" +#include "iobitmasks/wdt_iobitmask.h" +#include "iobitmasks/xspi_iobitmask.h" + +#ifdef BSP_OVERRIDE_MASK_HEADER_IOPORT + #include BSP_OVERRIDE_MASK_HEADER_IOPORT +#endif + +#endif /* __IOBITMASK_HEADER__ */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/adc_c_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/adc_c_iobitmask.h new file mode 100644 index 00000000..e6abc358 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/adc_c_iobitmask.h @@ -0,0 +1,353 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : adc_c_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for adc_c. + *********************************************************************************************************************/ + +#ifndef ADC_C_IOBITMASK_H +#define ADC_C_IOBITMASK_H + +#define R_ADC_C_ADM0_ADCE_Msk (0x00000001UL) +#define R_ADC_C_ADM0_ADCE_Pos (0UL) +#define R_ADC_C_ADM0_ADBSY_Msk (0x00000002UL) +#define R_ADC_C_ADM0_ADBSY_Pos (1UL) +#define R_ADC_C_ADM0_PWDWNB_Msk (0x00000004UL) +#define R_ADC_C_ADM0_PWDWNB_Pos (2UL) +#define R_ADC_C_ADM0_SRESB_Msk (0x00008000UL) +#define R_ADC_C_ADM0_SRESB_Pos (15UL) +#define R_ADC_C_ADM1_TRG_Msk (0x00000001UL) +#define R_ADC_C_ADM1_TRG_Pos (0UL) +#define R_ADC_C_ADM1_TRGIN_Msk (0x00000002UL) +#define R_ADC_C_ADM1_TRGIN_Pos (1UL) +#define R_ADC_C_ADM1_MS_Msk (0x00000004UL) +#define R_ADC_C_ADM1_MS_Pos (2UL) +#define R_ADC_C_ADM1_RPS_Msk (0x00000008UL) +#define R_ADC_C_ADM1_RPS_Pos (3UL) +#define R_ADC_C_ADM1_BS_Msk (0x00000010UL) +#define R_ADC_C_ADM1_BS_Pos (4UL) +#define R_ADC_C_ADM1_EGA_Msk (0x00003000UL) +#define R_ADC_C_ADM1_EGA_Pos (12UL) +#define R_ADC_C_ADM1_TRGEN_Msk (0x003F0000UL) +#define R_ADC_C_ADM1_TRGEN_Pos (16UL) +#define R_ADC_C_ADM2_CHSEL_Msk (0x000001FFUL) +#define R_ADC_C_ADM2_CHSEL_Pos (0UL) +#define R_ADC_C_ADM3_ADSMP_Msk (0x000000FFUL) +#define R_ADC_C_ADM3_ADSMP_Pos (0UL) +#define R_ADC_C_ADM3_ADCMP_Msk (0x00FF0000UL) +#define R_ADC_C_ADM3_ADCMP_Pos (16UL) +#define R_ADC_C_ADM3_ADIL_Msk (0xFF000000UL) +#define R_ADC_C_ADM3_ADIL_Pos (24UL) +#define R_ADC_C_TSUMODE_TSUEN_Msk (0x00000002UL) +#define R_ADC_C_TSUMODE_TSUEN_Pos (1UL) +#define R_ADC_C_ADINT_INTEN_Msk (0x00000FFFUL) +#define R_ADC_C_ADINT_INTEN_Pos (0UL) +#define R_ADC_C_ADINT_CSEEN_Msk (0x00010000UL) +#define R_ADC_C_ADINT_CSEEN_Pos (16UL) +#define R_ADC_C_ADINT_INTS_Msk (0x80000000UL) +#define R_ADC_C_ADINT_INTS_Pos (31UL) +#define R_ADC_C_ADSTS_INTST_Msk (0x000001FFUL) +#define R_ADC_C_ADSTS_INTST_Pos (0UL) +#define R_ADC_C_ADSTS_CSEST_Msk (0x00010000UL) +#define R_ADC_C_ADSTS_CSEST_Pos (16UL) +#define R_ADC_C_ADSTS_TRGS_Msk (0x80000000UL) +#define R_ADC_C_ADSTS_TRGS_Pos (31UL) +#define R_ADC_C_ADFIL_FILONOFF_Msk (0x00000001UL) +#define R_ADC_C_ADFIL_FILONOFF_Pos (0UL) +#define R_ADC_C_ADFIL_FILNUM_Msk (0x00000030UL) +#define R_ADC_C_ADFIL_FILNUM_Pos (4UL) +#define R_ADC_C_ADCR0_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR0_AD0_Pos (0UL) +#define R_ADC_C_ADCR0_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR0_AD1_Pos (1UL) +#define R_ADC_C_ADCR0_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR0_AD2_Pos (2UL) +#define R_ADC_C_ADCR0_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR0_AD3_Pos (3UL) +#define R_ADC_C_ADCR0_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR0_AD4_Pos (4UL) +#define R_ADC_C_ADCR0_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR0_AD5_Pos (5UL) +#define R_ADC_C_ADCR0_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR0_AD6_Pos (6UL) +#define R_ADC_C_ADCR0_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR0_AD7_Pos (7UL) +#define R_ADC_C_ADCR0_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR0_AD8_Pos (8UL) +#define R_ADC_C_ADCR0_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR0_AD9_Pos (9UL) +#define R_ADC_C_ADCR0_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR0_AD10_Pos (10UL) +#define R_ADC_C_ADCR0_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR0_AD11_Pos (11UL) +#define R_ADC_C_ADCR1_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR1_AD0_Pos (0UL) +#define R_ADC_C_ADCR1_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR1_AD1_Pos (1UL) +#define R_ADC_C_ADCR1_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR1_AD2_Pos (2UL) +#define R_ADC_C_ADCR1_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR1_AD3_Pos (3UL) +#define R_ADC_C_ADCR1_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR1_AD4_Pos (4UL) +#define R_ADC_C_ADCR1_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR1_AD5_Pos (5UL) +#define R_ADC_C_ADCR1_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR1_AD6_Pos (6UL) +#define R_ADC_C_ADCR1_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR1_AD7_Pos (7UL) +#define R_ADC_C_ADCR1_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR1_AD8_Pos (8UL) +#define R_ADC_C_ADCR1_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR1_AD9_Pos (9UL) +#define R_ADC_C_ADCR1_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR1_AD10_Pos (10UL) +#define R_ADC_C_ADCR1_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR1_AD11_Pos (11UL) +#define R_ADC_C_ADCR2_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR2_AD0_Pos (0UL) +#define R_ADC_C_ADCR2_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR2_AD1_Pos (1UL) +#define R_ADC_C_ADCR2_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR2_AD2_Pos (2UL) +#define R_ADC_C_ADCR2_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR2_AD3_Pos (3UL) +#define R_ADC_C_ADCR2_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR2_AD4_Pos (4UL) +#define R_ADC_C_ADCR2_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR2_AD5_Pos (5UL) +#define R_ADC_C_ADCR2_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR2_AD6_Pos (6UL) +#define R_ADC_C_ADCR2_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR2_AD7_Pos (7UL) +#define R_ADC_C_ADCR2_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR2_AD8_Pos (8UL) +#define R_ADC_C_ADCR2_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR2_AD9_Pos (9UL) +#define R_ADC_C_ADCR2_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR2_AD10_Pos (10UL) +#define R_ADC_C_ADCR2_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR2_AD11_Pos (11UL) +#define R_ADC_C_ADCR3_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR3_AD0_Pos (0UL) +#define R_ADC_C_ADCR3_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR3_AD1_Pos (1UL) +#define R_ADC_C_ADCR3_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR3_AD2_Pos (2UL) +#define R_ADC_C_ADCR3_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR3_AD3_Pos (3UL) +#define R_ADC_C_ADCR3_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR3_AD4_Pos (4UL) +#define R_ADC_C_ADCR3_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR3_AD5_Pos (5UL) +#define R_ADC_C_ADCR3_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR3_AD6_Pos (6UL) +#define R_ADC_C_ADCR3_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR3_AD7_Pos (7UL) +#define R_ADC_C_ADCR3_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR3_AD8_Pos (8UL) +#define R_ADC_C_ADCR3_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR3_AD9_Pos (9UL) +#define R_ADC_C_ADCR3_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR3_AD10_Pos (10UL) +#define R_ADC_C_ADCR3_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR3_AD11_Pos (11UL) +#define R_ADC_C_ADCR4_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR4_AD0_Pos (0UL) +#define R_ADC_C_ADCR4_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR4_AD1_Pos (1UL) +#define R_ADC_C_ADCR4_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR4_AD2_Pos (2UL) +#define R_ADC_C_ADCR4_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR4_AD3_Pos (3UL) +#define R_ADC_C_ADCR4_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR4_AD4_Pos (4UL) +#define R_ADC_C_ADCR4_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR4_AD5_Pos (5UL) +#define R_ADC_C_ADCR4_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR4_AD6_Pos (6UL) +#define R_ADC_C_ADCR4_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR4_AD7_Pos (7UL) +#define R_ADC_C_ADCR4_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR4_AD8_Pos (8UL) +#define R_ADC_C_ADCR4_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR4_AD9_Pos (9UL) +#define R_ADC_C_ADCR4_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR4_AD10_Pos (10UL) +#define R_ADC_C_ADCR4_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR4_AD11_Pos (11UL) +#define R_ADC_C_ADCR5_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR5_AD0_Pos (0UL) +#define R_ADC_C_ADCR5_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR5_AD1_Pos (1UL) +#define R_ADC_C_ADCR5_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR5_AD2_Pos (2UL) +#define R_ADC_C_ADCR5_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR5_AD3_Pos (3UL) +#define R_ADC_C_ADCR5_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR5_AD4_Pos (4UL) +#define R_ADC_C_ADCR5_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR5_AD5_Pos (5UL) +#define R_ADC_C_ADCR5_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR5_AD6_Pos (6UL) +#define R_ADC_C_ADCR5_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR5_AD7_Pos (7UL) +#define R_ADC_C_ADCR5_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR5_AD8_Pos (8UL) +#define R_ADC_C_ADCR5_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR5_AD9_Pos (9UL) +#define R_ADC_C_ADCR5_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR5_AD10_Pos (10UL) +#define R_ADC_C_ADCR5_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR5_AD11_Pos (11UL) +#define R_ADC_C_ADCR6_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR6_AD0_Pos (0UL) +#define R_ADC_C_ADCR6_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR6_AD1_Pos (1UL) +#define R_ADC_C_ADCR6_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR6_AD2_Pos (2UL) +#define R_ADC_C_ADCR6_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR6_AD3_Pos (3UL) +#define R_ADC_C_ADCR6_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR6_AD4_Pos (4UL) +#define R_ADC_C_ADCR6_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR6_AD5_Pos (5UL) +#define R_ADC_C_ADCR6_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR6_AD6_Pos (6UL) +#define R_ADC_C_ADCR6_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR6_AD7_Pos (7UL) +#define R_ADC_C_ADCR6_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR6_AD8_Pos (8UL) +#define R_ADC_C_ADCR6_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR6_AD9_Pos (9UL) +#define R_ADC_C_ADCR6_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR6_AD10_Pos (10UL) +#define R_ADC_C_ADCR6_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR6_AD11_Pos (11UL) +#define R_ADC_C_ADCR7_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR7_AD0_Pos (0UL) +#define R_ADC_C_ADCR7_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR7_AD1_Pos (1UL) +#define R_ADC_C_ADCR7_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR7_AD2_Pos (2UL) +#define R_ADC_C_ADCR7_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR7_AD3_Pos (3UL) +#define R_ADC_C_ADCR7_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR7_AD4_Pos (4UL) +#define R_ADC_C_ADCR7_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR7_AD5_Pos (5UL) +#define R_ADC_C_ADCR7_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR7_AD6_Pos (6UL) +#define R_ADC_C_ADCR7_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR7_AD7_Pos (7UL) +#define R_ADC_C_ADCR7_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR7_AD8_Pos (8UL) +#define R_ADC_C_ADCR7_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR7_AD9_Pos (9UL) +#define R_ADC_C_ADCR7_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR7_AD10_Pos (10UL) +#define R_ADC_C_ADCR7_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR7_AD11_Pos (11UL) +#define R_ADC_C_ADCR8_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR8_AD0_Pos (0UL) +#define R_ADC_C_ADCR8_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR8_AD1_Pos (1UL) +#define R_ADC_C_ADCR8_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR8_AD2_Pos (2UL) +#define R_ADC_C_ADCR8_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR8_AD3_Pos (3UL) +#define R_ADC_C_ADCR8_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR8_AD4_Pos (4UL) +#define R_ADC_C_ADCR8_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR8_AD5_Pos (5UL) +#define R_ADC_C_ADCR8_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR8_AD6_Pos (6UL) +#define R_ADC_C_ADCR8_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR8_AD7_Pos (7UL) +#define R_ADC_C_ADCR8_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR8_AD8_Pos (8UL) +#define R_ADC_C_ADCR8_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR8_AD9_Pos (9UL) +#define R_ADC_C_ADCR8_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR8_AD10_Pos (10UL) +#define R_ADC_C_ADCR8_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR8_AD11_Pos (11UL) +#define R_ADC_C_ADCR9_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR9_AD0_Pos (0UL) +#define R_ADC_C_ADCR9_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR9_AD1_Pos (1UL) +#define R_ADC_C_ADCR9_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR9_AD2_Pos (2UL) +#define R_ADC_C_ADCR9_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR9_AD3_Pos (3UL) +#define R_ADC_C_ADCR9_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR9_AD4_Pos (4UL) +#define R_ADC_C_ADCR9_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR9_AD5_Pos (5UL) +#define R_ADC_C_ADCR9_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR9_AD6_Pos (6UL) +#define R_ADC_C_ADCR9_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR9_AD7_Pos (7UL) +#define R_ADC_C_ADCR9_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR9_AD8_Pos (8UL) +#define R_ADC_C_ADCR9_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR9_AD9_Pos (9UL) +#define R_ADC_C_ADCR9_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR9_AD10_Pos (10UL) +#define R_ADC_C_ADCR9_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR9_AD11_Pos (11UL) +#define R_ADC_C_ADCR10_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR10_AD0_Pos (0UL) +#define R_ADC_C_ADCR10_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR10_AD1_Pos (1UL) +#define R_ADC_C_ADCR10_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR10_AD2_Pos (2UL) +#define R_ADC_C_ADCR10_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR10_AD3_Pos (3UL) +#define R_ADC_C_ADCR10_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR10_AD4_Pos (4UL) +#define R_ADC_C_ADCR10_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR10_AD5_Pos (5UL) +#define R_ADC_C_ADCR10_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR10_AD6_Pos (6UL) +#define R_ADC_C_ADCR10_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR10_AD7_Pos (7UL) +#define R_ADC_C_ADCR10_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR10_AD8_Pos (8UL) +#define R_ADC_C_ADCR10_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR10_AD9_Pos (9UL) +#define R_ADC_C_ADCR10_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR10_AD10_Pos (10UL) +#define R_ADC_C_ADCR10_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR10_AD11_Pos (11UL) +#define R_ADC_C_ADCR11_AD0_Msk (0x00000001UL) +#define R_ADC_C_ADCR11_AD0_Pos (0UL) +#define R_ADC_C_ADCR11_AD1_Msk (0x00000002UL) +#define R_ADC_C_ADCR11_AD1_Pos (1UL) +#define R_ADC_C_ADCR11_AD2_Msk (0x00000004UL) +#define R_ADC_C_ADCR11_AD2_Pos (2UL) +#define R_ADC_C_ADCR11_AD3_Msk (0x00000008UL) +#define R_ADC_C_ADCR11_AD3_Pos (3UL) +#define R_ADC_C_ADCR11_AD4_Msk (0x00000010UL) +#define R_ADC_C_ADCR11_AD4_Pos (4UL) +#define R_ADC_C_ADCR11_AD5_Msk (0x00000020UL) +#define R_ADC_C_ADCR11_AD5_Pos (5UL) +#define R_ADC_C_ADCR11_AD6_Msk (0x00000040UL) +#define R_ADC_C_ADCR11_AD6_Pos (6UL) +#define R_ADC_C_ADCR11_AD7_Msk (0x00000080UL) +#define R_ADC_C_ADCR11_AD7_Pos (7UL) +#define R_ADC_C_ADCR11_AD8_Msk (0x00000100UL) +#define R_ADC_C_ADCR11_AD8_Pos (8UL) +#define R_ADC_C_ADCR11_AD9_Msk (0x00000200UL) +#define R_ADC_C_ADCR11_AD9_Pos (9UL) +#define R_ADC_C_ADCR11_AD10_Msk (0x00000400UL) +#define R_ADC_C_ADCR11_AD10_Pos (10UL) +#define R_ADC_C_ADCR11_AD11_Msk (0x00000800UL) +#define R_ADC_C_ADCR11_AD11_Pos (11UL) + +#endif /* ADC_C_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/canfd_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/canfd_iobitmask.h new file mode 100644 index 00000000..b2bbf3fe --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/canfd_iobitmask.h @@ -0,0 +1,1003 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : canfd_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for canfd. + *********************************************************************************************************************/ + +#ifndef CANFD_IOBITMASK_H +#define CANFD_IOBITMASK_H + +/* ========================================================= NCFG ========================================================== */ +#define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ +#define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ +#define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ +#define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ +#define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ +#define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ +#define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ +#define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ +#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ +#define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ +#define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ +#define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ +#define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ +#define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ +#define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ +#define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ +#define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ +#define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ +#define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ +#define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ +#define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ +#define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ +#define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ +#define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ +#define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ +#define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ +#define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ +#define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ +#define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ +#define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ +#define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ +#define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ +#define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ +#define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ +#define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ +#define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ +#define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ +#define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ +#define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ +#define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ +#define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ +#define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ +#define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ +#define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ +#define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ +#define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ +#define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ +#define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ +#define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ +#define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ +#define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ +#define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ +#define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ +#define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ +#define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ +#define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ +#define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ +#define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ +#define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ +#define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ +#define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ +#define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ +#define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ +#define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ +#define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ +#define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ +#define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ +#define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ +#define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ +#define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ +#define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ +#define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ +#define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ +#define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ +#define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ +#define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ +#define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ +#define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ +#define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ +#define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ +#define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ +#define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ +#define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ +#define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ +#define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ +#define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ +#define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ +#define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ +#define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ +/* ========================================================= BLCT ========================================================== */ +#define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ +#define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ +#define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ +/* ========================================================= BLSTS ========================================================= */ +#define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ +#define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ +#define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ +#define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ +#define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ +#define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ +#define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ +#define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ +#define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ +#define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ +#define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ +#define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ +#define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ +#define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ +#define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ +#define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ +#define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ +#define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ +#define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ +#define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ +#define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ +#define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x7f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ +#define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ +#define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ +#define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ +#define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ +#define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ +#define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ +#define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ +#define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ +#define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ +#define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ +#define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ +#define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ +#define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ +#define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ +#define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ +#define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ +#define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ +#define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ +#define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ +#define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ +#define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ +#define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ +#define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ +#define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ +#define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ +#define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ +#define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ +#define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ +#define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ +#define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ +#define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ +#define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ +#define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ +#define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ +#define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ +#define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ +#define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ +#define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ +#define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ +#define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ +#define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ +#define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ +#define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ +#define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ +#define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ +#define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ +#define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ +#define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ +#define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ +#define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ +#define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ +#define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ +#define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ +#define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ +#define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ +#define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ +#define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ +#define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ +#define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ +#define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ +#define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ +#define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ +#define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ +#define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ +#define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ +#define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ +#define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ +#define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ +#define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ +#define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ +#define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ +#define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ +#define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ +#define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ +#define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ +#define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ +#define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ +#define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ +#define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ +#define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ +#define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ +#define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ +#define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGIPV ======================================================== */ +#define R_CANFD_CFDGIPV_IPV_Pos (0UL) /*!< IPV (Bit 0) */ +#define R_CANFD_CFDGIPV_IPV_Msk (0xffUL) /*!< IPV (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDGIPV_IPT_Pos (8UL) /*!< IPT (Bit 8) */ +#define R_CANFD_CFDGIPV_IPT_Msk (0x300UL) /*!< IPT (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDGIPV_PSI_Pos (16UL) /*!< PSI (Bit 16) */ +#define R_CANFD_CFDGIPV_PSI_Msk (0x3fff0000UL) /*!< PSI (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CFDGCFG ======================================================== */ +#define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ +#define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ +#define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ +#define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ +#define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ +#define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ +#define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ +#define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ +#define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ +#define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ +#define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ +#define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ +#define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ +#define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ +#define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ +#define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ +#define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ +#define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ +#define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCTR_QOWEIE_Pos (12UL) /*!< QOWEIE (Bit 12) */ +#define R_CANFD_CFDGCTR_QOWEIE_Msk (0x1000UL) /*!< QOWEIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ +#define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ +#define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ +#define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ +#define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ +#define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ +#define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ +#define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ +#define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ +#define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ +#define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ +#define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ +#define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ +#define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ +#define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ +#define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGERFL_MOWES_Pos (7UL) /*!< MOWES (Bit 7) */ +#define R_CANFD_CFDGERFL_MOWES_Msk (0x80UL) /*!< MOWES (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ +#define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ +#define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ +#define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ +#define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ +#define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ +#define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0x3fUL) /*!< AFLPN (Bitfield-Mask: 0x03f) */ +#define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ +#define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ +#define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ +#define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ +#define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ +#define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ +#define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ +#define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ +#define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ +#define R_CANFD_CFDRMND0_RMNS_Pos (0UL) /*!< RMNS (Bit 0) */ +#define R_CANFD_CFDRMND0_RMNS_Msk (0xffffffffUL) /*!< RMNS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ +#define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ +#define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ +#define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ +#define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ +#define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ +#define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ +#define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ +#define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFSTS ======================================================== */ +#define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ +#define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ +#define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ +#define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ +#define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ +#define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ +#define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFPCTR ======================================================= */ +#define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ +#define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ +#define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ +#define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ +#define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ +#define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ +#define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ +#define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ +#define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ +#define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ +#define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ +#define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ +#define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ +#define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ +#define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ +#define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFCCE ======================================================== */ +#define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ +#define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ +#define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ +#define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ +#define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ +#define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFSTS ======================================================== */ +#define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ +#define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ +#define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ +#define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ +#define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ +#define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ +#define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ +#define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ +#define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ +#define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ +#define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFPCTR ======================================================= */ +#define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ +#define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ +#define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ +#define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ +#define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFSTS ======================================================== */ +#define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ +#define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ +#define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFMSTS ======================================================== */ +#define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ +#define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ +#define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDRFISTS ======================================================= */ +#define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ +#define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ +#define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDCFRISTS ======================================================= */ +#define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ +#define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFTISTS ======================================================= */ +#define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ +#define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFRISTS ====================================================== */ +#define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ +#define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFTISTS ====================================================== */ +#define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ +#define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFMOWSTS ====================================================== */ +#define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ +#define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFFSTS ======================================================= */ +#define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ +#define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ +#define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ +#define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CFDTMC ========================================================= */ +#define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ +#define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ +#define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ +#define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ +#define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ +#define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ +#define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ +#define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ +#define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ +#define R_CANFD_CFDTMTRSTS_TMTRSTS_Pos (0UL) /*!< TMTRSTS (Bit 0) */ +#define R_CANFD_CFDTMTRSTS_TMTRSTS_Msk (0xffffUL) /*!< TMTRSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ +#define R_CANFD_CFDTMTARSTS_TMTARSTS_Pos (0UL) /*!< TMTARSTS (Bit 0) */ +#define R_CANFD_CFDTMTARSTS_TMTARSTS_Msk (0xffffUL) /*!< TMTARSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ +#define R_CANFD_CFDTMTCSTS_TMTCSTS_Pos (0UL) /*!< TMTCSTS (Bit 0) */ +#define R_CANFD_CFDTMTCSTS_TMTCSTS_Msk (0xffffUL) /*!< TMTCSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTASTS ======================================================= */ +#define R_CANFD_CFDTMTASTS_TMTASTS_Pos (0UL) /*!< TMTASTS (Bit 0) */ +#define R_CANFD_CFDTMTASTS_TMTASTS_Msk (0xffffUL) /*!< TMTASTS (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDTMIEC ======================================================== */ +#define R_CANFD_CFDTMIEC_TMIE_Pos (0UL) /*!< TMIE (Bit 0) */ +#define R_CANFD_CFDTMIEC_TMIE_Msk (0xffffUL) /*!< TMIE (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ +#define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ +#define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ +#define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC0_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ +#define R_CANFD_CFDTXQCC0_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ +#define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ +#define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ +#define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ +#define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ +#define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ +#define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ +#define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ +#define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ +#define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ +#define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ +#define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ +#define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +#define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ +#define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ +#define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ +#define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ +#define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS0_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ +#define R_CANFD_CFDTXQSTS0_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ +#define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ +#define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC1 ======================================================= */ +#define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ +#define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ +#define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC1_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ +#define R_CANFD_CFDTXQCC1_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ +#define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ +#define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ +#define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ +#define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ +#define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ +#define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ +#define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS1 ======================================================= */ +#define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ +#define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ +#define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ +#define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ +#define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +#define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ +#define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ +#define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ +#define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ +#define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS1_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ +#define R_CANFD_CFDTXQSTS1_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR1 ====================================================== */ +#define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ +#define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC2 ======================================================= */ +#define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ +#define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ +#define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC2_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ +#define R_CANFD_CFDTXQCC2_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ +#define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ +#define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ +#define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ +#define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ +#define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ +#define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ +#define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS2 ======================================================= */ +#define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ +#define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ +#define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ +#define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ +#define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +#define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ +#define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ +#define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ +#define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ +#define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS2_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ +#define R_CANFD_CFDTXQSTS2_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR2 ====================================================== */ +#define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ +#define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC3 ======================================================= */ +#define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ +#define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC3_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ +#define R_CANFD_CFDTXQCC3_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ +#define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ +#define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ +#define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ +#define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ +#define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS3 ======================================================= */ +#define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ +#define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ +#define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ +#define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ +#define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +#define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ +#define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTXQSTS3_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ +#define R_CANFD_CFDTXQSTS3_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR3 ====================================================== */ +#define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ +#define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQESTS ======================================================= */ +#define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ +#define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQFISTS ====================================================== */ +#define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ +#define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ +#define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQMSTS ======================================================= */ +#define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ +#define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ +#define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQOWSTS ======================================================= */ +#define R_CANFD_CFDTXQOWSTS_TXQ0OW_Pos (0UL) /*!< TXQ0OW (Bit 0) */ +#define R_CANFD_CFDTXQOWSTS_TXQ0OW_Msk (0xfUL) /*!< TXQ0OW (Bitfield-Mask: 0x0f) */ +#define R_CANFD_CFDTXQOWSTS_TXQ1OW_Pos (4UL) /*!< TXQ1OW (Bit 4) */ +#define R_CANFD_CFDTXQOWSTS_TXQ1OW_Msk (0xf0UL) /*!< TXQ1OW (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTXQISTS ======================================================= */ +#define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ +#define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ +#define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ +#define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFTISTS ===================================================== */ +#define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ +#define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ +#define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ +#define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFRISTS ===================================================== */ +#define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ +#define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ +#define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQFSTS ======================================================= */ +#define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ +#define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ +#define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ +#define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTHLCC ======================================================== */ +#define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ +#define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ +#define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ +#define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ +#define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ +#define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ +#define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ +#define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ +#define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ +#define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ +#define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ +#define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ +#define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ +#define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ +#define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ +#define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ +#define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ +#define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ +#define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ +#define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ +#define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ +#define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ +#define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ +#define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ +#define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ +#define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ +#define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ +#define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ +#define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ +#define R_CANFD_CFDGTSTCFG_C0ICBCE_Pos (0UL) /*!< C0ICBCE (Bit 0) */ +#define R_CANFD_CFDGTSTCFG_C0ICBCE_Msk (0x1UL) /*!< C0ICBCE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTSTCFG_C1ICBCE_Pos (1UL) /*!< C1ICBCE (Bit 1) */ +#define R_CANFD_CFDGTSTCFG_C1ICBCE_Msk (0x2UL) /*!< C1ICBCE (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ +#define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ +#define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ +#define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ +#define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ +#define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ +#define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ +#define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ +#define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ +#define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDCDTCT ======================================================== */ +#define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ +#define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ +#define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ +#define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ +#define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ +#define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ +#define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ +#define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ +#define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ +#define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ +#define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ +#define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ +#define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ +#define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ +#define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTTCT ======================================================= */ +#define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ +#define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ +#define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ +#define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ +#define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ +#define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ +#define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDCDTTSTS ======================================================= */ +#define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ +#define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ +#define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ +#define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ +#define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ +#define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ +#define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGRINTSTS ====================================================== */ +#define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ +#define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDGRINTSTS_BQFIF_Pos (4UL) /*!< BQFIF (Bit 4) */ +#define R_CANFD_CFDGRINTSTS_BQFIF_Msk (0x30UL) /*!< BQFIF (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ +#define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDGRINTSTS_BQOFRIF_Pos (12UL) /*!< BQOFRIF (Bit 12) */ +#define R_CANFD_CFDGRINTSTS_BQOFRIF_Msk (0x3000UL) /*!< BQOFRIF (Bitfield-Mask: 0x03) */ +#define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ +#define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ +#define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ +#define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ +#define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDGRSTC ======================================================== */ +#define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ +#define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ +#define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ +#define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDGFCMC ======================================================= */ +#define R_CANFD_CFDGFCMC_FLXC0_Pos (0UL) /*!< FLXC0 (Bit 0) */ +#define R_CANFD_CFDGFCMC_FLXC0_Msk (0x1UL) /*!< FLXC0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFTBAC ======================================================= */ +#define R_CANFD_CFDGFTBAC_FLXMB0_Pos (0UL) /*!< FLXMB0 (Bit 0) */ +#define R_CANFD_CFDGFTBAC_FLXMB0_Msk (0xfUL) /*!< FLXMB0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDRPGACC ======================================================= */ +#define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ +#define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/cpg_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/cpg_iobitmask.h new file mode 100644 index 00000000..b7ae7f9b --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/cpg_iobitmask.h @@ -0,0 +1,2927 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : cpg_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for cpg. + *********************************************************************************************************************/ + +#ifndef CPG_IOBITMASK_H +#define CPG_IOBITMASK_H + +#define R_CPG_CPG_PLL1_STBY_RESETB_Msk (0x00000001UL) +#define R_CPG_CPG_PLL1_STBY_RESETB_Pos (0UL) +#define R_CPG_CPG_PLL1_STBY_SSCG_EN_Msk (0x00000004UL) +#define R_CPG_CPG_PLL1_STBY_SSCG_EN_Pos (2UL) +#define R_CPG_CPG_PLL1_STBY_SSCG_MODE_Msk (0x00000010UL) +#define R_CPG_CPG_PLL1_STBY_SSCG_MODE_Pos (4UL) +#define R_CPG_CPG_PLL1_STBY_RESETB_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PLL1_STBY_RESETB_WEN_Pos (16UL) +#define R_CPG_CPG_PLL1_STBY_SSCG_EN_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_PLL1_STBY_SSCG_EN_WEN_Pos (18UL) +#define R_CPG_CPG_PLL1_STBY_SSCG_MODE_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_PLL1_STBY_SSCG_MODE_WEN_Pos (20UL) +#define R_CPG_CPG_PLL1_CLK1_RANGESEL_Msk (0x00000001UL) +#define R_CPG_CPG_PLL1_CLK1_RANGESEL_Pos (0UL) +#define R_CPG_CPG_PLL1_CLK1_DIV_NF_Msk (0x00001FFEUL) +#define R_CPG_CPG_PLL1_CLK1_DIV_NF_Pos (1UL) +#define R_CPG_CPG_PLL1_CLK1_DIV_NI_Msk (0x003FE000UL) +#define R_CPG_CPG_PLL1_CLK1_DIV_NI_Pos (13UL) +#define R_CPG_CPG_PLL1_CLK1_DIV_M_Msk (0x03C00000UL) +#define R_CPG_CPG_PLL1_CLK1_DIV_M_Pos (22UL) +#define R_CPG_CPG_PLL1_CLK1_DIV_P_Msk (0x1C000000UL) +#define R_CPG_CPG_PLL1_CLK1_DIV_P_Pos (26UL) +#define R_CPG_CPG_PLL1_CLK2_SELMPERCENT_Msk (0x00000007UL) +#define R_CPG_CPG_PLL1_CLK2_SELMPERCENT_Pos (0UL) +#define R_CPG_CPG_PLL1_CLK2_SELMFREQ_Msk (0x000000F8UL) +#define R_CPG_CPG_PLL1_CLK2_SELMFREQ_Pos (3UL) +#define R_CPG_CPG_PLL1_MON_PLL1_RESETB_Msk (0x00000001UL) +#define R_CPG_CPG_PLL1_MON_PLL1_RESETB_Pos (0UL) +#define R_CPG_CPG_PLL1_MON_PLL1_LOCK_Msk (0x00000010UL) +#define R_CPG_CPG_PLL1_MON_PLL1_LOCK_Pos (4UL) +#define R_CPG_CPG_PLL2_MON_PLL2_RESETB_Msk (0x00000001UL) +#define R_CPG_CPG_PLL2_MON_PLL2_RESETB_Pos (0UL) +#define R_CPG_CPG_PLL2_MON_PLL2_LOCK_Msk (0x00000010UL) +#define R_CPG_CPG_PLL2_MON_PLL2_LOCK_Pos (4UL) +#define R_CPG_CPG_PLL3_MON_PLL3_RESETB_Msk (0x00000001UL) +#define R_CPG_CPG_PLL3_MON_PLL3_RESETB_Pos (0UL) +#define R_CPG_CPG_PLL3_MON_PLL3_LOCK_Msk (0x00000010UL) +#define R_CPG_CPG_PLL3_MON_PLL3_LOCK_Pos (4UL) +#define R_CPG_CPG_PLL4_STBY_RESETB_Msk (0x00000001UL) +#define R_CPG_CPG_PLL4_STBY_RESETB_Pos (0UL) +#define R_CPG_CPG_PLL4_STBY_SSCG_EN_Msk (0x00000004UL) +#define R_CPG_CPG_PLL4_STBY_SSCG_EN_Pos (2UL) +#define R_CPG_CPG_PLL4_STBY_SSCG_MODE_Msk (0x00000010UL) +#define R_CPG_CPG_PLL4_STBY_SSCG_MODE_Pos (4UL) +#define R_CPG_CPG_PLL4_STBY_RESETB_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PLL4_STBY_RESETB_WEN_Pos (16UL) +#define R_CPG_CPG_PLL4_STBY_SSCG_EN_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_PLL4_STBY_SSCG_EN_WEN_Pos (18UL) +#define R_CPG_CPG_PLL4_STBY_SSCG_MODE_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_PLL4_STBY_SSCG_MODE_WEN_Pos (20UL) +#define R_CPG_CPG_PLL4_CLK1_RANGESEL_Msk (0x00000001UL) +#define R_CPG_CPG_PLL4_CLK1_RANGESEL_Pos (0UL) +#define R_CPG_CPG_PLL4_CLK1_DIV_NF_Msk (0x00001FFEUL) +#define R_CPG_CPG_PLL4_CLK1_DIV_NF_Pos (1UL) +#define R_CPG_CPG_PLL4_CLK1_DIV_NI_Msk (0x003FE000UL) +#define R_CPG_CPG_PLL4_CLK1_DIV_NI_Pos (13UL) +#define R_CPG_CPG_PLL4_CLK1_DIV_M_Msk (0x03C00000UL) +#define R_CPG_CPG_PLL4_CLK1_DIV_M_Pos (22UL) +#define R_CPG_CPG_PLL4_CLK1_DIV_P_Msk (0x1C000000UL) +#define R_CPG_CPG_PLL4_CLK1_DIV_P_Pos (26UL) +#define R_CPG_CPG_PLL4_CLK2_SELMPERCENT_Msk (0x00000007UL) +#define R_CPG_CPG_PLL4_CLK2_SELMPERCENT_Pos (0UL) +#define R_CPG_CPG_PLL4_CLK2_SELMFREQ_Msk (0x000000F8UL) +#define R_CPG_CPG_PLL4_CLK2_SELMFREQ_Pos (3UL) +#define R_CPG_CPG_PLL4_MON_PLL4_RESETB_Msk (0x00000001UL) +#define R_CPG_CPG_PLL4_MON_PLL4_RESETB_Pos (0UL) +#define R_CPG_CPG_PLL4_MON_PLL4_LOCK_Msk (0x00000010UL) +#define R_CPG_CPG_PLL4_MON_PLL4_LOCK_Pos (4UL) +#define R_CPG_CPG_PLL6_STBY_RESETB_Msk (0x00000001UL) +#define R_CPG_CPG_PLL6_STBY_RESETB_Pos (0UL) +#define R_CPG_CPG_PLL6_STBY_SSCG_EN_Msk (0x00000004UL) +#define R_CPG_CPG_PLL6_STBY_SSCG_EN_Pos (2UL) +#define R_CPG_CPG_PLL6_STBY_SSCG_MODE_Msk (0x00000010UL) +#define R_CPG_CPG_PLL6_STBY_SSCG_MODE_Pos (4UL) +#define R_CPG_CPG_PLL6_STBY_RESETB_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PLL6_STBY_RESETB_WEN_Pos (16UL) +#define R_CPG_CPG_PLL6_STBY_SSCG_EN_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_PLL6_STBY_SSCG_EN_WEN_Pos (18UL) +#define R_CPG_CPG_PLL6_STBY_SSCG_MODE_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_PLL6_STBY_SSCG_MODE_WEN_Pos (20UL) +#define R_CPG_CPG_PLL6_CLK1_RANGESEL_Msk (0x00000001UL) +#define R_CPG_CPG_PLL6_CLK1_RANGESEL_Pos (0UL) +#define R_CPG_CPG_PLL6_CLK1_DIV_NF_Msk (0x00001FFEUL) +#define R_CPG_CPG_PLL6_CLK1_DIV_NF_Pos (1UL) +#define R_CPG_CPG_PLL6_CLK1_DIV_NI_Msk (0x003FE000UL) +#define R_CPG_CPG_PLL6_CLK1_DIV_NI_Pos (13UL) +#define R_CPG_CPG_PLL6_CLK1_DIV_M_Msk (0x03C00000UL) +#define R_CPG_CPG_PLL6_CLK1_DIV_M_Pos (22UL) +#define R_CPG_CPG_PLL6_CLK1_DIV_P_Msk (0x1C000000UL) +#define R_CPG_CPG_PLL6_CLK1_DIV_P_Pos (26UL) +#define R_CPG_CPG_PLL6_CLK2_SELMPERCENT_Msk (0x00000007UL) +#define R_CPG_CPG_PLL6_CLK2_SELMPERCENT_Pos (0UL) +#define R_CPG_CPG_PLL6_CLK2_SELMFREQ_Msk (0x000000F8UL) +#define R_CPG_CPG_PLL6_CLK2_SELMFREQ_Pos (3UL) +#define R_CPG_CPG_PLL6_MON_PLL6_RESETB_Msk (0x00000001UL) +#define R_CPG_CPG_PLL6_MON_PLL6_RESETB_Pos (0UL) +#define R_CPG_CPG_PLL6_MON_PLL6_LOCK_Msk (0x00000010UL) +#define R_CPG_CPG_PLL6_MON_PLL6_LOCK_Pos (4UL) +#define R_CPG_CPG_PLL1_SETTING_SEL_PLL1_Msk (0x00000001UL) +#define R_CPG_CPG_PLL1_SETTING_SEL_PLL1_Pos (0UL) +#define R_CPG_CPG_PLL1_SETTING_SEL_PLL1_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PLL1_SETTING_SEL_PLL1_WEN_Pos (16UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP0_MON_Pos (0UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP1_MON_Pos (1UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP2_MON_Pos (2UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP3_MON_Pos (3UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP4_MON_Pos (4UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP5_MON_Pos (5UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP6_MON_Pos (6UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP7_MON_Pos (7UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP8_MON_Pos (8UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP9_MON_Pos (9UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP10_MON_Msk (0x00000400UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP10_MON_Pos (10UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP11_MON_Msk (0x00000800UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP11_MON_Pos (11UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP12_MON_Msk (0x00001000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP12_MON_Pos (12UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP13_MON_Msk (0x00002000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP13_MON_Pos (13UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP14_MON_Msk (0x00004000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP14_MON_Pos (14UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP15_MON_Msk (0x00008000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP15_MON_Pos (15UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP16_MON_Msk (0x00010000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP16_MON_Pos (16UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP17_MON_Msk (0x00020000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP17_MON_Pos (17UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP18_MON_Msk (0x00040000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP18_MON_Pos (18UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP19_MON_Msk (0x00080000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP19_MON_Pos (19UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP20_MON_Msk (0x00100000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP20_MON_Pos (20UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP21_MON_Msk (0x00200000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP21_MON_Pos (21UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP22_MON_Msk (0x00400000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP22_MON_Pos (22UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP23_MON_Msk (0x00800000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP23_MON_Pos (23UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP24_MON_Msk (0x01000000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP24_MON_Pos (24UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP25_MON_Msk (0x02000000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP25_MON_Pos (25UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP26_MON_Msk (0x04000000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP26_MON_Pos (26UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP27_MON_Msk (0x08000000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP27_MON_Pos (27UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP28_MON_Msk (0x10000000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP28_MON_Pos (28UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP29_MON_Msk (0x20000000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP29_MON_Pos (29UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP30_MON_Msk (0x40000000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP30_MON_Pos (30UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP31_MON_Msk (0x80000000UL) +#define R_CPG_CPG_OTPPLL0_MON_OTP31_MON_Pos (31UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP0_MON_Pos (0UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP1_MON_Pos (1UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP2_MON_Pos (2UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP3_MON_Pos (3UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP4_MON_Pos (4UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP5_MON_Pos (5UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP6_MON_Pos (6UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP7_MON_Pos (7UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP8_MON_Pos (8UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP9_MON_Pos (9UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP10_MON_Msk (0x00000400UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP10_MON_Pos (10UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP11_MON_Msk (0x00000800UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP11_MON_Pos (11UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP12_MON_Msk (0x00001000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP12_MON_Pos (12UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP13_MON_Msk (0x00002000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP13_MON_Pos (13UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP14_MON_Msk (0x00004000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP14_MON_Pos (14UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP15_MON_Msk (0x00008000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP15_MON_Pos (15UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP16_MON_Msk (0x00010000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP16_MON_Pos (16UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP17_MON_Msk (0x00020000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP17_MON_Pos (17UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP18_MON_Msk (0x00040000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP18_MON_Pos (18UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP19_MON_Msk (0x00080000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP19_MON_Pos (19UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP20_MON_Msk (0x00100000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP20_MON_Pos (20UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP21_MON_Msk (0x00200000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP21_MON_Pos (21UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP22_MON_Msk (0x00400000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP22_MON_Pos (22UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP23_MON_Msk (0x00800000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP23_MON_Pos (23UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP24_MON_Msk (0x01000000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP24_MON_Pos (24UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP25_MON_Msk (0x02000000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP25_MON_Pos (25UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP26_MON_Msk (0x04000000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP26_MON_Pos (26UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP27_MON_Msk (0x08000000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP27_MON_Pos (27UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP28_MON_Msk (0x10000000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP28_MON_Pos (28UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP29_MON_Msk (0x20000000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP29_MON_Pos (29UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP30_MON_Msk (0x40000000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP30_MON_Pos (30UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP31_MON_Msk (0x80000000UL) +#define R_CPG_CPG_OTPPLL1_MON_OTP31_MON_Pos (31UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP0_MON_Pos (0UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP1_MON_Pos (1UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP2_MON_Pos (2UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP3_MON_Pos (3UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP4_MON_Pos (4UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP5_MON_Pos (5UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP6_MON_Pos (6UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP7_MON_Pos (7UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP8_MON_Pos (8UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP9_MON_Pos (9UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP10_MON_Msk (0x00000400UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP10_MON_Pos (10UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP11_MON_Msk (0x00000800UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP11_MON_Pos (11UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP12_MON_Msk (0x00001000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP12_MON_Pos (12UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP13_MON_Msk (0x00002000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP13_MON_Pos (13UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP14_MON_Msk (0x00004000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP14_MON_Pos (14UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP15_MON_Msk (0x00008000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP15_MON_Pos (15UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP16_MON_Msk (0x00010000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP16_MON_Pos (16UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP17_MON_Msk (0x00020000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP17_MON_Pos (17UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP18_MON_Msk (0x00040000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP18_MON_Pos (18UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP19_MON_Msk (0x00080000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP19_MON_Pos (19UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP20_MON_Msk (0x00100000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP20_MON_Pos (20UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP21_MON_Msk (0x00200000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP21_MON_Pos (21UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP22_MON_Msk (0x00400000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP22_MON_Pos (22UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP23_MON_Msk (0x00800000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP23_MON_Pos (23UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP24_MON_Msk (0x01000000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP24_MON_Pos (24UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP25_MON_Msk (0x02000000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP25_MON_Pos (25UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP26_MON_Msk (0x04000000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP26_MON_Pos (26UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP27_MON_Msk (0x08000000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP27_MON_Pos (27UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP28_MON_Msk (0x10000000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP28_MON_Pos (28UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP29_MON_Msk (0x20000000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP29_MON_Pos (29UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP30_MON_Msk (0x40000000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP30_MON_Pos (30UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP31_MON_Msk (0x80000000UL) +#define R_CPG_CPG_OTPPLL2_MON_OTP31_MON_Pos (31UL) +#define R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Msk (0x00000003UL) +#define R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Pos (0UL) +#define R_CPG_CPG_PL1_DDIV_DIV_PLL1SET_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PL1_DDIV_DIV_PLL1SET_WEN_Pos (16UL) +#define R_CPG_CPG_PL2_DDIV_DIVPL2B_SET_Msk (0x00000070UL) +#define R_CPG_CPG_PL2_DDIV_DIVPL2B_SET_Pos (4UL) +#define R_CPG_CPG_PL2_DDIV_DIV_PLL2_B_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_PL2_DDIV_DIV_PLL2_B_WEN_Pos (20UL) +#define R_CPG_CPG_PL3_DDIV_DIVPL3A_SET_Msk (0x00000007UL) +#define R_CPG_CPG_PL3_DDIV_DIVPL3A_SET_Pos (0UL) +#define R_CPG_CPG_PL3_DDIV_DIVPL3B_SET_Msk (0x00000070UL) +#define R_CPG_CPG_PL3_DDIV_DIVPL3B_SET_Pos (4UL) +#define R_CPG_CPG_PL3_DDIV_DIVPL3C_SET_Msk (0x00000700UL) +#define R_CPG_CPG_PL3_DDIV_DIVPL3C_SET_Pos (8UL) +#define R_CPG_CPG_PL3_DDIV_DIV_PLL3_A_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PL3_DDIV_DIV_PLL3_A_WEN_Pos (16UL) +#define R_CPG_CPG_PL3_DDIV_DIV_PLL3_B_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_PL3_DDIV_DIV_PLL3_B_WEN_Pos (20UL) +#define R_CPG_CPG_PL3_DDIV_DIV_PLL3_C_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_PL3_DDIV_DIV_PLL3_C_WEN_Pos (24UL) +#define R_CPG_CPG_PL6_DDIV_DIVPL6A_SET_Msk (0x00000007UL) +#define R_CPG_CPG_PL6_DDIV_DIVPL6A_SET_Pos (0UL) +#define R_CPG_CPG_PL6_DDIV_DIVPL6B_SET_Msk (0x00000070UL) +#define R_CPG_CPG_PL6_DDIV_DIVPL6B_SET_Pos (4UL) +#define R_CPG_CPG_PL6_DDIV_DIV_PLL6_A_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PL6_DDIV_DIV_PLL6_A_WEN_Pos (16UL) +#define R_CPG_CPG_PL6_DDIV_DIV_PLL6_B_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_PL6_DDIV_DIV_PLL6_B_WEN_Pos (20UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI0_SET_Msk (0x00000001UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI0_SET_Pos (0UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI1_SET_Msk (0x00000010UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI1_SET_Pos (4UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI2_SET_Msk (0x00000100UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI2_SET_Pos (8UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI0_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI0_WEN_Pos (16UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI1_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI1_WEN_Pos (20UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI2_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_SDHI_DDIV_DIVSDHI2_WEN_Pos (24UL) +#define R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk (0x00000007UL) +#define R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos (0UL) +#define R_CPG_CPG_OCTA_DDIV_DIVOCTA_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_OCTA_DDIV_DIVOCTA_WEN_Pos (16UL) +#define R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk (0x00000007UL) +#define R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos (0UL) +#define R_CPG_CPG_SPI_DDIV_DIVSPI_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_SPI_DDIV_DIVSPI_WEN_Pos (16UL) +#define R_CPG_CPG_PLL_DSEL_SELPL4_SET_Msk (0x00000040UL) +#define R_CPG_CPG_PLL_DSEL_SELPL4_SET_Pos (6UL) +#define R_CPG_CPG_PLL_DSEL_SELPL4_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_PLL_DSEL_SELPL4_WEN_Pos (22UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Msk (0x00000003UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Pos (0UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Msk (0x00000030UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Pos (4UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Msk (0x00000300UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Pos (8UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_WEN_Pos (16UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_WEN_Pos (20UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_WEN_Pos (24UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk (0x00000001UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Pos (0UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL2B_STS_Msk (0x00000020UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL2B_STS_Pos (5UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL3A_STS_Msk (0x00000100UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL3A_STS_Pos (8UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL3B_STS_Msk (0x00000200UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL3B_STS_Pos (9UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL3C_STS_Msk (0x00000400UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL3C_STS_Pos (10UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL6A_STS_Msk (0x00100000UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL6A_STS_Pos (20UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL6B_STS_Msk (0x00200000UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVPL6B_STS_Pos (21UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVSDHI0_STS_Msk (0x01000000UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVSDHI0_STS_Pos (24UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVSDHI1_STS_Msk (0x02000000UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVSDHI1_STS_Pos (25UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVSDHI2_STS_Msk (0x04000000UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVSDHI2_STS_Pos (26UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk (0x10000000UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos (28UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk (0x20000000UL) +#define R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos (29UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL1_STS_Msk (0x00000001UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL1_STS_Pos (0UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL2_STS_Msk (0x00000004UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL2_STS_Pos (2UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL3_STS_Msk (0x00000010UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL3_STS_Pos (4UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL4_STS_Msk (0x00000040UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL4_STS_Pos (6UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL6_STS_Msk (0x00000400UL) +#define R_CPG_CPG_CLKSELSTATUS_SELPL6_STS_Pos (10UL) +#define R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk (0x00010000UL) +#define R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Pos (16UL) +#define R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk (0x00020000UL) +#define R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Pos (17UL) +#define R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk (0x00040000UL) +#define R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Pos (18UL) +#define R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk (0x00000003UL) +#define R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos (0UL) +#define R_CPG_CPG_OCTA_SSEL_SELOCTA_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_OCTA_SSEL_SELOCTA_WEN_Pos (16UL) +#define R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk (0x00000003UL) +#define R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos (0UL) +#define R_CPG_CPG_SPI_SSEL_SELSPI_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_SPI_SSEL_SELSPI_WEN_Pos (16UL) +#define R_CPG_CPG_CLKON_CA55_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_CA55_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_CA55_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_CA55_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_CA55_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_CA55_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_CA55_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_CA55_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_CA55_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_CA55_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_CA55_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_CA55_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_CA55_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_CA55_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_CA55_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_CA55_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_CA55_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_CA55_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_CA55_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_CA55_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_CA55_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_CA55_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_CA55_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_CA55_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_CM33_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_CM33_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_CM33_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_CM33_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_CM33_CLK8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKON_CM33_CLK8_ON_Pos (8UL) +#define R_CPG_CPG_CLKON_CM33_CLK9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKON_CM33_CLK9_ON_Pos (9UL) +#define R_CPG_CPG_CLKON_CM33_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_CM33_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_CM33_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_CM33_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_CM33_CLK8_ONWEN_Msk (0x01000000UL) +#define R_CPG_CPG_CLKON_CM33_CLK8_ONWEN_Pos (24UL) +#define R_CPG_CPG_CLKON_CM33_CLK9_ONWEN_Msk (0x02000000UL) +#define R_CPG_CPG_CLKON_CM33_CLK9_ONWEN_Pos (25UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_SRAM_ACPU_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_SRAM_MCPU_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SRAM_MCPU_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SRAM_MCPU_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_SRAM_MCPU_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_SRAM_MCPU_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SRAM_MCPU_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_SRAM_MCPU_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_SRAM_MCPU_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_GIC600_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_GIC600_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_GIC600_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_GIC600_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_IA55_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_IA55_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_IA55_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_IA55_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_IA55_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_IA55_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_IA55_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_IA55_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_IM33_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_IM33_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_IM33_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_IM33_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_IM33_CLK8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKON_IM33_CLK8_ON_Pos (8UL) +#define R_CPG_CPG_CLKON_IM33_CLK9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKON_IM33_CLK9_ON_Pos (9UL) +#define R_CPG_CPG_CLKON_IM33_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_IM33_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_IM33_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_IM33_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_IM33_CLK8_ONWEN_Msk (0x01000000UL) +#define R_CPG_CPG_CLKON_IM33_CLK8_ONWEN_Pos (24UL) +#define R_CPG_CPG_CLKON_IM33_CLK9_ONWEN_Msk (0x02000000UL) +#define R_CPG_CPG_CLKON_IM33_CLK9_ONWEN_Pos (25UL) +#define R_CPG_CPG_CLKON_MHU_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_MHU_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_MHU_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_MHU_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_CST_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_CST_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_CST_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_CST_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_CST_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_CST_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_CST_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_CST_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_CST_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_CST_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_CST_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_CST_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_CST_CLK6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKON_CST_CLK6_ON_Pos (6UL) +#define R_CPG_CPG_CLKON_CST_CLK7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKON_CST_CLK7_ON_Pos (7UL) +#define R_CPG_CPG_CLKON_CST_CLK8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKON_CST_CLK8_ON_Pos (8UL) +#define R_CPG_CPG_CLKON_CST_CLK9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKON_CST_CLK9_ON_Pos (9UL) +#define R_CPG_CPG_CLKON_CST_CLK10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_CLKON_CST_CLK10_ON_Pos (10UL) +#define R_CPG_CPG_CLKON_CST_CLK11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_CLKON_CST_CLK11_ON_Pos (11UL) +#define R_CPG_CPG_CLKON_CST_CLK12_ON_Msk (0x00001000UL) +#define R_CPG_CPG_CLKON_CST_CLK12_ON_Pos (12UL) +#define R_CPG_CPG_CLKON_CST_CLK13_ON_Msk (0x00002000UL) +#define R_CPG_CPG_CLKON_CST_CLK13_ON_Pos (13UL) +#define R_CPG_CPG_CLKON_CST_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_CST_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_CST_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_CST_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_CST_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_CST_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_CST_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_CST_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_CST_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_CST_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_CST_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_CST_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_CST_CLK6_ONWEN_Msk (0x00400000UL) +#define R_CPG_CPG_CLKON_CST_CLK6_ONWEN_Pos (22UL) +#define R_CPG_CPG_CLKON_CST_CLK7_ONWEN_Msk (0x00800000UL) +#define R_CPG_CPG_CLKON_CST_CLK7_ONWEN_Pos (23UL) +#define R_CPG_CPG_CLKON_CST_CLK8_ONWEN_Msk (0x01000000UL) +#define R_CPG_CPG_CLKON_CST_CLK8_ONWEN_Pos (24UL) +#define R_CPG_CPG_CLKON_CST_CLK9_ONWEN_Msk (0x02000000UL) +#define R_CPG_CPG_CLKON_CST_CLK9_ONWEN_Pos (25UL) +#define R_CPG_CPG_CLKON_CST_CLK10_ONWEN_Msk (0x04000000UL) +#define R_CPG_CPG_CLKON_CST_CLK10_ONWEN_Pos (26UL) +#define R_CPG_CPG_CLKON_CST_CLK11_ONWEN_Msk (0x08000000UL) +#define R_CPG_CPG_CLKON_CST_CLK11_ONWEN_Pos (27UL) +#define R_CPG_CPG_CLKON_CST_CLK12_ONWEN_Msk (0x10000000UL) +#define R_CPG_CPG_CLKON_CST_CLK12_ONWEN_Pos (28UL) +#define R_CPG_CPG_CLKON_CST_CLK13_ONWEN_Msk (0x20000000UL) +#define R_CPG_CPG_CLKON_CST_CLK13_ONWEN_Pos (29UL) +#define R_CPG_CPG_CLKON_SYC_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SYC_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SYC_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SYC_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_DMAC_REG_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_DMAC_REG_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_DMAC_REG_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_DMAC_REG_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_DMAC_REG_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_DMAC_REG_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_DMAC_REG_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_DMAC_REG_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_GTM_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_GTM_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_GTM_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_GTM_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_GTM_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_GTM_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_GTM_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_GTM_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_GTM_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_GTM_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_GTM_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_GTM_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_GTM_CLK6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKON_GTM_CLK6_ON_Pos (6UL) +#define R_CPG_CPG_CLKON_GTM_CLK7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKON_GTM_CLK7_ON_Pos (7UL) +#define R_CPG_CPG_CLKON_GTM_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_GTM_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_GTM_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_GTM_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_GTM_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_GTM_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_GTM_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_GTM_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_GTM_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_GTM_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_GTM_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_GTM_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_GTM_CLK6_ONWEN_Msk (0x00400000UL) +#define R_CPG_CPG_CLKON_GTM_CLK6_ONWEN_Pos (22UL) +#define R_CPG_CPG_CLKON_GTM_CLK7_ONWEN_Msk (0x00800000UL) +#define R_CPG_CPG_CLKON_GTM_CLK7_ONWEN_Pos (23UL) +#define R_CPG_CPG_CLKON_MTU_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_MTU_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_MTU_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_MTU_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_POE3_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_POE3_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_POE3_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_POE3_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_GPT_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_GPT_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_GPT_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_GPT_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_POEG_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_POEG_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_POEG_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_POEG_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_POEG_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_POEG_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_POEG_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_POEG_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_POEG_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_POEG_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_POEG_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_POEG_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_POEG_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_POEG_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_POEG_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_POEG_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_WDT_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_WDT_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_WDT_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_WDT_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_WDT_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_WDT_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_WDT_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_WDT_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_WDT_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_WDT_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_WDT_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_WDT_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_WDT_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_WDT_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_WDT_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_WDT_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_WDT_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_WDT_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_WDT_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_WDT_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_WDT_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_WDT_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_WDT_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_WDT_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_DDR_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_DDR_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_DDR_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_DDR_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_DDR_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_DDR_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_DDR_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_DDR_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_DDR_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_DDR_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_DDR_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_DDR_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_DDR_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_DDR_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_DDR_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_DDR_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_SPI_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SPI_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SPI_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_SPI_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_SPI_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_SPI_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_SPI_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_SPI_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_SPI_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SPI_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_SPI_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_SPI_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_SPI_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_SPI_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_SPI_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_SPI_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_SDHI_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SDHI_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SDHI_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_SDHI_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_SDHI_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_SDHI_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_SDHI_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_SDHI_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_SDHI_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_SDHI_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_SDHI_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_SDHI_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_SDHI_CLK6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKON_SDHI_CLK6_ON_Pos (6UL) +#define R_CPG_CPG_CLKON_SDHI_CLK7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKON_SDHI_CLK7_ON_Pos (7UL) +#define R_CPG_CPG_CLKON_SDHI_CLK8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKON_SDHI_CLK8_ON_Pos (8UL) +#define R_CPG_CPG_CLKON_SDHI_CLK9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKON_SDHI_CLK9_ON_Pos (9UL) +#define R_CPG_CPG_CLKON_SDHI_CLK10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_CLKON_SDHI_CLK10_ON_Pos (10UL) +#define R_CPG_CPG_CLKON_SDHI_CLK11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_CLKON_SDHI_CLK11_ON_Pos (11UL) +#define R_CPG_CPG_CLKON_SDHI_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_SDHI_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_SDHI_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_SDHI_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_SDHI_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_SDHI_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_SDHI_CLK6_ONWEN_Msk (0x00400000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK6_ONWEN_Pos (22UL) +#define R_CPG_CPG_CLKON_SDHI_CLK7_ONWEN_Msk (0x00800000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK7_ONWEN_Pos (23UL) +#define R_CPG_CPG_CLKON_SDHI_CLK8_ONWEN_Msk (0x01000000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK8_ONWEN_Pos (24UL) +#define R_CPG_CPG_CLKON_SDHI_CLK9_ONWEN_Msk (0x02000000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK9_ONWEN_Pos (25UL) +#define R_CPG_CPG_CLKON_SDHI_CLK10_ONWEN_Msk (0x04000000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK10_ONWEN_Pos (26UL) +#define R_CPG_CPG_CLKON_SDHI_CLK11_ONWEN_Msk (0x08000000UL) +#define R_CPG_CPG_CLKON_SDHI_CLK11_ONWEN_Pos (27UL) +#define R_CPG_CPG_CLKON_SSI_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SSI_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SSI_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_SSI_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_SSI_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_SSI_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_SSI_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_SSI_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_SSI_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_SSI_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_SSI_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_SSI_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_SSI_CLK6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKON_SSI_CLK6_ON_Pos (6UL) +#define R_CPG_CPG_CLKON_SSI_CLK7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKON_SSI_CLK7_ON_Pos (7UL) +#define R_CPG_CPG_CLKON_SSI_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SSI_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_SSI_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_SSI_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_SSI_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_SSI_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_SSI_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_SSI_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_SSI_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_SSI_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_SSI_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_SSI_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_SSI_CLK6_ONWEN_Msk (0x00400000UL) +#define R_CPG_CPG_CLKON_SSI_CLK6_ONWEN_Pos (22UL) +#define R_CPG_CPG_CLKON_SSI_CLK7_ONWEN_Msk (0x00800000UL) +#define R_CPG_CPG_CLKON_SSI_CLK7_ONWEN_Pos (23UL) +#define R_CPG_CPG_CLKON_SRC_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SRC_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SRC_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SRC_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_USB_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_USB_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_USB_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_USB_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_USB_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_USB_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_USB_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_USB_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_USB_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_USB_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_USB_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_USB_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_USB_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_USB_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_USB_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_USB_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_ETH_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_ETH_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_ETH_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_ETH_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_ETH_CLK8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKON_ETH_CLK8_ON_Pos (8UL) +#define R_CPG_CPG_CLKON_ETH_CLK9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKON_ETH_CLK9_ON_Pos (9UL) +#define R_CPG_CPG_CLKON_ETH_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_ETH_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_ETH_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_ETH_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_ETH_CLK8_ONWEN_Msk (0x01000000UL) +#define R_CPG_CPG_CLKON_ETH_CLK8_ONWEN_Pos (24UL) +#define R_CPG_CPG_CLKON_ETH_CLK9_ONWEN_Msk (0x02000000UL) +#define R_CPG_CPG_CLKON_ETH_CLK9_ONWEN_Pos (25UL) +#define R_CPG_CPG_CLKON_I2C_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_I2C_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_I2C_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_I2C_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_I2C_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_I2C_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_I2C_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_I2C_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_I2C_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_I2C_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_I2C_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_I2C_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_I2C_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_I2C_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_I2C_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_I2C_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_SCIF_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SCIF_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SCIF_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_SCIF_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_SCIF_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_SCIF_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_SCIF_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_SCIF_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_SCIF_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_SCIF_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_SCIF_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_SCIF_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_SCIF_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SCIF_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_SCIF_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_SCIF_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_SCIF_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_SCIF_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_SCIF_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_SCIF_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_SCIF_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_SCIF_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_SCIF_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_SCIF_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_SCI_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SCI_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SCI_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_SCI_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_SCI_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SCI_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_SCI_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_SCI_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_IRDA_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_IRDA_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_IRDA_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_IRDA_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_RSPI_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_RSPI_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_RSPI_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_RSPI_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_RSPI_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_RSPI_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_RSPI_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_RSPI_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_RSPI_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_RSPI_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_RSPI_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_RSPI_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_RSPI_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_RSPI_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_RSPI_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_RSPI_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_RSPI_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_RSPI_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_RSPI_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_RSPI_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_CANFD_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_CANFD_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_CANFD_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_CANFD_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_CANFD_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_CANFD_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_CANFD_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_CANFD_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_GPIO_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_GPIO_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_GPIO_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_GPIO_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_ADC_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_ADC_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_ADC_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_ADC_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_ADC_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_ADC_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_ADC_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_ADC_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_TSU_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_TSU_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_TSU_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_TSU_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK6_ON_Pos (6UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK6_ONWEN_Msk (0x00400000UL) +#define R_CPG_CPG_CLKON_AXI_ACPU_BUS_CLK6_ONWEN_Pos (22UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK6_ON_Pos (6UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK7_ON_Pos (7UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK8_ON_Pos (8UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK10_ON_Pos (10UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK11_ON_Pos (11UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK12_ON_Msk (0x00001000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK12_ON_Pos (12UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK14_ON_Msk (0x00004000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK14_ON_Pos (14UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK15_ON_Msk (0x00008000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK15_ON_Pos (15UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK6_ONWEN_Msk (0x00400000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK6_ONWEN_Pos (22UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK7_ONWEN_Msk (0x00800000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK7_ONWEN_Pos (23UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK8_ONWEN_Msk (0x01000000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK8_ONWEN_Pos (24UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK10_ONWEN_Msk (0x04000000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK10_ONWEN_Pos (26UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK11_ONWEN_Msk (0x08000000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK11_ONWEN_Pos (27UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK12_ONWEN_Msk (0x10000000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK12_ONWEN_Pos (28UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK14_ONWEN_Msk (0x40000000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK14_ONWEN_Pos (30UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK15_ONWEN_Msk (0x80000000UL) +#define R_CPG_CPG_CLKON_AXI_MCPU_BUS_CLK15_ONWEN_Pos (31UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK8_ON_Pos (8UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK9_ON_Pos (9UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK8_ONWEN_Msk (0x01000000UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK8_ONWEN_Pos (24UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK9_ONWEN_Msk (0x02000000UL) +#define R_CPG_CPG_CLKON_AXI_COM_BUS_CLK9_ONWEN_Pos (25UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK8_ON_Pos (8UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK9_ON_Pos (9UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK8_ONWEN_Msk (0x01000000UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK8_ONWEN_Pos (24UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK9_ONWEN_Msk (0x02000000UL) +#define R_CPG_CPG_CLKON_PERI_COM_CLK9_ONWEN_Pos (25UL) +#define R_CPG_CPG_CLKON_REG1_BUS_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_REG1_BUS_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_REG1_BUS_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_REG1_BUS_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_REG1_BUS_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_REG1_BUS_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_REG1_BUS_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_REG1_BUS_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_REG0_BUS_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK2_ON_Pos (2UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK3_ON_Pos (3UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK4_ON_Pos (4UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK5_ON_Pos (5UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK6_ON_Pos (6UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK7_ON_Pos (7UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK2_ONWEN_Msk (0x00040000UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK2_ONWEN_Pos (18UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK3_ONWEN_Msk (0x00080000UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK3_ONWEN_Pos (19UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK4_ONWEN_Msk (0x00100000UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK4_ONWEN_Pos (20UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK5_ONWEN_Msk (0x00200000UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK5_ONWEN_Pos (21UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK6_ONWEN_Msk (0x00400000UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK6_ONWEN_Pos (22UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK7_ONWEN_Msk (0x00800000UL) +#define R_CPG_CPG_CLKON_PERI_CPU_CLK7_ONWEN_Pos (23UL) +#define R_CPG_CPG_CLKON_PERI_DDR_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_PERI_DDR_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_PERI_DDR_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_PERI_DDR_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_AXI_TZCDDR_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_AXI_TZCDDR_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_AXI_TZCDDR_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_AXI_TZCDDR_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_OCTA_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_OCTA_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_OCTA_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_OCTA_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_OCTA_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_OCTA_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_OCTA_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_OCTA_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_OTFDE_DDR_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_OTFDE_DDR_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_OTFDE_DDR_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_OTFDE_DDR_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_OTFDE_DDR_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_OTFDE_DDR_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_OTFDE_DDR_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_OTFDE_DDR_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_OTFDE_SPI_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_OTFDE_SPI_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_OTFDE_SPI_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_OTFDE_SPI_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_OTFDE_SPI_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_OTFDE_SPI_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_OTFDE_SPI_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_OTFDE_SPI_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_PDM_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_PDM_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_PDM_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_PDM_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_PDM_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_PDM_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_PDM_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_PDM_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_PCI_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_PCI_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_PCI_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_PCI_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_PCI_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_PCI_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_PCI_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_PCI_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_SPDIF_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_SPDIF_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_SPDIF_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_SPDIF_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_I3C_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_I3C_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_I3C_CLK1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKON_I3C_CLK1_ON_Pos (1UL) +#define R_CPG_CPG_CLKON_I3C_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_I3C_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKON_I3C_CLK1_ONWEN_Msk (0x00020000UL) +#define R_CPG_CPG_CLKON_I3C_CLK1_ONWEN_Pos (17UL) +#define R_CPG_CPG_CLKON_VBAT_CLK0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKON_VBAT_CLK0_ON_Pos (0UL) +#define R_CPG_CPG_CLKON_VBAT_CLK0_ONWEN_Msk (0x00010000UL) +#define R_CPG_CPG_CLKON_VBAT_CLK0_ONWEN_Pos (16UL) +#define R_CPG_CPG_CLKMON_CA55_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_CA55_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_CA55_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_CA55_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_CA55_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_CA55_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_CA55_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_CA55_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_CA55_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_CA55_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_CA55_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_CA55_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_CM33_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_CM33_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_CM33_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_CM33_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_CM33_CLK8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKMON_CM33_CLK8_MON_Pos (8UL) +#define R_CPG_CPG_CLKMON_CM33_CLK9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKMON_CM33_CLK9_MON_Pos (9UL) +#define R_CPG_CPG_CLKMON_SRAM_ACPU_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SRAM_ACPU_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_SRAM_ACPU_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_SRAM_ACPU_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_SRAM_ACPU_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_SRAM_ACPU_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_SRAM_MCPU_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SRAM_MCPU_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_SRAM_MCPU_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_SRAM_MCPU_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_GIC600_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_GIC600_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_IA55_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_IA55_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_IA55_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_IA55_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_IM33_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_IM33_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_IM33_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_IM33_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_IM33_CLK8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKMON_IM33_CLK8_MON_Pos (8UL) +#define R_CPG_CPG_CLKMON_IM33_CLK9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKMON_IM33_CLK9_MON_Pos (9UL) +#define R_CPG_CPG_CLKMON_MHU_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_MHU_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_CST_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_CST_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_CST_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_CST_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_CST_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_CST_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_CST_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_CST_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_CST_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_CST_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_CST_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_CST_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_CST_CLK6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKMON_CST_CLK6_MON_Pos (6UL) +#define R_CPG_CPG_CLKMON_CST_CLK7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKMON_CST_CLK7_MON_Pos (7UL) +#define R_CPG_CPG_CLKMON_CST_CLK8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKMON_CST_CLK8_MON_Pos (8UL) +#define R_CPG_CPG_CLKMON_CST_CLK9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKMON_CST_CLK9_MON_Pos (9UL) +#define R_CPG_CPG_CLKMON_CST_CLK10_MON_Msk (0x00000400UL) +#define R_CPG_CPG_CLKMON_CST_CLK10_MON_Pos (10UL) +#define R_CPG_CPG_CLKMON_CST_CLK11_MON_Msk (0x00000800UL) +#define R_CPG_CPG_CLKMON_CST_CLK11_MON_Pos (11UL) +#define R_CPG_CPG_CLKMON_CST_CLK12_MON_Msk (0x00001000UL) +#define R_CPG_CPG_CLKMON_CST_CLK12_MON_Pos (12UL) +#define R_CPG_CPG_CLKMON_CST_CLK13_MON_Msk (0x00002000UL) +#define R_CPG_CPG_CLKMON_CST_CLK13_MON_Pos (13UL) +#define R_CPG_CPG_CLKMON_SYC_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SYC_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_DMAC_REG_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_DMAC_REG_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_DMAC_REG_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_DMAC_REG_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_GTM_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_GTM_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_GTM_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_GTM_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_GTM_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_GTM_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_GTM_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_GTM_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_GTM_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_GTM_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_GTM_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_GTM_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_GTM_CLK6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKMON_GTM_CLK6_MON_Pos (6UL) +#define R_CPG_CPG_CLKMON_GTM_CLK7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKMON_GTM_CLK7_MON_Pos (7UL) +#define R_CPG_CPG_CLKMON_MTU_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_MTU_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_POE3_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_POE3_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_GPT_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_GPT_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_POEG_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_POEG_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_POEG_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_POEG_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_POEG_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_POEG_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_POEG_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_POEG_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_WDT_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_WDT_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_WDT_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_WDT_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_WDT_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_WDT_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_WDT_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_WDT_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_WDT_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_WDT_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_WDT_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_WDT_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_DDR_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_DDR_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_DDR_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_DDR_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_DDR_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_DDR_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_DDR_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_DDR_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_SPI_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SPI_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_SPI_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_SPI_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_SPI_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_SPI_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_SPI_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_SPI_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK6_MON_Pos (6UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK7_MON_Pos (7UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK8_MON_Pos (8UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK9_MON_Pos (9UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK10_MON_Msk (0x00000400UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK10_MON_Pos (10UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK11_MON_Msk (0x00000800UL) +#define R_CPG_CPG_CLKMON_SDHI_CLK11_MON_Pos (11UL) +#define R_CPG_CPG_CLKMON_SSI_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SSI_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_SSI_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_SSI_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_SSI_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_SSI_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_SSI_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_SSI_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_SSI_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_SSI_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_SSI_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_SSI_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_SSI_CLK6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKMON_SSI_CLK6_MON_Pos (6UL) +#define R_CPG_CPG_CLKMON_SSI_CLK7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKMON_SSI_CLK7_MON_Pos (7UL) +#define R_CPG_CPG_CLKMON_SRC_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SRC_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_USB_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_USB_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_USB_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_USB_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_USB_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_USB_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_USB_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_USB_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_ETH_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_ETH_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_ETH_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_ETH_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_ETH_CLK8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKMON_ETH_CLK8_MON_Pos (8UL) +#define R_CPG_CPG_CLKMON_ETH_CLK9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKMON_ETH_CLK9_MON_Pos (9UL) +#define R_CPG_CPG_CLKMON_I2C_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_I2C_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_I2C_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_I2C_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_I2C_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_I2C_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_I2C_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_I2C_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_SCIF_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_SCI_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SCI_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_SCI_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_SCI_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_IRDA_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_IRDA_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_RSPI_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_CANFD_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_CANFD_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_CANFD_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_CANFD_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_GPIO_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_GPIO_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_ADC_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_ADC_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_ADC_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_ADC_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_TSU_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_TSU_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKMON_AXI_ACPU_BUS_CLK6_MON_Pos (6UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK6_MON_Pos (6UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK7_MON_Pos (7UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK8_MON_Pos (8UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK10_MON_Msk (0x00000400UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK10_MON_Pos (10UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK11_MON_Msk (0x00000800UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK11_MON_Pos (11UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK12_MON_Msk (0x00001000UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK12_MON_Pos (12UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK14_MON_Msk (0x00004000UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK14_MON_Pos (14UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK15_MON_Msk (0x00008000UL) +#define R_CPG_CPG_CLKMON_AXI_MCPU_BUS_CLK15_MON_Pos (15UL) +#define R_CPG_CPG_CLKMON_AXI_COM_BUS_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_AXI_COM_BUS_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_AXI_COM_BUS_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_AXI_COM_BUS_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_AXI_COM_BUS_CLK8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKMON_AXI_COM_BUS_CLK8_MON_Pos (8UL) +#define R_CPG_CPG_CLKMON_AXI_COM_BUS_CLK9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKMON_AXI_COM_BUS_CLK9_MON_Pos (9UL) +#define R_CPG_CPG_CLKMON_PERI_COM_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_PERI_COM_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_PERI_COM_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_PERI_COM_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_PERI_COM_CLK8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_CLKMON_PERI_COM_CLK8_MON_Pos (8UL) +#define R_CPG_CPG_CLKMON_PERI_COM_CLK9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_CLKMON_PERI_COM_CLK9_MON_Pos (9UL) +#define R_CPG_CPG_CLKMON_REG1_BUS_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_REG1_BUS_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_REG1_BUS_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_REG1_BUS_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_REG0_BUS_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_REG0_BUS_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_REG0_BUS_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_REG0_BUS_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_REG0_BUS_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_REG0_BUS_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_REG0_BUS_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_REG0_BUS_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK2_MON_Pos (2UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK3_MON_Pos (3UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK4_MON_Pos (4UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK5_MON_Pos (5UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK6_MON_Pos (6UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_CLKMON_PERI_CPU_CLK7_MON_Pos (7UL) +#define R_CPG_CPG_CLKMON_PERI_DDR_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_PERI_DDR_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_AXI_TZCDDR_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_AXI_TZCDDR_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_OTFDE_DDR_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_OTFDE_DDR_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_OTFDE_DDR_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_OTFDE_DDR_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_OTFDE_SPI_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_OTFDE_SPI_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_OTFDE_SPI_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_OTFDE_SPI_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_PDM_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_PDM_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_PDM_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_PDM_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_PCI_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_PCI_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_PCI_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_PCI_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_SPDIF_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_SPDIF_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_I3C_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_I3C_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_CLKMON_I3C_CLK1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLKMON_I3C_CLK1_MON_Pos (1UL) +#define R_CPG_CPG_CLKMON_VBAT_CLK0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLKMON_VBAT_CLK0_MON_Pos (0UL) +#define R_CPG_CPG_RST_CA55_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_CA55_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_CA55_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_CA55_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_CA55_UNIT4_RSTB_Msk (0x00000010UL) +#define R_CPG_CPG_RST_CA55_UNIT4_RSTB_Pos (4UL) +#define R_CPG_CPG_RST_CA55_UNIT5_RSTB_Msk (0x00000020UL) +#define R_CPG_CPG_RST_CA55_UNIT5_RSTB_Pos (5UL) +#define R_CPG_CPG_RST_CA55_UNIT6_RSTB_Msk (0x00000040UL) +#define R_CPG_CPG_RST_CA55_UNIT6_RSTB_Pos (6UL) +#define R_CPG_CPG_RST_CA55_UNIT7_RSTB_Msk (0x00000080UL) +#define R_CPG_CPG_RST_CA55_UNIT7_RSTB_Pos (7UL) +#define R_CPG_CPG_RST_CA55_UNIT8_RSTB_Msk (0x00000100UL) +#define R_CPG_CPG_RST_CA55_UNIT8_RSTB_Pos (8UL) +#define R_CPG_CPG_RST_CA55_UNIT9_RSTB_Msk (0x00000200UL) +#define R_CPG_CPG_RST_CA55_UNIT9_RSTB_Pos (9UL) +#define R_CPG_CPG_RST_CA55_UNIT10_RSTB_Msk (0x00000400UL) +#define R_CPG_CPG_RST_CA55_UNIT10_RSTB_Pos (10UL) +#define R_CPG_CPG_RST_CA55_UNIT11_RSTB_Msk (0x00000800UL) +#define R_CPG_CPG_RST_CA55_UNIT11_RSTB_Pos (11UL) +#define R_CPG_CPG_RST_CA55_UNIT12_RSTB_Msk (0x00001000UL) +#define R_CPG_CPG_RST_CA55_UNIT12_RSTB_Pos (12UL) +#define R_CPG_CPG_RST_CA55_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_CA55_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_CA55_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_CA55_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_CA55_UNIT4_RSTWEN_Msk (0x00100000UL) +#define R_CPG_CPG_RST_CA55_UNIT4_RSTWEN_Pos (20UL) +#define R_CPG_CPG_RST_CA55_UNIT5_RSTWEN_Msk (0x00200000UL) +#define R_CPG_CPG_RST_CA55_UNIT5_RSTWEN_Pos (21UL) +#define R_CPG_CPG_RST_CA55_UNIT6_RSTWEN_Msk (0x00400000UL) +#define R_CPG_CPG_RST_CA55_UNIT6_RSTWEN_Pos (22UL) +#define R_CPG_CPG_RST_CA55_UNIT7_RSTWEN_Msk (0x00800000UL) +#define R_CPG_CPG_RST_CA55_UNIT7_RSTWEN_Pos (23UL) +#define R_CPG_CPG_RST_CA55_UNIT8_RSTWEN_Msk (0x01000000UL) +#define R_CPG_CPG_RST_CA55_UNIT8_RSTWEN_Pos (24UL) +#define R_CPG_CPG_RST_CA55_UNIT9_RSTWEN_Msk (0x02000000UL) +#define R_CPG_CPG_RST_CA55_UNIT9_RSTWEN_Pos (25UL) +#define R_CPG_CPG_RST_CA55_UNIT10_RSTWEN_Msk (0x04000000UL) +#define R_CPG_CPG_RST_CA55_UNIT10_RSTWEN_Pos (26UL) +#define R_CPG_CPG_RST_CA55_UNIT11_RSTWEN_Msk (0x08000000UL) +#define R_CPG_CPG_RST_CA55_UNIT11_RSTWEN_Pos (27UL) +#define R_CPG_CPG_RST_CA55_UNIT12_RSTWEN_Msk (0x10000000UL) +#define R_CPG_CPG_RST_CA55_UNIT12_RSTWEN_Pos (28UL) +#define R_CPG_CPG_RST_CM33_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_CM33_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_CM33_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_CM33_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_CM33_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_CM33_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_CM33_UNIT8_RSTB_Msk (0x00000100UL) +#define R_CPG_CPG_RST_CM33_UNIT8_RSTB_Pos (8UL) +#define R_CPG_CPG_RST_CM33_UNIT9_RSTB_Msk (0x00000200UL) +#define R_CPG_CPG_RST_CM33_UNIT9_RSTB_Pos (9UL) +#define R_CPG_CPG_RST_CM33_UNIT10_RSTB_Msk (0x00000400UL) +#define R_CPG_CPG_RST_CM33_UNIT10_RSTB_Pos (10UL) +#define R_CPG_CPG_RST_CM33_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_CM33_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_CM33_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_CM33_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_CM33_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_CM33_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_CM33_UNIT8_RSTWEN_Msk (0x01000000UL) +#define R_CPG_CPG_RST_CM33_UNIT8_RSTWEN_Pos (24UL) +#define R_CPG_CPG_RST_CM33_UNIT9_RSTWEN_Msk (0x02000000UL) +#define R_CPG_CPG_RST_CM33_UNIT9_RSTWEN_Pos (25UL) +#define R_CPG_CPG_RST_CM33_UNIT10_RSTWEN_Msk (0x04000000UL) +#define R_CPG_CPG_RST_CM33_UNIT10_RSTWEN_Pos (26UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_SRAM_ACPU_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_SRAM_MCPU_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SRAM_MCPU_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SRAM_MCPU_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_SRAM_MCPU_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_SRAM_MCPU_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SRAM_MCPU_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_SRAM_MCPU_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_SRAM_MCPU_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_GIC600_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_GIC600_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_GIC600_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_GIC600_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_GIC600_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_GIC600_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_GIC600_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_GIC600_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_IA55_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_IA55_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_IA55_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_IA55_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_IM33_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_IM33_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_IM33_UNIT8_RSTB_Msk (0x00000100UL) +#define R_CPG_CPG_RST_IM33_UNIT8_RSTB_Pos (8UL) +#define R_CPG_CPG_RST_IM33_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_IM33_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_IM33_UNIT8_RSTWEN_Msk (0x01000000UL) +#define R_CPG_CPG_RST_IM33_UNIT8_RSTWEN_Pos (24UL) +#define R_CPG_CPG_RST_MHU_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_MHU_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_MHU_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_MHU_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_SYC_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SYC_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SYC_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SYC_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_DMAC_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_DMAC_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_DMAC_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_DMAC_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_DMAC_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_DMAC_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_DMAC_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_DMAC_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_GTM_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_GTM_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_GTM_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_GTM_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_GTM_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_GTM_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_GTM_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_GTM_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_GTM_UNIT4_RSTB_Msk (0x00000010UL) +#define R_CPG_CPG_RST_GTM_UNIT4_RSTB_Pos (4UL) +#define R_CPG_CPG_RST_GTM_UNIT5_RSTB_Msk (0x00000020UL) +#define R_CPG_CPG_RST_GTM_UNIT5_RSTB_Pos (5UL) +#define R_CPG_CPG_RST_GTM_UNIT6_RSTB_Msk (0x00000040UL) +#define R_CPG_CPG_RST_GTM_UNIT6_RSTB_Pos (6UL) +#define R_CPG_CPG_RST_GTM_UNIT7_RSTB_Msk (0x00000080UL) +#define R_CPG_CPG_RST_GTM_UNIT7_RSTB_Pos (7UL) +#define R_CPG_CPG_RST_GTM_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_GTM_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_GTM_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_GTM_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_GTM_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_GTM_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_GTM_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_GTM_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_GTM_UNIT4_RSTWEN_Msk (0x00100000UL) +#define R_CPG_CPG_RST_GTM_UNIT4_RSTWEN_Pos (20UL) +#define R_CPG_CPG_RST_GTM_UNIT5_RSTWEN_Msk (0x00200000UL) +#define R_CPG_CPG_RST_GTM_UNIT5_RSTWEN_Pos (21UL) +#define R_CPG_CPG_RST_GTM_UNIT6_RSTWEN_Msk (0x00400000UL) +#define R_CPG_CPG_RST_GTM_UNIT6_RSTWEN_Pos (22UL) +#define R_CPG_CPG_RST_GTM_UNIT7_RSTWEN_Msk (0x00800000UL) +#define R_CPG_CPG_RST_GTM_UNIT7_RSTWEN_Pos (23UL) +#define R_CPG_CPG_RST_MTU_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_MTU_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_MTU_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_MTU_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_POE3_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_POE3_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_POE3_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_POE3_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_GPT_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_GPT_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_GPT_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_GPT_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_POEG_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_POEG_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_POEG_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_POEG_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_POEG_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_POEG_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_POEG_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_POEG_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_POEG_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_POEG_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_POEG_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_POEG_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_POEG_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_POEG_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_POEG_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_POEG_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_WDT_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_WDT_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_WDT_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_WDT_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_WDT_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_WDT_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_WDT_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_WDT_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_WDT_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_WDT_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_WDT_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_WDT_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_DDR_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_DDR_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_DDR_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_DDR_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_DDR_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_DDR_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_DDR_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_DDR_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_DDR_UNIT6_RSTB_Msk (0x00000040UL) +#define R_CPG_CPG_RST_DDR_UNIT6_RSTB_Pos (6UL) +#define R_CPG_CPG_RST_DDR_UNIT7_RSTB_Msk (0x00000080UL) +#define R_CPG_CPG_RST_DDR_UNIT7_RSTB_Pos (7UL) +#define R_CPG_CPG_RST_DDR_UNIT8_RSTB_Msk (0x00000100UL) +#define R_CPG_CPG_RST_DDR_UNIT8_RSTB_Pos (8UL) +#define R_CPG_CPG_RST_DDR_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_DDR_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_DDR_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_DDR_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_DDR_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_DDR_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_DDR_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_DDR_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_DDR_UNIT6_RSTWEN_Msk (0x00400000UL) +#define R_CPG_CPG_RST_DDR_UNIT6_RSTWEN_Pos (22UL) +#define R_CPG_CPG_RST_DDR_UNIT7_RSTWEN_Msk (0x00800000UL) +#define R_CPG_CPG_RST_DDR_UNIT7_RSTWEN_Pos (23UL) +#define R_CPG_CPG_RST_DDR_UNIT8_RSTWEN_Msk (0x01000000UL) +#define R_CPG_CPG_RST_DDR_UNIT8_RSTWEN_Pos (24UL) +#define R_CPG_CPG_RST_SPI_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SPI_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SPI_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_SPI_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_SPI_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SPI_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_SPI_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_SPI_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_SDHI_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SDHI_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SDHI_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_SDHI_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_SDHI_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_SDHI_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_SDHI_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SDHI_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_SDHI_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_SDHI_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_SDHI_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_SDHI_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_SSIF_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SSIF_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SSIF_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_SSIF_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_SSIF_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_SSIF_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_SSIF_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_SSIF_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_SSIF_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SSIF_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_SSIF_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_SSIF_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_SSIF_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_SSIF_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_SSIF_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_SSIF_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_SRC_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SRC_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SRC_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SRC_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_USB_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_USB_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_USB_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_USB_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_USB_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_USB_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_USB_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_USB_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_USB_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_USB_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_USB_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_USB_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_USB_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_USB_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_USB_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_USB_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_ETH_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_ETH_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_ETH_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_ETH_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_ETH_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_ETH_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_ETH_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_ETH_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_I2C_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_I2C_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_I2C_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_I2C_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_I2C_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_I2C_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_I2C_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_I2C_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_I2C_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_I2C_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_I2C_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_I2C_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_I2C_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_I2C_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_I2C_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_I2C_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_SCIF_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SCIF_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SCIF_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_SCIF_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_SCIF_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_SCIF_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_SCIF_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_SCIF_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_SCIF_UNIT4_RSTB_Msk (0x00000010UL) +#define R_CPG_CPG_RST_SCIF_UNIT4_RSTB_Pos (4UL) +#define R_CPG_CPG_RST_SCIF_UNIT5_RSTB_Msk (0x00000020UL) +#define R_CPG_CPG_RST_SCIF_UNIT5_RSTB_Pos (5UL) +#define R_CPG_CPG_RST_SCIF_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SCIF_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_SCIF_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_SCIF_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_SCIF_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_SCIF_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_SCIF_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_SCIF_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_SCIF_UNIT4_RSTWEN_Msk (0x00100000UL) +#define R_CPG_CPG_RST_SCIF_UNIT4_RSTWEN_Pos (20UL) +#define R_CPG_CPG_RST_SCIF_UNIT5_RSTWEN_Msk (0x00200000UL) +#define R_CPG_CPG_RST_SCIF_UNIT5_RSTWEN_Pos (21UL) +#define R_CPG_CPG_RST_SCI_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SCI_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SCI_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_SCI_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_SCI_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SCI_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_SCI_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_SCI_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_IRDA_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_IRDA_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_IRDA_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_IRDA_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_RSPI_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_RSPI_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_RSPI_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_RSPI_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_RSPI_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_RSPI_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_RSPI_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_RSPI_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_RSPI_UNIT4_RSTB_Msk (0x00000010UL) +#define R_CPG_CPG_RST_RSPI_UNIT4_RSTB_Pos (4UL) +#define R_CPG_CPG_RST_RSPI_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_RSPI_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_RSPI_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_RSPI_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_RSPI_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_RSPI_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_RSPI_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_RSPI_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_RSPI_UNIT4_RSTWEN_Msk (0x00100000UL) +#define R_CPG_CPG_RST_RSPI_UNIT4_RSTWEN_Pos (20UL) +#define R_CPG_CPG_RST_CANFD_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_CANFD_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_CANFD_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_CANFD_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_CANFD_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_CANFD_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_CANFD_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_CANFD_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_GPIO_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_GPIO_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_GPIO_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_GPIO_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_GPIO_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_GPIO_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_GPIO_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_GPIO_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_GPIO_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_GPIO_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_GPIO_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_GPIO_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_ADC_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_ADC_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_ADC_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_ADC_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_ADC_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_ADC_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_ADC_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_ADC_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_TSU_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_TSU_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_TSU_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_TSU_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_AXI_ACPU_BUS_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_AXI_ACPU_BUS_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_AXI_ACPU_BUS_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_AXI_ACPU_BUS_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_AXI_MCPU_BUS_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_AXI_MCPU_BUS_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_AXI_MCPU_BUS_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_AXI_MCPU_BUS_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_AXI_COM_BUS_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_AXI_COM_BUS_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_AXI_COM_BUS_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_AXI_COM_BUS_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_AXI_COM_BUS_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_AXI_COM_BUS_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_AXI_COM_BUS_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_AXI_COM_BUS_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_PERI_COM_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_PERI_COM_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_PERI_COM_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_PERI_COM_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_PERI_COM_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_PERI_COM_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_PERI_COM_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_PERI_COM_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_REG1_BUS_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_REG1_BUS_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_REG1_BUS_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_REG1_BUS_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_REG0_BUS_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_REG0_BUS_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_REG0_BUS_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_REG0_BUS_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_PERI_CPU_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_PERI_CPU_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_PERI_CPU_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_PERI_CPU_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_PERI_CPU_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_PERI_CPU_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_PERI_CPU_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_PERI_CPU_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_PERI_DDR_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_PERI_DDR_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_PERI_DDR_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_PERI_DDR_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_AXI_TZCDDR_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_OCTA_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_OCTA_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_OCTA_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_OCTA_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_OTFDE_DDR_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_OTFDE_DDR_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_OTFDE_DDR_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_OTFDE_DDR_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_OTFDE_DDR_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_OTFDE_DDR_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_OTFDE_DDR_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_OTFDE_DDR_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_OTFDE_SPI_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_OTFDE_SPI_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_OTFDE_SPI_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_OTFDE_SPI_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_OTFDE_SPI_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_OTFDE_SPI_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_OTFDE_SPI_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_OTFDE_SPI_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_PDM_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_PDM_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_PDM_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_PDM_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_PCI_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_PCI_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_PCI_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_PCI_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_PCI_UNIT2_RSTB_Msk (0x00000004UL) +#define R_CPG_CPG_RST_PCI_UNIT2_RSTB_Pos (2UL) +#define R_CPG_CPG_RST_PCI_UNIT3_RSTB_Msk (0x00000008UL) +#define R_CPG_CPG_RST_PCI_UNIT3_RSTB_Pos (3UL) +#define R_CPG_CPG_RST_PCI_UNIT4_RSTB_Msk (0x00000010UL) +#define R_CPG_CPG_RST_PCI_UNIT4_RSTB_Pos (4UL) +#define R_CPG_CPG_RST_PCI_UNIT5_RSTB_Msk (0x00000020UL) +#define R_CPG_CPG_RST_PCI_UNIT5_RSTB_Pos (5UL) +#define R_CPG_CPG_RST_PCI_UNIT6_RSTB_Msk (0x00000040UL) +#define R_CPG_CPG_RST_PCI_UNIT6_RSTB_Pos (6UL) +#define R_CPG_CPG_RST_PCI_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_PCI_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_PCI_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_PCI_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_PCI_UNIT2_RSTWEN_Msk (0x00040000UL) +#define R_CPG_CPG_RST_PCI_UNIT2_RSTWEN_Pos (18UL) +#define R_CPG_CPG_RST_PCI_UNIT3_RSTWEN_Msk (0x00080000UL) +#define R_CPG_CPG_RST_PCI_UNIT3_RSTWEN_Pos (19UL) +#define R_CPG_CPG_RST_PCI_UNIT4_RSTWEN_Msk (0x00100000UL) +#define R_CPG_CPG_RST_PCI_UNIT4_RSTWEN_Pos (20UL) +#define R_CPG_CPG_RST_PCI_UNIT5_RSTWEN_Msk (0x00200000UL) +#define R_CPG_CPG_RST_PCI_UNIT5_RSTWEN_Pos (21UL) +#define R_CPG_CPG_RST_PCI_UNIT6_RSTWEN_Msk (0x00400000UL) +#define R_CPG_CPG_RST_PCI_UNIT6_RSTWEN_Pos (22UL) +#define R_CPG_CPG_RST_SPDIF_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_SPDIF_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_SPDIF_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_SPDIF_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_I3C_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_I3C_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_I3C_UNIT1_RSTB_Msk (0x00000002UL) +#define R_CPG_CPG_RST_I3C_UNIT1_RSTB_Pos (1UL) +#define R_CPG_CPG_RST_I3C_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_I3C_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RST_I3C_UNIT1_RSTWEN_Msk (0x00020000UL) +#define R_CPG_CPG_RST_I3C_UNIT1_RSTWEN_Pos (17UL) +#define R_CPG_CPG_RST_VBAT_UNIT0_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RST_VBAT_UNIT0_RSTB_Pos (0UL) +#define R_CPG_CPG_RST_VBAT_UNIT0_RSTWEN_Msk (0x00010000UL) +#define R_CPG_CPG_RST_VBAT_UNIT0_RSTWEN_Pos (16UL) +#define R_CPG_CPG_RSTMON_CA55_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_CA55_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_CA55_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_CA55_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_CA55_RST4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_RSTMON_CA55_RST4_MON_Pos (4UL) +#define R_CPG_CPG_RSTMON_CA55_RST5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_RSTMON_CA55_RST5_MON_Pos (5UL) +#define R_CPG_CPG_RSTMON_CA55_RST6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_RSTMON_CA55_RST6_MON_Pos (6UL) +#define R_CPG_CPG_RSTMON_CA55_RST7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_RSTMON_CA55_RST7_MON_Pos (7UL) +#define R_CPG_CPG_RSTMON_CA55_RST8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_RSTMON_CA55_RST8_MON_Pos (8UL) +#define R_CPG_CPG_RSTMON_CA55_RST9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_RSTMON_CA55_RST9_MON_Pos (9UL) +#define R_CPG_CPG_RSTMON_CA55_RST10_MON_Msk (0x00000400UL) +#define R_CPG_CPG_RSTMON_CA55_RST10_MON_Pos (10UL) +#define R_CPG_CPG_RSTMON_CA55_RST11_MON_Msk (0x00000800UL) +#define R_CPG_CPG_RSTMON_CA55_RST11_MON_Pos (11UL) +#define R_CPG_CPG_RSTMON_CA55_RST12_MON_Msk (0x00001000UL) +#define R_CPG_CPG_RSTMON_CA55_RST12_MON_Pos (12UL) +#define R_CPG_CPG_RSTMON_CM33_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_CM33_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_CM33_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_CM33_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_CM33_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_CM33_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_CM33_RST8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_RSTMON_CM33_RST8_MON_Pos (8UL) +#define R_CPG_CPG_RSTMON_CM33_RST9_MON_Msk (0x00000200UL) +#define R_CPG_CPG_RSTMON_CM33_RST9_MON_Pos (9UL) +#define R_CPG_CPG_RSTMON_CM33_RST10_MON_Msk (0x00000400UL) +#define R_CPG_CPG_RSTMON_CM33_RST10_MON_Pos (10UL) +#define R_CPG_CPG_RSTMON_SRAM_ACPU_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SRAM_ACPU_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_SRAM_MCPU_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SRAM_MCPU_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_SRAM_MCPU_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_SRAM_MCPU_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_GIC600_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_GIC600_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_GIC600_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_GIC600_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_IA55_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_IA55_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_IM33_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_IM33_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_MHU_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_MHU_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_SYC_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SYC_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_DMAC_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_DMAC_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_DMAC_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_DMAC_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_GTM_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_GTM_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_GTM_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_GTM_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_GTM_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_GTM_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_GTM_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_GTM_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_GTM_RST4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_RSTMON_GTM_RST4_MON_Pos (4UL) +#define R_CPG_CPG_RSTMON_GTM_RST5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_RSTMON_GTM_RST5_MON_Pos (5UL) +#define R_CPG_CPG_RSTMON_GTM_RST6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_RSTMON_GTM_RST6_MON_Pos (6UL) +#define R_CPG_CPG_RSTMON_GTM_RST7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_RSTMON_GTM_RST7_MON_Pos (7UL) +#define R_CPG_CPG_RSTMON_MTU_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_MTU_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_POE3_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_POE3_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_GPT_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_GPT_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_POEG_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_POEG_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_POEG_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_POEG_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_POEG_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_POEG_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_POEG_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_POEG_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_WDT_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_WDT_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_WDT_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_WDT_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_WDT_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_WDT_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_DDR_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_DDR_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_DDR_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_DDR_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_DDR_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_DDR_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_DDR_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_DDR_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_DDR_RST6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_RSTMON_DDR_RST6_MON_Pos (6UL) +#define R_CPG_CPG_RSTMON_DDR_RST7_MON_Msk (0x00000080UL) +#define R_CPG_CPG_RSTMON_DDR_RST7_MON_Pos (7UL) +#define R_CPG_CPG_RSTMON_DDR_RST8_MON_Msk (0x00000100UL) +#define R_CPG_CPG_RSTMON_DDR_RST8_MON_Pos (8UL) +#define R_CPG_CPG_RSTMON_SPI_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SPI_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_SPI_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_SPI_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_SDHI_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SDHI_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_SDHI_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_SDHI_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_SDHI_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_SDHI_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_SSIF_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SSIF_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_SSIF_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_SSIF_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_SSIF_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_SSIF_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_SSIF_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_SSIF_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_SRC_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SRC_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_USB_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_USB_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_USB_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_USB_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_USB_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_USB_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_USB_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_USB_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_ETH_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_ETH_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_ETH_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_ETH_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_I2C_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_I2C_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_I2C_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_I2C_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_I2C_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_I2C_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_I2C_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_I2C_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_SCIF_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SCIF_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_SCIF_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_SCIF_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_SCIF_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_SCIF_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_SCIF_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_SCIF_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_SCIF_RST4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_RSTMON_SCIF_RST4_MON_Pos (4UL) +#define R_CPG_CPG_RSTMON_SCIF_RST5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_RSTMON_SCIF_RST5_MON_Pos (5UL) +#define R_CPG_CPG_RSTMON_SCI_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SCI_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_SCI_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_SCI_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_IRDA_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_IRDA_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_RSPI_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_RSPI_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_RSPI_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_RSPI_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_RSPI_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_RSPI_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_RSPI_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_RSPI_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_RSPI_RST4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_RSTMON_RSPI_RST4_MON_Pos (4UL) +#define R_CPG_CPG_RSTMON_CANFD_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_CANFD_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_CANFD_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_CANFD_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_GPIO_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_GPIO_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_GPIO_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_GPIO_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_GPIO_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_GPIO_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_ADC_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_ADC_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_ADC_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_ADC_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_TSU_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_TSU_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_AXI_ACPU_BUS_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_AXI_ACPU_BUS_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_AXI_MCPU_BUS_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_AXI_MCPU_BUS_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_AXI_COM_BUS_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_AXI_COM_BUS_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_AXI_COM_BUS_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_AXI_COM_BUS_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_PERI_COM_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_PERI_COM_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_PERI_COM_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_PERI_COM_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_REG1_BUS_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_REG1_BUS_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_REG0_BUS_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_REG0_BUS_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_PERI_CPU_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_PERI_CPU_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_PERI_CPU_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_PERI_CPU_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_PERI_DDR_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_PERI_DDR_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_AXI_TZCDDR_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_AXI_TZCDDR_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_AXI_TZCDDR_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_AXI_TZCDDR_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_AXI_TZCDDR_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_AXI_TZCDDR_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_AXI_TZCDDR_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_AXI_TZCDDR_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_OCTA_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_OCTA_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_OTFDE_DDR_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_OTFDE_DDR_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_OTFDE_DDR_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_OTFDE_DDR_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_OTFDE_SPI_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_OTFDE_SPI_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_OTFDE_SPI_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_OTFDE_SPI_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_PDM_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_PDM_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_PCI_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_PCI_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_PCI_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_PCI_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_PCI_RST2_MON_Msk (0x00000004UL) +#define R_CPG_CPG_RSTMON_PCI_RST2_MON_Pos (2UL) +#define R_CPG_CPG_RSTMON_PCI_RST3_MON_Msk (0x00000008UL) +#define R_CPG_CPG_RSTMON_PCI_RST3_MON_Pos (3UL) +#define R_CPG_CPG_RSTMON_PCI_RST4_MON_Msk (0x00000010UL) +#define R_CPG_CPG_RSTMON_PCI_RST4_MON_Pos (4UL) +#define R_CPG_CPG_RSTMON_PCI_RST5_MON_Msk (0x00000020UL) +#define R_CPG_CPG_RSTMON_PCI_RST5_MON_Pos (5UL) +#define R_CPG_CPG_RSTMON_PCI_RST6_MON_Msk (0x00000040UL) +#define R_CPG_CPG_RSTMON_PCI_RST6_MON_Pos (6UL) +#define R_CPG_CPG_RSTMON_SPDIF_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_SPDIF_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_I3C_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_I3C_RST0_MON_Pos (0UL) +#define R_CPG_CPG_RSTMON_I3C_RST1_MON_Msk (0x00000002UL) +#define R_CPG_CPG_RSTMON_I3C_RST1_MON_Pos (1UL) +#define R_CPG_CPG_RSTMON_VBAT_RST0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_RSTMON_VBAT_RST0_MON_Pos (0UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF0_Msk (0x00000001UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF0_Pos (0UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF1_Msk (0x00000002UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF1_Pos (1UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF2_Msk (0x00000004UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF2_Pos (2UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF0_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF0_WEN_Pos (16UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF1_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF1_WEN_Pos (17UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF2_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_WDTOVF_RST_WDTOVF2_WEN_Pos (18UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL0_Msk (0x00000001UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL0_Pos (0UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL1_Msk (0x00000002UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL1_Pos (1UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL2_Msk (0x00000004UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL2_Pos (2UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL4_Msk (0x00000010UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL4_Pos (4UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL5_Msk (0x00000020UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL5_Pos (5UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL6_Msk (0x00000040UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL6_Pos (6UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL8_Msk (0x00000100UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL8_Pos (8UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL9_Msk (0x00000200UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL9_Pos (9UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL10_Msk (0x00000400UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL10_Pos (10UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL0_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL0_WEN_Pos (16UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL1_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL1_WEN_Pos (17UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL2_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL2_WEN_Pos (18UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL4_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL4_WEN_Pos (20UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL5_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL5_WEN_Pos (21UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL6_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL6_WEN_Pos (22UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL8_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL8_WEN_Pos (24UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL9_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL9_WEN_Pos (25UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL10_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_WDTRST_SEL_WDTRSTSEL10_WEN_Pos (26UL) +#define R_CPG_CPG_CLUSTER_PCHMON_PACCEPT_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CLUSTER_PCHMON_PACCEPT_MON_Pos (0UL) +#define R_CPG_CPG_CLUSTER_PCHMON_PDENY_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CLUSTER_PCHMON_PDENY_MON_Pos (1UL) +#define R_CPG_CPG_CLUSTER_PCHCTL_PREQ_SET_Msk (0x00000001UL) +#define R_CPG_CPG_CLUSTER_PCHCTL_PREQ_SET_Pos (0UL) +#define R_CPG_CPG_CLUSTER_PCHCTL_PSTATE0_SET_Msk (0x007F0000UL) +#define R_CPG_CPG_CLUSTER_PCHCTL_PSTATE0_SET_Pos (16UL) +#define R_CPG_CPG_CORE0_PCHMON_PACCEPT0_MON_Msk (0x00000001UL) +#define R_CPG_CPG_CORE0_PCHMON_PACCEPT0_MON_Pos (0UL) +#define R_CPG_CPG_CORE0_PCHMON_PDENY0_MON_Msk (0x00000002UL) +#define R_CPG_CPG_CORE0_PCHMON_PDENY0_MON_Pos (1UL) +#define R_CPG_CPG_CORE0_PCHCTL_PREQ0_SET_Msk (0x00000001UL) +#define R_CPG_CPG_CORE0_PCHCTL_PREQ0_SET_Pos (0UL) +#define R_CPG_CPG_CORE0_PCHCTL_PSTATE0_SET_Msk (0x003F0000UL) +#define R_CPG_CPG_CORE0_PCHCTL_PSTATE0_SET_Pos (16UL) +#define R_CPG_CPG_BUS_ACPU_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_ACPU_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_ACPU_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_ACPU_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP3_ON_Pos (3UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP4_ON_Pos (4UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP5_ON_Pos (5UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP6_ON_Pos (6UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP7_ON_Pos (7UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP8_ON_Pos (8UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP9_ON_Pos (9UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP10_ON_Pos (10UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP11_ON_Pos (11UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP12_ON_Msk (0x00001000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP12_ON_Pos (12UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP13_ON_Msk (0x00002000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP13_ON_Pos (13UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP14_ON_Msk (0x00004000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP14_ON_Pos (14UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP15_ON_Msk (0x00008000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP15_ON_Pos (15UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP7_ON_WEN_Msk (0x00800000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP7_ON_WEN_Pos (23UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP10_ON_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP10_ON_WEN_Pos (26UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP11_ON_WEN_Msk (0x08000000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP11_ON_WEN_Pos (27UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP12_ON_WEN_Msk (0x10000000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP12_ON_WEN_Pos (28UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP13_ON_WEN_Msk (0x20000000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP13_ON_WEN_Pos (29UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP14_ON_WEN_Msk (0x40000000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP14_ON_WEN_Pos (30UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP15_ON_WEN_Msk (0x80000000UL) +#define R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP15_ON_WEN_Pos (31UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP3_ON_Pos (3UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP4_ON_Pos (4UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP5_ON_Pos (5UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP6_ON_Pos (6UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP7_ON_Pos (7UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP8_ON_Pos (8UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP9_ON_Pos (9UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP10_ON_Pos (10UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP11_ON_Pos (11UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP12_ON_Msk (0x00001000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP12_ON_Pos (12UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP13_ON_Msk (0x00002000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP13_ON_Pos (13UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP14_ON_Msk (0x00004000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP14_ON_Pos (14UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP15_ON_Msk (0x00008000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP15_ON_Pos (15UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP7_ON_WEN_Msk (0x00800000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP7_ON_WEN_Pos (23UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP10_ON_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP10_ON_WEN_Pos (26UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP11_ON_WEN_Msk (0x08000000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP11_ON_WEN_Pos (27UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP12_ON_WEN_Msk (0x10000000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP12_ON_WEN_Pos (28UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP13_ON_WEN_Msk (0x20000000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP13_ON_WEN_Pos (29UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP14_ON_WEN_Msk (0x40000000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP14_ON_WEN_Pos (30UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP15_ON_WEN_Msk (0x80000000UL) +#define R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP15_ON_WEN_Pos (31UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP3_ON_Pos (3UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP4_ON_Pos (4UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP5_ON_Pos (5UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP6_ON_Pos (6UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP7_ON_Pos (7UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP8_ON_Pos (8UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP9_ON_Pos (9UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP10_ON_Pos (10UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP11_ON_Pos (11UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP7_ON_WEN_Msk (0x00800000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP7_ON_WEN_Pos (23UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP10_ON_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP10_ON_WEN_Pos (26UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP11_ON_WEN_Msk (0x08000000UL) +#define R_CPG_CPG_BUS_PERI_COM_MSTOP_MSTOP11_ON_WEN_Pos (27UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP3_ON_Pos (3UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP4_ON_Pos (4UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP6_ON_Pos (6UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP7_ON_Pos (7UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP8_ON_Pos (8UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP9_ON_Pos (9UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP10_ON_Pos (10UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP11_ON_Pos (11UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP12_ON_Msk (0x00001000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP12_ON_Pos (12UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP13_ON_Msk (0x00002000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP13_ON_Pos (13UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP14_ON_Msk (0x00004000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP14_ON_Pos (14UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP15_ON_Msk (0x00008000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP15_ON_Pos (15UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP7_ON_WEN_Msk (0x00800000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP7_ON_WEN_Pos (23UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP10_ON_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP10_ON_WEN_Pos (26UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP11_ON_WEN_Msk (0x08000000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP11_ON_WEN_Pos (27UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP12_ON_WEN_Msk (0x10000000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP12_ON_WEN_Pos (28UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP13_ON_WEN_Msk (0x20000000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP13_ON_WEN_Pos (29UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP14_ON_WEN_Msk (0x40000000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP14_ON_WEN_Pos (30UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP15_ON_WEN_Msk (0x80000000UL) +#define R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP15_ON_WEN_Pos (31UL) +#define R_CPG_CPG_BUS_PERI_DDR_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_PERI_DDR_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_PERI_DDR_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_PERI_DDR_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_PERI_DDR_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_PERI_DDR_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_PERI_DDR_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_PERI_DDR_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP4_ON_Pos (4UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP5_ON_Pos (5UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP6_ON_Pos (6UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP7_ON_Pos (7UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP8_ON_Pos (8UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP9_ON_Pos (9UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP10_ON_Pos (10UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP11_ON_Pos (11UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP7_ON_WEN_Msk (0x00800000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP7_ON_WEN_Pos (23UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP10_ON_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP10_ON_WEN_Pos (26UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP11_ON_WEN_Msk (0x08000000UL) +#define R_CPG_CPG_BUS_REG0_MSTOP_MSTOP11_ON_WEN_Pos (27UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP3_ON_Pos (3UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP5_ON_Pos (5UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP6_ON_Pos (6UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_BUS_REG1_MSTOP_MSTOP6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_TZCDDR_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_MHU_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_MHU_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_MHU_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_MHU_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP3_ON_Pos (3UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP4_ON_Pos (4UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP5_ON_Pos (5UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP6_ON_Pos (6UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP7_ON_Pos (7UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP8_ON_Pos (8UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP9_ON_Pos (9UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP10_ON_Pos (10UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP7_ON_WEN_Msk (0x00800000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP7_ON_WEN_Pos (23UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP10_ON_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP10_ON_WEN_Pos (26UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP0_ON_Pos (0UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP1_ON_Pos (1UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP2_ON_Pos (2UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP3_ON_Pos (3UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP4_ON_Pos (4UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP5_ON_Pos (5UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP6_ON_Pos (6UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP7_ON_Msk (0x00000080UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP7_ON_Pos (7UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP8_ON_Pos (8UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP9_ON_Pos (9UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP7_ON_WEN_Msk (0x00800000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP7_ON_WEN_Pos (23UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_BUS_PERI_CPU2_MSTOP_MSTOP9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN0_ON_Pos (0UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN1_ON_Pos (1UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN2_ON_Pos (2UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN3_ON_Pos (3UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN4_ON_Pos (4UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN5_ON_Msk (0x00000020UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN5_ON_Pos (5UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN6_ON_Msk (0x00000040UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN6_ON_Pos (6UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN8_ON_Msk (0x00000100UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN8_ON_Pos (8UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN9_ON_Msk (0x00000200UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN9_ON_Pos (9UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN10_ON_Msk (0x00000400UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN10_ON_Pos (10UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN11_ON_Msk (0x00000800UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN11_ON_Pos (11UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN12_ON_Msk (0x00001000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN12_ON_Pos (12UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN13_ON_Msk (0x00002000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN13_ON_Pos (13UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN14_ON_Msk (0x00004000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN14_ON_Pos (14UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN15_ON_Msk (0x00008000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN15_ON_Pos (15UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN10_ON_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN10_ON_WEN_Pos (26UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN11_ON_WEN_Msk (0x08000000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN11_ON_WEN_Pos (27UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN12_ON_WEN_Msk (0x10000000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN12_ON_WEN_Pos (28UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN13_ON_WEN_Msk (0x20000000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN13_ON_WEN_Pos (29UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN14_ON_WEN_Msk (0x40000000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN14_ON_WEN_Pos (30UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN15_ON_WEN_Msk (0x80000000UL) +#define R_CPG_CPG_PWRDN_IP1_PWRDN15_ON_WEN_Pos (31UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN0_ON_Pos (0UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN1_ON_Msk (0x00000002UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN1_ON_Pos (1UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN2_ON_Msk (0x00000004UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN2_ON_Pos (2UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN3_ON_Msk (0x00000008UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN3_ON_Pos (3UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN4_ON_Msk (0x00000010UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN4_ON_Pos (4UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_PWRDN_IP2_PWRDN4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_PWRDN_MSTOP_PWRDN0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_PWRDN_MSTOP_PWRDN0_ON_Pos (0UL) +#define R_CPG_CPG_PWRDN_MSTOP_PWRDN0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PWRDN_MSTOP_PWRDN0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_PWRDN_CLKON_PWRDN0_ON_Msk (0x00000001UL) +#define R_CPG_CPG_PWRDN_CLKON_PWRDN0_ON_Pos (0UL) +#define R_CPG_CPG_PWRDN_CLKON_PWRDN0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PWRDN_CLKON_PWRDN0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_PWRDN_RST_PWRDN0_RST_Msk (0x00000001UL) +#define R_CPG_CPG_PWRDN_RST_PWRDN0_RST_Pos (0UL) +#define R_CPG_CPG_PWRDN_RST_PWRDN0_RST_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_PWRDN_RST_PWRDN0_RST_WEN_Pos (16UL) +#define R_CPG_CPG_RET_FUNC1_RSTB_Msk (0x00000001UL) +#define R_CPG_CPG_RET_FUNC1_RSTB_Pos (0UL) +#define R_CPG_CPG_RET_FUNC1_RSTB_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_RET_FUNC1_RSTB_WEN_Pos (16UL) +#define R_CPG_CPG_RET_FUNC2_FUNC_EN_Msk (0x00000007UL) +#define R_CPG_CPG_RET_FUNC2_FUNC_EN_Pos (0UL) +#define R_CPG_CPG_RET_FUNC3_STATUS_Msk (0x00000001UL) +#define R_CPG_CPG_RET_FUNC3_STATUS_Pos (0UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES0_SET_Msk (0x00000001UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES0_SET_Pos (0UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES1_SET_Msk (0x00000002UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES1_SET_Pos (1UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES2_SET_Msk (0x00000004UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES2_SET_Pos (2UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES3_SET_Msk (0x00000008UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES3_SET_Pos (3UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES4_SET_Msk (0x00000010UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES4_SET_Pos (4UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES5_SET_Msk (0x00000020UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES5_SET_Pos (5UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES6_SET_Msk (0x00000040UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES6_SET_Pos (6UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES7_SET_Msk (0x00000080UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES7_SET_Pos (7UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES8_SET_Msk (0x00000100UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES8_SET_Pos (8UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES9_SET_Msk (0x00000200UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES9_SET_Pos (9UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES10_SET_Msk (0x00000400UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES10_SET_Pos (10UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES11_SET_Msk (0x00000800UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES11_SET_Pos (11UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES12_SET_Msk (0x00001000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES12_SET_Pos (12UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES13_SET_Msk (0x00002000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES13_SET_Pos (13UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES14_SET_Msk (0x00004000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES14_SET_Pos (14UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES15_SET_Msk (0x00008000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES15_SET_Pos (15UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES0_ON_WEN_Msk (0x00010000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES0_ON_WEN_Pos (16UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES1_ON_WEN_Msk (0x00020000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES1_ON_WEN_Pos (17UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES2_ON_WEN_Msk (0x00040000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES2_ON_WEN_Pos (18UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES3_ON_WEN_Msk (0x00080000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES3_ON_WEN_Pos (19UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES4_ON_WEN_Msk (0x00100000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES4_ON_WEN_Pos (20UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES5_ON_WEN_Msk (0x00200000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES5_ON_WEN_Pos (21UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES6_ON_WEN_Msk (0x00400000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES6_ON_WEN_Pos (22UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES7_ON_WEN_Msk (0x00800000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES7_ON_WEN_Pos (23UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES8_ON_WEN_Msk (0x01000000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES8_ON_WEN_Pos (24UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES9_ON_WEN_Msk (0x02000000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES9_ON_WEN_Pos (25UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES10_ON_WEN_Msk (0x04000000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES10_ON_WEN_Pos (26UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES11_ON_WEN_Msk (0x08000000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES11_ON_WEN_Pos (27UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES12_ON_WEN_Msk (0x10000000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES12_ON_WEN_Pos (28UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES13_ON_WEN_Msk (0x20000000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES13_ON_WEN_Pos (29UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES14_ON_WEN_Msk (0x40000000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES14_ON_WEN_Pos (30UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES15_ON_WEN_Msk (0x80000000UL) +#define R_CPG_CPG_OTHERFUNC2_REG_RES15_ON_WEN_Pos (31UL) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/dmac_b_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/dmac_b_iobitmask.h new file mode 100644 index 00000000..60a2c56c --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/dmac_b_iobitmask.h @@ -0,0 +1,267 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : dmac_b_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for dmac. + *********************************************************************************************************************/ + +#ifndef DMAC_B_IOBITMASK_H +#define DMAC_B_IOBITMASK_H + +#define R_DMAC_B0_GRP_CH_CHSTAT_EN_Msk (0x00000001UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_EN_Pos (0UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_RQST_Msk (0x00000002UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_RQST_Pos (1UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_TACT_Msk (0x00000004UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_TACT_Pos (2UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_SUS_Msk (0x00000008UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_SUS_Pos (3UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_ER_Msk (0x00000010UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_ER_Pos (4UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_END_Msk (0x00000020UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_END_Pos (5UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_TC_Msk (0x00000040UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_TC_Pos (6UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_SR_Msk (0x00000080UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_SR_Pos (7UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_DL_Msk (0x00000100UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_DL_Pos (8UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_DW_Msk (0x00000200UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_DW_Pos (9UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_DER_Msk (0x00000400UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_DER_Pos (10UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_MODE_Msk (0x00000800UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_MODE_Pos (11UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_INTMSK_Msk (0x00010000UL) +#define R_DMAC_B0_GRP_CH_CHSTAT_INTMSK_Pos (16UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_SETEN_Msk (0x00000001UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_SETEN_Pos (0UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLREN_Msk (0x00000002UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLREN_Pos (1UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_STG_Msk (0x00000004UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_STG_Pos (2UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_SWRST_Msk (0x00000008UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_SWRST_Pos (3UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLRRQ_Msk (0x00000010UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLRRQ_Pos (4UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLREND_Msk (0x00000020UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLREND_Pos (5UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLRTC_Msk (0x00000040UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLRTC_Pos (6UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_SETSUS_Msk (0x00000100UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_SETSUS_Pos (8UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLRSUS_Msk (0x00000200UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLRSUS_Pos (9UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_SETINTMSK_Msk (0x00010000UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_SETINTMSK_Pos (16UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLRINTMSK_Msk (0x00020000UL) +#define R_DMAC_B0_GRP_CH_CHCTRL_CLRINTMSK_Pos (17UL) +#define R_DMAC_B0_GRP_CH_CHCFG_SEL_Msk (0x00000007UL) +#define R_DMAC_B0_GRP_CH_CHCFG_SEL_Pos (0UL) +#define R_DMAC_B0_GRP_CH_CHCFG_REQD_Msk (0x00000008UL) +#define R_DMAC_B0_GRP_CH_CHCFG_REQD_Pos (3UL) +#define R_DMAC_B0_GRP_CH_CHCFG_LOEN_Msk (0x00000010UL) +#define R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos (4UL) +#define R_DMAC_B0_GRP_CH_CHCFG_HIEN_Msk (0x00000020UL) +#define R_DMAC_B0_GRP_CH_CHCFG_HIEN_Pos (5UL) +#define R_DMAC_B0_GRP_CH_CHCFG_LVL_Msk (0x00000040UL) +#define R_DMAC_B0_GRP_CH_CHCFG_LVL_Pos (6UL) +#define R_DMAC_B0_GRP_CH_CHCFG_AM_Msk (0x00000700UL) +#define R_DMAC_B0_GRP_CH_CHCFG_AM_Pos (8UL) +#define R_DMAC_B0_GRP_CH_CHCFG_SDS_Msk (0x0000F000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_SDS_Pos (12UL) +#define R_DMAC_B0_GRP_CH_CHCFG_DDS_Msk (0x000F0000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_DDS_Pos (16UL) +#define R_DMAC_B0_GRP_CH_CHCFG_SAD_Msk (0x00100000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_SAD_Pos (20UL) +#define R_DMAC_B0_GRP_CH_CHCFG_DAD_Msk (0x00200000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_DAD_Pos (21UL) +#define R_DMAC_B0_GRP_CH_CHCFG_TM_Msk (0x00400000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_TM_Pos (22UL) +#define R_DMAC_B0_GRP_CH_CHCFG_DEM_Msk (0x01000000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_DEM_Pos (24UL) +#define R_DMAC_B0_GRP_CH_CHCFG_TCM_Msk (0x02000000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_TCM_Pos (25UL) +#define R_DMAC_B0_GRP_CH_CHCFG_SBE_Msk (0x08000000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_SBE_Pos (27UL) +#define R_DMAC_B0_GRP_CH_CHCFG_RSEL_Msk (0x10000000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_RSEL_Pos (28UL) +#define R_DMAC_B0_GRP_CH_CHCFG_RSW_Msk (0x20000000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_RSW_Pos (29UL) +#define R_DMAC_B0_GRP_CH_CHCFG_REN_Msk (0x40000000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_REN_Pos (30UL) +#define R_DMAC_B0_GRP_CH_CHCFG_DMS_Msk (0x80000000UL) +#define R_DMAC_B0_GRP_CH_CHCFG_DMS_Pos (31UL) +#define R_DMAC_B0_GRP_CH_CHITVL_ITVL_Msk (0x0000FFFFUL) +#define R_DMAC_B0_GRP_CH_CHITVL_ITVL_Pos (0UL) +#define R_DMAC_B0_GRP_CH_CHEXT_SPR_Msk (0x00000007UL) +#define R_DMAC_B0_GRP_CH_CHEXT_SPR_Pos (0UL) +#define R_DMAC_B0_GRP_CH_CHEXT_SCA_Msk (0x000000F0UL) +#define R_DMAC_B0_GRP_CH_CHEXT_SCA_Pos (4UL) +#define R_DMAC_B0_GRP_CH_CHEXT_DPR_Msk (0x00000700UL) +#define R_DMAC_B0_GRP_CH_CHEXT_DPR_Pos (8UL) +#define R_DMAC_B0_GRP_CH_CHEXT_DCA_Msk (0x0000F000UL) +#define R_DMAC_B0_GRP_CH_CHEXT_DCA_Pos (12UL) +#define R_DMAC_B0_GRP_DCTRL_PR_Msk (0x00000001UL) +#define R_DMAC_B0_GRP_DCTRL_PR_Pos (0UL) +#define R_DMAC_B0_GRP_DCTRL_LVINT_Msk (0x00000002UL) +#define R_DMAC_B0_GRP_DCTRL_LVINT_Pos (1UL) +#define R_DMAC_B0_GRP_DCTRL_LDPR_Msk (0x00070000UL) +#define R_DMAC_B0_GRP_DCTRL_LDPR_Pos (16UL) +#define R_DMAC_B0_GRP_DCTRL_LDCA_Msk (0x00F00000UL) +#define R_DMAC_B0_GRP_DCTRL_LDCA_Pos (20UL) +#define R_DMAC_B0_GRP_DCTRL_LWPR_Msk (0x07000000UL) +#define R_DMAC_B0_GRP_DCTRL_LWPR_Pos (24UL) +#define R_DMAC_B0_GRP_DCTRL_LWCA_Msk (0xF0000000UL) +#define R_DMAC_B0_GRP_DCTRL_LWCA_Pos (28UL) +#define R_DMAC_B0_GRP_DST_EN_EN0_Msk (0x00000001UL) +#define R_DMAC_B0_GRP_DST_EN_EN0_Pos (0UL) +#define R_DMAC_B0_GRP_DST_EN_EN1_Msk (0x00000002UL) +#define R_DMAC_B0_GRP_DST_EN_EN1_Pos (1UL) +#define R_DMAC_B0_GRP_DST_EN_EN2_Msk (0x00000004UL) +#define R_DMAC_B0_GRP_DST_EN_EN2_Pos (2UL) +#define R_DMAC_B0_GRP_DST_EN_EN3_Msk (0x00000008UL) +#define R_DMAC_B0_GRP_DST_EN_EN3_Pos (3UL) +#define R_DMAC_B0_GRP_DST_EN_EN4_Msk (0x00000010UL) +#define R_DMAC_B0_GRP_DST_EN_EN4_Pos (4UL) +#define R_DMAC_B0_GRP_DST_EN_EN5_Msk (0x00000020UL) +#define R_DMAC_B0_GRP_DST_EN_EN5_Pos (5UL) +#define R_DMAC_B0_GRP_DST_EN_EN6_Msk (0x00000040UL) +#define R_DMAC_B0_GRP_DST_EN_EN6_Pos (6UL) +#define R_DMAC_B0_GRP_DST_EN_EN7_Msk (0x00000080UL) +#define R_DMAC_B0_GRP_DST_EN_EN7_Pos (7UL) +#define R_DMAC_B0_GRP_DST_ER_ER0_Msk (0x00000001UL) +#define R_DMAC_B0_GRP_DST_ER_ER0_Pos (0UL) +#define R_DMAC_B0_GRP_DST_ER_ER1_Msk (0x00000002UL) +#define R_DMAC_B0_GRP_DST_ER_ER1_Pos (1UL) +#define R_DMAC_B0_GRP_DST_ER_ER2_Msk (0x00000004UL) +#define R_DMAC_B0_GRP_DST_ER_ER2_Pos (2UL) +#define R_DMAC_B0_GRP_DST_ER_ER3_Msk (0x00000008UL) +#define R_DMAC_B0_GRP_DST_ER_ER3_Pos (3UL) +#define R_DMAC_B0_GRP_DST_ER_ER4_Msk (0x00000010UL) +#define R_DMAC_B0_GRP_DST_ER_ER4_Pos (4UL) +#define R_DMAC_B0_GRP_DST_ER_ER5_Msk (0x00000020UL) +#define R_DMAC_B0_GRP_DST_ER_ER5_Pos (5UL) +#define R_DMAC_B0_GRP_DST_ER_ER6_Msk (0x00000040UL) +#define R_DMAC_B0_GRP_DST_ER_ER6_Pos (6UL) +#define R_DMAC_B0_GRP_DST_ER_ER7_Msk (0x00000080UL) +#define R_DMAC_B0_GRP_DST_ER_ER7_Pos (7UL) +#define R_DMAC_B0_GRP_DST_END_END0_Msk (0x00000001UL) +#define R_DMAC_B0_GRP_DST_END_END0_Pos (0UL) +#define R_DMAC_B0_GRP_DST_END_END1_Msk (0x00000002UL) +#define R_DMAC_B0_GRP_DST_END_END1_Pos (1UL) +#define R_DMAC_B0_GRP_DST_END_END2_Msk (0x00000004UL) +#define R_DMAC_B0_GRP_DST_END_END2_Pos (2UL) +#define R_DMAC_B0_GRP_DST_END_END3_Msk (0x00000008UL) +#define R_DMAC_B0_GRP_DST_END_END3_Pos (3UL) +#define R_DMAC_B0_GRP_DST_END_END4_Msk (0x00000010UL) +#define R_DMAC_B0_GRP_DST_END_END4_Pos (4UL) +#define R_DMAC_B0_GRP_DST_END_END5_Msk (0x00000020UL) +#define R_DMAC_B0_GRP_DST_END_END5_Pos (5UL) +#define R_DMAC_B0_GRP_DST_END_END6_Msk (0x00000040UL) +#define R_DMAC_B0_GRP_DST_END_END6_Pos (6UL) +#define R_DMAC_B0_GRP_DST_END_END7_Msk (0x00000080UL) +#define R_DMAC_B0_GRP_DST_END_END7_Pos (7UL) +#define R_DMAC_B0_GRP_DST_TC_TC0_Msk (0x00000001UL) +#define R_DMAC_B0_GRP_DST_TC_TC0_Pos (0UL) +#define R_DMAC_B0_GRP_DST_TC_TC1_Msk (0x00000002UL) +#define R_DMAC_B0_GRP_DST_TC_TC1_Pos (1UL) +#define R_DMAC_B0_GRP_DST_TC_TC2_Msk (0x00000004UL) +#define R_DMAC_B0_GRP_DST_TC_TC2_Pos (2UL) +#define R_DMAC_B0_GRP_DST_TC_TC3_Msk (0x00000008UL) +#define R_DMAC_B0_GRP_DST_TC_TC3_Pos (3UL) +#define R_DMAC_B0_GRP_DST_TC_TC4_Msk (0x00000010UL) +#define R_DMAC_B0_GRP_DST_TC_TC4_Pos (4UL) +#define R_DMAC_B0_GRP_DST_TC_TC5_Msk (0x00000020UL) +#define R_DMAC_B0_GRP_DST_TC_TC5_Pos (5UL) +#define R_DMAC_B0_GRP_DST_TC_TC6_Msk (0x00000040UL) +#define R_DMAC_B0_GRP_DST_TC_TC6_Pos (6UL) +#define R_DMAC_B0_GRP_DST_TC_TC7_Msk (0x00000080UL) +#define R_DMAC_B0_GRP_DST_TC_TC7_Pos (7UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS0_Msk (0x00000001UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS0_Pos (0UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS1_Msk (0x00000002UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS1_Pos (1UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS2_Msk (0x00000004UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS2_Pos (2UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS3_Msk (0x00000008UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS3_Pos (3UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS4_Msk (0x00000010UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS4_Pos (4UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS5_Msk (0x00000020UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS5_Pos (5UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS6_Msk (0x00000040UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS6_Pos (6UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS7_Msk (0x00000080UL) +#define R_DMAC_B0_GRP_DST_SUS_SUS7_Pos (7UL) +#define R_DMAC_B0_EX_DMARS0_CH0_RID_Msk (0x00000003UL) +#define R_DMAC_B0_EX_DMARS0_CH0_RID_Pos (0UL) +#define R_DMAC_B0_EX_DMARS0_CH0_MID_Msk (0x000003FCUL) +#define R_DMAC_B0_EX_DMARS0_CH0_MID_Pos (2UL) +#define R_DMAC_B0_EX_DMARS0_CH1_RID_Msk (0x00030000UL) +#define R_DMAC_B0_EX_DMARS0_CH1_RID_Pos (16UL) +#define R_DMAC_B0_EX_DMARS0_CH1_MID_Msk (0x03FC0000UL) +#define R_DMAC_B0_EX_DMARS0_CH1_MID_Pos (18UL) +#define R_DMAC_B0_EX_DMARS1_CH2_RID_Msk (0x00000003UL) +#define R_DMAC_B0_EX_DMARS1_CH2_RID_Pos (0UL) +#define R_DMAC_B0_EX_DMARS1_CH2_MID_Msk (0x000003FCUL) +#define R_DMAC_B0_EX_DMARS1_CH2_MID_Pos (2UL) +#define R_DMAC_B0_EX_DMARS1_CH3_RID_Msk (0x00030000UL) +#define R_DMAC_B0_EX_DMARS1_CH3_RID_Pos (16UL) +#define R_DMAC_B0_EX_DMARS1_CH3_MID_Msk (0x03FC0000UL) +#define R_DMAC_B0_EX_DMARS1_CH3_MID_Pos (18UL) +#define R_DMAC_B0_EX_DMARS2_CH4_RID_Msk (0x00000003UL) +#define R_DMAC_B0_EX_DMARS2_CH4_RID_Pos (0UL) +#define R_DMAC_B0_EX_DMARS2_CH4_MID_Msk (0x000003FCUL) +#define R_DMAC_B0_EX_DMARS2_CH4_MID_Pos (2UL) +#define R_DMAC_B0_EX_DMARS2_CH5_RID_Msk (0x00030000UL) +#define R_DMAC_B0_EX_DMARS2_CH5_RID_Pos (16UL) +#define R_DMAC_B0_EX_DMARS2_CH5_MID_Msk (0x03FC0000UL) +#define R_DMAC_B0_EX_DMARS2_CH5_MID_Pos (18UL) +#define R_DMAC_B0_EX_DMARS3_CH6_RID_Msk (0x00000003UL) +#define R_DMAC_B0_EX_DMARS3_CH6_RID_Pos (0UL) +#define R_DMAC_B0_EX_DMARS3_CH6_MID_Msk (0x000003FCUL) +#define R_DMAC_B0_EX_DMARS3_CH6_MID_Pos (2UL) +#define R_DMAC_B0_EX_DMARS3_CH7_RID_Msk (0x00030000UL) +#define R_DMAC_B0_EX_DMARS3_CH7_RID_Pos (16UL) +#define R_DMAC_B0_EX_DMARS3_CH7_MID_Msk (0x03FC0000UL) +#define R_DMAC_B0_EX_DMARS3_CH7_MID_Pos (18UL) +#define R_DMAC_B0_EX_DMARS4_CH8_RID_Msk (0x00000003UL) +#define R_DMAC_B0_EX_DMARS4_CH8_RID_Pos (0UL) +#define R_DMAC_B0_EX_DMARS4_CH8_MID_Msk (0x000003FCUL) +#define R_DMAC_B0_EX_DMARS4_CH8_MID_Pos (2UL) +#define R_DMAC_B0_EX_DMARS4_CH9_RID_Msk (0x00030000UL) +#define R_DMAC_B0_EX_DMARS4_CH9_RID_Pos (16UL) +#define R_DMAC_B0_EX_DMARS4_CH9_MID_Msk (0x03FC0000UL) +#define R_DMAC_B0_EX_DMARS4_CH9_MID_Pos (18UL) +#define R_DMAC_B0_EX_DMARS5_CH10_RID_Msk (0x00000003UL) +#define R_DMAC_B0_EX_DMARS5_CH10_RID_Pos (0UL) +#define R_DMAC_B0_EX_DMARS5_CH10_MID_Msk (0x000003FCUL) +#define R_DMAC_B0_EX_DMARS5_CH10_MID_Pos (2UL) +#define R_DMAC_B0_EX_DMARS5_CH11_RID_Msk (0x00030000UL) +#define R_DMAC_B0_EX_DMARS5_CH11_RID_Pos (16UL) +#define R_DMAC_B0_EX_DMARS5_CH11_MID_Msk (0x03FC0000UL) +#define R_DMAC_B0_EX_DMARS5_CH11_MID_Pos (18UL) +#define R_DMAC_B0_EX_DMARS6_CH12_RID_Msk (0x00000003UL) +#define R_DMAC_B0_EX_DMARS6_CH12_RID_Pos (0UL) +#define R_DMAC_B0_EX_DMARS6_CH12_MID_Msk (0x000003FCUL) +#define R_DMAC_B0_EX_DMARS6_CH12_MID_Pos (2UL) +#define R_DMAC_B0_EX_DMARS6_CH13_RID_Msk (0x00030000UL) +#define R_DMAC_B0_EX_DMARS6_CH13_RID_Pos (16UL) +#define R_DMAC_B0_EX_DMARS6_CH13_MID_Msk (0x03FC0000UL) +#define R_DMAC_B0_EX_DMARS6_CH13_MID_Pos (18UL) +#define R_DMAC_B0_EX_DMARS7_CH14_RID_Msk (0x00000003UL) +#define R_DMAC_B0_EX_DMARS7_CH14_RID_Pos (0UL) +#define R_DMAC_B0_EX_DMARS7_CH14_MID_Msk (0x000003FCUL) +#define R_DMAC_B0_EX_DMARS7_CH14_MID_Pos (2UL) +#define R_DMAC_B0_EX_DMARS7_CH15_RID_Msk (0x00030000UL) +#define R_DMAC_B0_EX_DMARS7_CH15_RID_Pos (16UL) +#define R_DMAC_B0_EX_DMARS7_CH15_MID_Msk (0x03FC0000UL) +#define R_DMAC_B0_EX_DMARS7_CH15_MID_Pos (18UL) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gpio_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gpio_iobitmask.h new file mode 100644 index 00000000..2b7d96b4 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gpio_iobitmask.h @@ -0,0 +1,1959 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : gpio_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for gpio. + *********************************************************************************************************************/ + +#ifndef GPIO_IOBITMASK_H +#define GPIO_IOBITMASK_H + +#define R_GPIO_P_20_P0_Msk (0x01UL) +#define R_GPIO_P_20_P0_Pos (0UL) +#define R_GPIO_P_20_P1_Msk (0x02UL) +#define R_GPIO_P_20_P1_Pos (1UL) +#define R_GPIO_P_20_P2_Msk (0x04UL) +#define R_GPIO_P_20_P2_Pos (2UL) +#define R_GPIO_P_20_P3_Msk (0x08UL) +#define R_GPIO_P_20_P3_Pos (3UL) +#define R_GPIO_P_21_P0_Msk (0x01UL) +#define R_GPIO_P_21_P0_Pos (0UL) +#define R_GPIO_P_21_P1_Msk (0x02UL) +#define R_GPIO_P_21_P1_Pos (1UL) +#define R_GPIO_P_21_P2_Msk (0x04UL) +#define R_GPIO_P_21_P2_Pos (2UL) +#define R_GPIO_P_21_P3_Msk (0x08UL) +#define R_GPIO_P_21_P3_Pos (3UL) +#define R_GPIO_P_21_P4_Msk (0x10UL) +#define R_GPIO_P_21_P4_Pos (4UL) +#define R_GPIO_P_22_P0_Msk (0x01UL) +#define R_GPIO_P_22_P0_Pos (0UL) +#define R_GPIO_P_22_P1_Msk (0x02UL) +#define R_GPIO_P_22_P1_Pos (1UL) +#define R_GPIO_P_22_P2_Msk (0x04UL) +#define R_GPIO_P_22_P2_Pos (2UL) +#define R_GPIO_P_22_P3_Msk (0x08UL) +#define R_GPIO_P_22_P3_Pos (3UL) +#define R_GPIO_P_22_P4_Msk (0x10UL) +#define R_GPIO_P_22_P4_Pos (4UL) +#define R_GPIO_P_23_P0_Msk (0x01UL) +#define R_GPIO_P_23_P0_Pos (0UL) +#define R_GPIO_P_23_P1_Msk (0x02UL) +#define R_GPIO_P_23_P1_Pos (1UL) +#define R_GPIO_P_23_P2_Msk (0x04UL) +#define R_GPIO_P_23_P2_Pos (2UL) +#define R_GPIO_P_23_P3_Msk (0x08UL) +#define R_GPIO_P_23_P3_Pos (3UL) +#define R_GPIO_P_24_P0_Msk (0x01UL) +#define R_GPIO_P_24_P0_Pos (0UL) +#define R_GPIO_P_24_P1_Msk (0x02UL) +#define R_GPIO_P_24_P1_Pos (1UL) +#define R_GPIO_P_25_P0_Msk (0x01UL) +#define R_GPIO_P_25_P0_Pos (0UL) +#define R_GPIO_P_25_P1_Msk (0x02UL) +#define R_GPIO_P_25_P1_Pos (1UL) +#define R_GPIO_P_25_P2_Msk (0x04UL) +#define R_GPIO_P_25_P2_Pos (2UL) +#define R_GPIO_P_25_P3_Msk (0x08UL) +#define R_GPIO_P_25_P3_Pos (3UL) +#define R_GPIO_P_25_P4_Msk (0x10UL) +#define R_GPIO_P_25_P4_Pos (4UL) +#define R_GPIO_P_26_P0_Msk (0x01UL) +#define R_GPIO_P_26_P0_Pos (0UL) +#define R_GPIO_P_26_P1_Msk (0x02UL) +#define R_GPIO_P_26_P1_Pos (1UL) +#define R_GPIO_P_26_P2_Msk (0x04UL) +#define R_GPIO_P_26_P2_Pos (2UL) +#define R_GPIO_P_27_P0_Msk (0x01UL) +#define R_GPIO_P_27_P0_Pos (0UL) +#define R_GPIO_P_27_P1_Msk (0x02UL) +#define R_GPIO_P_27_P1_Pos (1UL) +#define R_GPIO_P_27_P2_Msk (0x04UL) +#define R_GPIO_P_27_P2_Pos (2UL) +#define R_GPIO_P_27_P3_Msk (0x08UL) +#define R_GPIO_P_27_P3_Pos (3UL) +#define R_GPIO_P_28_P0_Msk (0x01UL) +#define R_GPIO_P_28_P0_Pos (0UL) +#define R_GPIO_P_28_P1_Msk (0x02UL) +#define R_GPIO_P_28_P1_Pos (1UL) +#define R_GPIO_P_29_P0_Msk (0x01UL) +#define R_GPIO_P_29_P0_Pos (0UL) +#define R_GPIO_P_29_P1_Msk (0x02UL) +#define R_GPIO_P_29_P1_Pos (1UL) +#define R_GPIO_P_29_P2_Msk (0x04UL) +#define R_GPIO_P_29_P2_Pos (2UL) +#define R_GPIO_P_29_P3_Msk (0x08UL) +#define R_GPIO_P_29_P3_Pos (3UL) +#define R_GPIO_P_2A_P0_Msk (0x01UL) +#define R_GPIO_P_2A_P0_Pos (0UL) +#define R_GPIO_P_2A_P1_Msk (0x02UL) +#define R_GPIO_P_2A_P1_Pos (1UL) +#define R_GPIO_P_2A_P2_Msk (0x04UL) +#define R_GPIO_P_2A_P2_Pos (2UL) +#define R_GPIO_P_2A_P3_Msk (0x08UL) +#define R_GPIO_P_2A_P3_Pos (3UL) +#define R_GPIO_P_2A_P4_Msk (0x10UL) +#define R_GPIO_P_2A_P4_Pos (4UL) +#define R_GPIO_P_2A_P5_Msk (0x20UL) +#define R_GPIO_P_2A_P5_Pos (5UL) +#define R_GPIO_P_30_P0_Msk (0x01UL) +#define R_GPIO_P_30_P0_Pos (0UL) +#define R_GPIO_P_30_P1_Msk (0x02UL) +#define R_GPIO_P_30_P1_Pos (1UL) +#define R_GPIO_P_30_P2_Msk (0x04UL) +#define R_GPIO_P_30_P2_Pos (2UL) +#define R_GPIO_P_30_P3_Msk (0x08UL) +#define R_GPIO_P_30_P3_Pos (3UL) +#define R_GPIO_P_30_P4_Msk (0x10UL) +#define R_GPIO_P_30_P4_Pos (4UL) +#define R_GPIO_P_31_P0_Msk (0x01UL) +#define R_GPIO_P_31_P0_Pos (0UL) +#define R_GPIO_P_31_P1_Msk (0x02UL) +#define R_GPIO_P_31_P1_Pos (1UL) +#define R_GPIO_P_31_P2_Msk (0x04UL) +#define R_GPIO_P_31_P2_Pos (2UL) +#define R_GPIO_P_31_P3_Msk (0x08UL) +#define R_GPIO_P_31_P3_Pos (3UL) +#define R_GPIO_P_32_P0_Msk (0x01UL) +#define R_GPIO_P_32_P0_Pos (0UL) +#define R_GPIO_P_32_P1_Msk (0x02UL) +#define R_GPIO_P_32_P1_Pos (1UL) +#define R_GPIO_P_32_P2_Msk (0x04UL) +#define R_GPIO_P_32_P2_Pos (2UL) +#define R_GPIO_P_32_P3_Msk (0x08UL) +#define R_GPIO_P_32_P3_Pos (3UL) +#define R_GPIO_P_33_P0_Msk (0x01UL) +#define R_GPIO_P_33_P0_Pos (0UL) +#define R_GPIO_P_33_P1_Msk (0x02UL) +#define R_GPIO_P_33_P1_Pos (1UL) +#define R_GPIO_P_33_P2_Msk (0x04UL) +#define R_GPIO_P_33_P2_Pos (2UL) +#define R_GPIO_P_33_P3_Msk (0x08UL) +#define R_GPIO_P_33_P3_Pos (3UL) +#define R_GPIO_P_33_P4_Msk (0x10UL) +#define R_GPIO_P_33_P4_Pos (4UL) +#define R_GPIO_P_33_P5_Msk (0x20UL) +#define R_GPIO_P_33_P5_Pos (5UL) +#define R_GPIO_P_34_P0_Msk (0x01UL) +#define R_GPIO_P_34_P0_Pos (0UL) +#define R_GPIO_P_34_P1_Msk (0x02UL) +#define R_GPIO_P_34_P1_Pos (1UL) +#define R_GPIO_P_34_P2_Msk (0x04UL) +#define R_GPIO_P_34_P2_Pos (2UL) +#define R_GPIO_P_34_P3_Msk (0x08UL) +#define R_GPIO_P_34_P3_Pos (3UL) +#define R_GPIO_P_34_P4_Msk (0x10UL) +#define R_GPIO_P_34_P4_Pos (4UL) +#define R_GPIO_P_35_P0_Msk (0x01UL) +#define R_GPIO_P_35_P0_Pos (0UL) +#define R_GPIO_P_35_P1_Msk (0x02UL) +#define R_GPIO_P_35_P1_Pos (1UL) +#define R_GPIO_P_35_P2_Msk (0x04UL) +#define R_GPIO_P_35_P2_Pos (2UL) +#define R_GPIO_P_35_P3_Msk (0x08UL) +#define R_GPIO_P_35_P3_Pos (3UL) +#define R_GPIO_P_35_P4_Msk (0x10UL) +#define R_GPIO_P_35_P4_Pos (4UL) +#define R_GPIO_P_36_P0_Msk (0x01UL) +#define R_GPIO_P_36_P0_Pos (0UL) +#define R_GPIO_P_36_P1_Msk (0x02UL) +#define R_GPIO_P_36_P1_Pos (1UL) +#define R_GPIO_P_36_P2_Msk (0x04UL) +#define R_GPIO_P_36_P2_Pos (2UL) +#define R_GPIO_P_36_P3_Msk (0x08UL) +#define R_GPIO_P_36_P3_Pos (3UL) +#define R_GPIO_P_37_P0_Msk (0x01UL) +#define R_GPIO_P_37_P0_Pos (0UL) +#define R_GPIO_P_37_P1_Msk (0x02UL) +#define R_GPIO_P_37_P1_Pos (1UL) +#define R_GPIO_P_37_P2_Msk (0x04UL) +#define R_GPIO_P_37_P2_Pos (2UL) +#define R_GPIO_P_37_P3_Msk (0x08UL) +#define R_GPIO_P_37_P3_Pos (3UL) +#define R_GPIO_P_37_P4_Msk (0x10UL) +#define R_GPIO_P_37_P4_Pos (4UL) +#define R_GPIO_PM_20_PM20_0_Msk (0x0003UL) +#define R_GPIO_PM_20_PM20_0_Pos (0UL) +#define R_GPIO_PM_20_PM20_1_Msk (0x000CUL) +#define R_GPIO_PM_20_PM20_1_Pos (2UL) +#define R_GPIO_PM_20_PM20_2_Msk (0x0030UL) +#define R_GPIO_PM_20_PM20_2_Pos (4UL) +#define R_GPIO_PM_20_PM20_3_Msk (0x00C0UL) +#define R_GPIO_PM_20_PM20_3_Pos (6UL) +#define R_GPIO_PM_21_PM21_0_Msk (0x0003UL) +#define R_GPIO_PM_21_PM21_0_Pos (0UL) +#define R_GPIO_PM_21_PM21_1_Msk (0x000CUL) +#define R_GPIO_PM_21_PM21_1_Pos (2UL) +#define R_GPIO_PM_21_PM21_2_Msk (0x0030UL) +#define R_GPIO_PM_21_PM21_2_Pos (4UL) +#define R_GPIO_PM_21_PM21_3_Msk (0x00C0UL) +#define R_GPIO_PM_21_PM21_3_Pos (6UL) +#define R_GPIO_PM_21_PM21_4_Msk (0x0300UL) +#define R_GPIO_PM_21_PM21_4_Pos (8UL) +#define R_GPIO_PM_22_PM22_0_Msk (0x0003UL) +#define R_GPIO_PM_22_PM22_0_Pos (0UL) +#define R_GPIO_PM_22_PM22_1_Msk (0x000CUL) +#define R_GPIO_PM_22_PM22_1_Pos (2UL) +#define R_GPIO_PM_22_PM22_2_Msk (0x0030UL) +#define R_GPIO_PM_22_PM22_2_Pos (4UL) +#define R_GPIO_PM_22_PM22_3_Msk (0x00C0UL) +#define R_GPIO_PM_22_PM22_3_Pos (6UL) +#define R_GPIO_PM_22_PM22_4_Msk (0x0300UL) +#define R_GPIO_PM_22_PM22_4_Pos (8UL) +#define R_GPIO_PM_23_PM23_0_Msk (0x0003UL) +#define R_GPIO_PM_23_PM23_0_Pos (0UL) +#define R_GPIO_PM_23_PM23_1_Msk (0x000CUL) +#define R_GPIO_PM_23_PM23_1_Pos (2UL) +#define R_GPIO_PM_23_PM23_2_Msk (0x0030UL) +#define R_GPIO_PM_23_PM23_2_Pos (4UL) +#define R_GPIO_PM_23_PM23_3_Msk (0x00C0UL) +#define R_GPIO_PM_23_PM23_3_Pos (6UL) +#define R_GPIO_PM_24_PM24_0_Msk (0x0003UL) +#define R_GPIO_PM_24_PM24_0_Pos (0UL) +#define R_GPIO_PM_24_PM24_1_Msk (0x000CUL) +#define R_GPIO_PM_24_PM24_1_Pos (2UL) +#define R_GPIO_PM_25_PM25_0_Msk (0x0003UL) +#define R_GPIO_PM_25_PM25_0_Pos (0UL) +#define R_GPIO_PM_25_PM25_1_Msk (0x000CUL) +#define R_GPIO_PM_25_PM25_1_Pos (2UL) +#define R_GPIO_PM_25_PM25_2_Msk (0x0030UL) +#define R_GPIO_PM_25_PM25_2_Pos (4UL) +#define R_GPIO_PM_25_PM25_3_Msk (0x00C0UL) +#define R_GPIO_PM_25_PM25_3_Pos (6UL) +#define R_GPIO_PM_26_PM26_0_Msk (0x0003UL) +#define R_GPIO_PM_26_PM26_0_Pos (0UL) +#define R_GPIO_PM_26_PM26_1_Msk (0x000CUL) +#define R_GPIO_PM_26_PM26_1_Pos (2UL) +#define R_GPIO_PM_26_PM26_2_Msk (0x0030UL) +#define R_GPIO_PM_26_PM26_2_Pos (4UL) +#define R_GPIO_PM_27_PM27_0_Msk (0x0003UL) +#define R_GPIO_PM_27_PM27_0_Pos (0UL) +#define R_GPIO_PM_27_PM27_1_Msk (0x000CUL) +#define R_GPIO_PM_27_PM27_1_Pos (2UL) +#define R_GPIO_PM_27_PM27_2_Msk (0x0030UL) +#define R_GPIO_PM_27_PM27_2_Pos (4UL) +#define R_GPIO_PM_27_PM27_3_Msk (0x00C0UL) +#define R_GPIO_PM_27_PM27_3_Pos (6UL) +#define R_GPIO_PM_28_PM28_0_Msk (0x0003UL) +#define R_GPIO_PM_28_PM28_0_Pos (0UL) +#define R_GPIO_PM_28_PM28_1_Msk (0x000CUL) +#define R_GPIO_PM_28_PM28_1_Pos (2UL) +#define R_GPIO_PM_29_PM29_0_Msk (0x0003UL) +#define R_GPIO_PM_29_PM29_0_Pos (0UL) +#define R_GPIO_PM_29_PM29_1_Msk (0x000CUL) +#define R_GPIO_PM_29_PM29_1_Pos (2UL) +#define R_GPIO_PM_29_PM29_2_Msk (0x0030UL) +#define R_GPIO_PM_29_PM29_2_Pos (4UL) +#define R_GPIO_PM_29_PM29_3_Msk (0x00C0UL) +#define R_GPIO_PM_29_PM29_3_Pos (6UL) +#define R_GPIO_PM_2A_PM2A_0_Msk (0x0003UL) +#define R_GPIO_PM_2A_PM2A_0_Pos (0UL) +#define R_GPIO_PM_2A_PM2A_1_Msk (0x000CUL) +#define R_GPIO_PM_2A_PM2A_1_Pos (2UL) +#define R_GPIO_PM_2A_PM2A_2_Msk (0x0030UL) +#define R_GPIO_PM_2A_PM2A_2_Pos (4UL) +#define R_GPIO_PM_2A_PM2A_3_Msk (0x00C0UL) +#define R_GPIO_PM_2A_PM2A_3_Pos (6UL) +#define R_GPIO_PM_2A_PM2A_4_Msk (0x0300UL) +#define R_GPIO_PM_2A_PM2A_4_Pos (8UL) +#define R_GPIO_PM_2A_PM2A_5_Msk (0x0C00UL) +#define R_GPIO_PM_2A_PM2A_5_Pos (10UL) +#define R_GPIO_PM_30_PM30_0_Msk (0x0003UL) +#define R_GPIO_PM_30_PM30_0_Pos (0UL) +#define R_GPIO_PM_30_PM30_1_Msk (0x000CUL) +#define R_GPIO_PM_30_PM30_1_Pos (2UL) +#define R_GPIO_PM_30_PM30_2_Msk (0x0030UL) +#define R_GPIO_PM_30_PM30_2_Pos (4UL) +#define R_GPIO_PM_30_PM30_3_Msk (0x00C0UL) +#define R_GPIO_PM_30_PM30_3_Pos (6UL) +#define R_GPIO_PM_31_PM31_0_Msk (0x0003UL) +#define R_GPIO_PM_31_PM31_0_Pos (0UL) +#define R_GPIO_PM_31_PM31_1_Msk (0x000CUL) +#define R_GPIO_PM_31_PM31_1_Pos (2UL) +#define R_GPIO_PM_31_PM31_2_Msk (0x0030UL) +#define R_GPIO_PM_31_PM31_2_Pos (4UL) +#define R_GPIO_PM_32_PM32_0_Msk (0x0003UL) +#define R_GPIO_PM_32_PM32_0_Pos (0UL) +#define R_GPIO_PM_32_PM32_1_Msk (0x000CUL) +#define R_GPIO_PM_32_PM32_1_Pos (2UL) +#define R_GPIO_PM_32_PM32_2_Msk (0x0030UL) +#define R_GPIO_PM_32_PM32_2_Pos (4UL) +#define R_GPIO_PM_33_PM33_0_Msk (0x0003UL) +#define R_GPIO_PM_33_PM33_0_Pos (0UL) +#define R_GPIO_PM_33_PM33_1_Msk (0x000CUL) +#define R_GPIO_PM_33_PM33_1_Pos (2UL) +#define R_GPIO_PM_33_PM33_2_Msk (0x0030UL) +#define R_GPIO_PM_33_PM33_2_Pos (4UL) +#define R_GPIO_PM_33_PM33_3_Msk (0x00C0UL) +#define R_GPIO_PM_33_PM33_3_Pos (6UL) +#define R_GPIO_PM_33_PM33_4_Msk (0x0300UL) +#define R_GPIO_PM_33_PM33_4_Pos (8UL) +#define R_GPIO_PM_33_PM33_5_Msk (0x0C00UL) +#define R_GPIO_PM_33_PM33_5_Pos (10UL) +#define R_GPIO_PM_34_PM34_0_Msk (0x0003UL) +#define R_GPIO_PM_34_PM34_0_Pos (0UL) +#define R_GPIO_PM_34_PM34_1_Msk (0x000CUL) +#define R_GPIO_PM_34_PM34_1_Pos (2UL) +#define R_GPIO_PM_34_PM34_2_Msk (0x0030UL) +#define R_GPIO_PM_34_PM34_2_Pos (4UL) +#define R_GPIO_PM_34_PM34_3_Msk (0x00C0UL) +#define R_GPIO_PM_34_PM34_3_Pos (6UL) +#define R_GPIO_PM_35_PM35_0_Msk (0x0003UL) +#define R_GPIO_PM_35_PM35_0_Pos (0UL) +#define R_GPIO_PM_35_PM35_1_Msk (0x000CUL) +#define R_GPIO_PM_35_PM35_1_Pos (2UL) +#define R_GPIO_PM_35_PM35_2_Msk (0x0030UL) +#define R_GPIO_PM_35_PM35_2_Pos (4UL) +#define R_GPIO_PM_35_PM35_3_Msk (0x00C0UL) +#define R_GPIO_PM_35_PM35_3_Pos (6UL) +#define R_GPIO_PM_36_PM36_0_Msk (0x0003UL) +#define R_GPIO_PM_36_PM36_0_Pos (0UL) +#define R_GPIO_PM_36_PM36_1_Msk (0x000CUL) +#define R_GPIO_PM_36_PM36_1_Pos (2UL) +#define R_GPIO_PM_36_PM36_2_Msk (0x0030UL) +#define R_GPIO_PM_36_PM36_2_Pos (4UL) +#define R_GPIO_PM_37_PM37_0_Msk (0x0003UL) +#define R_GPIO_PM_37_PM37_0_Pos (0UL) +#define R_GPIO_PM_37_PM37_1_Msk (0x000CUL) +#define R_GPIO_PM_37_PM37_1_Pos (2UL) +#define R_GPIO_PM_37_PM37_2_Msk (0x0030UL) +#define R_GPIO_PM_37_PM37_2_Pos (4UL) +#define R_GPIO_PM_37_PM37_3_Msk (0x00C0UL) +#define R_GPIO_PM_37_PM37_3_Pos (6UL) +#define R_GPIO_PMC_20_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_20_PMC0_Pos (0UL) +#define R_GPIO_PMC_20_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_20_PMC1_Pos (1UL) +#define R_GPIO_PMC_20_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_20_PMC2_Pos (2UL) +#define R_GPIO_PMC_20_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_20_PMC3_Pos (3UL) +#define R_GPIO_PMC_21_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_21_PMC0_Pos (0UL) +#define R_GPIO_PMC_21_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_21_PMC1_Pos (1UL) +#define R_GPIO_PMC_21_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_21_PMC2_Pos (2UL) +#define R_GPIO_PMC_21_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_21_PMC3_Pos (3UL) +#define R_GPIO_PMC_21_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_21_PMC4_Pos (4UL) +#define R_GPIO_PMC_22_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_22_PMC0_Pos (0UL) +#define R_GPIO_PMC_22_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_22_PMC1_Pos (1UL) +#define R_GPIO_PMC_22_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_22_PMC2_Pos (2UL) +#define R_GPIO_PMC_22_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_22_PMC3_Pos (3UL) +#define R_GPIO_PMC_22_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_22_PMC4_Pos (4UL) +#define R_GPIO_PMC_23_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_23_PMC0_Pos (0UL) +#define R_GPIO_PMC_23_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_23_PMC1_Pos (1UL) +#define R_GPIO_PMC_23_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_23_PMC2_Pos (2UL) +#define R_GPIO_PMC_23_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_23_PMC3_Pos (3UL) +#define R_GPIO_PMC_24_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_24_PMC0_Pos (0UL) +#define R_GPIO_PMC_24_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_24_PMC1_Pos (1UL) +#define R_GPIO_PMC_25_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_25_PMC0_Pos (0UL) +#define R_GPIO_PMC_25_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_25_PMC1_Pos (1UL) +#define R_GPIO_PMC_25_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_25_PMC2_Pos (2UL) +#define R_GPIO_PMC_25_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_25_PMC3_Pos (3UL) +#define R_GPIO_PMC_25_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_25_PMC4_Pos (4UL) +#define R_GPIO_PMC_26_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_26_PMC0_Pos (0UL) +#define R_GPIO_PMC_26_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_26_PMC1_Pos (1UL) +#define R_GPIO_PMC_26_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_26_PMC2_Pos (2UL) +#define R_GPIO_PMC_27_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_27_PMC0_Pos (0UL) +#define R_GPIO_PMC_27_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_27_PMC1_Pos (1UL) +#define R_GPIO_PMC_27_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_27_PMC2_Pos (2UL) +#define R_GPIO_PMC_27_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_27_PMC3_Pos (3UL) +#define R_GPIO_PMC_28_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_28_PMC0_Pos (0UL) +#define R_GPIO_PMC_28_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_28_PMC1_Pos (1UL) +#define R_GPIO_PMC_29_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_29_PMC0_Pos (0UL) +#define R_GPIO_PMC_29_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_29_PMC1_Pos (1UL) +#define R_GPIO_PMC_29_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_29_PMC2_Pos (2UL) +#define R_GPIO_PMC_29_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_29_PMC3_Pos (3UL) +#define R_GPIO_PMC_2A_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_2A_PMC0_Pos (0UL) +#define R_GPIO_PMC_2A_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_2A_PMC1_Pos (1UL) +#define R_GPIO_PMC_2A_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_2A_PMC2_Pos (2UL) +#define R_GPIO_PMC_2A_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_2A_PMC3_Pos (3UL) +#define R_GPIO_PMC_2A_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_2A_PMC4_Pos (4UL) +#define R_GPIO_PMC_2A_PMC5_Msk (0x20UL) +#define R_GPIO_PMC_2A_PMC5_Pos (5UL) +#define R_GPIO_PMC_30_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_30_PMC0_Pos (0UL) +#define R_GPIO_PMC_30_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_30_PMC1_Pos (1UL) +#define R_GPIO_PMC_30_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_30_PMC2_Pos (2UL) +#define R_GPIO_PMC_30_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_30_PMC3_Pos (3UL) +#define R_GPIO_PMC_30_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_30_PMC4_Pos (4UL) +#define R_GPIO_PMC_31_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_31_PMC0_Pos (0UL) +#define R_GPIO_PMC_31_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_31_PMC1_Pos (1UL) +#define R_GPIO_PMC_31_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_31_PMC2_Pos (2UL) +#define R_GPIO_PMC_31_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_31_PMC3_Pos (3UL) +#define R_GPIO_PMC_32_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_32_PMC0_Pos (0UL) +#define R_GPIO_PMC_32_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_32_PMC1_Pos (1UL) +#define R_GPIO_PMC_32_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_32_PMC2_Pos (2UL) +#define R_GPIO_PMC_32_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_32_PMC3_Pos (3UL) +#define R_GPIO_PMC_33_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_33_PMC0_Pos (0UL) +#define R_GPIO_PMC_33_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_33_PMC1_Pos (1UL) +#define R_GPIO_PMC_33_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_33_PMC2_Pos (2UL) +#define R_GPIO_PMC_33_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_33_PMC3_Pos (3UL) +#define R_GPIO_PMC_33_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_33_PMC4_Pos (4UL) +#define R_GPIO_PMC_33_PMC5_Msk (0x20UL) +#define R_GPIO_PMC_33_PMC5_Pos (5UL) +#define R_GPIO_PMC_34_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_34_PMC0_Pos (0UL) +#define R_GPIO_PMC_34_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_34_PMC1_Pos (1UL) +#define R_GPIO_PMC_34_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_34_PMC2_Pos (2UL) +#define R_GPIO_PMC_34_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_34_PMC3_Pos (3UL) +#define R_GPIO_PMC_34_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_34_PMC4_Pos (4UL) +#define R_GPIO_PMC_35_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_35_PMC0_Pos (0UL) +#define R_GPIO_PMC_35_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_35_PMC1_Pos (1UL) +#define R_GPIO_PMC_35_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_35_PMC2_Pos (2UL) +#define R_GPIO_PMC_35_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_35_PMC3_Pos (3UL) +#define R_GPIO_PMC_35_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_35_PMC4_Pos (4UL) +#define R_GPIO_PMC_36_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_36_PMC0_Pos (0UL) +#define R_GPIO_PMC_36_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_36_PMC1_Pos (1UL) +#define R_GPIO_PMC_36_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_36_PMC2_Pos (2UL) +#define R_GPIO_PMC_36_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_36_PMC3_Pos (3UL) +#define R_GPIO_PMC_37_PMC0_Msk (0x01UL) +#define R_GPIO_PMC_37_PMC0_Pos (0UL) +#define R_GPIO_PMC_37_PMC1_Msk (0x02UL) +#define R_GPIO_PMC_37_PMC1_Pos (1UL) +#define R_GPIO_PMC_37_PMC2_Msk (0x04UL) +#define R_GPIO_PMC_37_PMC2_Pos (2UL) +#define R_GPIO_PMC_37_PMC3_Msk (0x08UL) +#define R_GPIO_PMC_37_PMC3_Pos (3UL) +#define R_GPIO_PMC_37_PMC4_Msk (0x10UL) +#define R_GPIO_PMC_37_PMC4_Pos (4UL) +#define R_GPIO_PFC_20_PFC20_0_Msk (0x00000007UL) +#define R_GPIO_PFC_20_PFC20_0_Pos (0UL) +#define R_GPIO_PFC_20_PFC20_1_Msk (0x00000070UL) +#define R_GPIO_PFC_20_PFC20_1_Pos (4UL) +#define R_GPIO_PFC_20_PFC20_2_Msk (0x00000700UL) +#define R_GPIO_PFC_20_PFC20_2_Pos (8UL) +#define R_GPIO_PFC_20_PFC20_3_Msk (0x00007000UL) +#define R_GPIO_PFC_20_PFC20_3_Pos (12UL) +#define R_GPIO_PFC_21_PFC21_0_Msk (0x00000007UL) +#define R_GPIO_PFC_21_PFC21_0_Pos (0UL) +#define R_GPIO_PFC_21_PFC21_1_Msk (0x00000070UL) +#define R_GPIO_PFC_21_PFC21_1_Pos (4UL) +#define R_GPIO_PFC_21_PFC21_2_Msk (0x00000700UL) +#define R_GPIO_PFC_21_PFC21_2_Pos (8UL) +#define R_GPIO_PFC_21_PFC21_3_Msk (0x00007000UL) +#define R_GPIO_PFC_21_PFC21_3_Pos (12UL) +#define R_GPIO_PFC_21_PFC21_4_Msk (0x00070000UL) +#define R_GPIO_PFC_21_PFC21_4_Pos (16UL) +#define R_GPIO_PFC_22_PFC22_0_Msk (0x00000007UL) +#define R_GPIO_PFC_22_PFC22_0_Pos (0UL) +#define R_GPIO_PFC_22_PFC22_1_Msk (0x00000070UL) +#define R_GPIO_PFC_22_PFC22_1_Pos (4UL) +#define R_GPIO_PFC_22_PFC22_2_Msk (0x00000700UL) +#define R_GPIO_PFC_22_PFC22_2_Pos (8UL) +#define R_GPIO_PFC_22_PFC22_3_Msk (0x00007000UL) +#define R_GPIO_PFC_22_PFC22_3_Pos (12UL) +#define R_GPIO_PFC_22_PFC22_4_Msk (0x00070000UL) +#define R_GPIO_PFC_22_PFC22_4_Pos (16UL) +#define R_GPIO_PFC_23_PFC23_0_Msk (0x00000007UL) +#define R_GPIO_PFC_23_PFC23_0_Pos (0UL) +#define R_GPIO_PFC_23_PFC23_1_Msk (0x00000070UL) +#define R_GPIO_PFC_23_PFC23_1_Pos (4UL) +#define R_GPIO_PFC_23_PFC23_2_Msk (0x00000700UL) +#define R_GPIO_PFC_23_PFC23_2_Pos (8UL) +#define R_GPIO_PFC_23_PFC23_3_Msk (0x00007000UL) +#define R_GPIO_PFC_23_PFC23_3_Pos (12UL) +#define R_GPIO_PFC_24_PFC24_0_Msk (0x00000007UL) +#define R_GPIO_PFC_24_PFC24_0_Pos (0UL) +#define R_GPIO_PFC_24_PFC24_1_Msk (0x00000070UL) +#define R_GPIO_PFC_24_PFC24_1_Pos (4UL) +#define R_GPIO_PFC_25_PFC25_0_Msk (0x00000007UL) +#define R_GPIO_PFC_25_PFC25_0_Pos (0UL) +#define R_GPIO_PFC_25_PFC25_1_Msk (0x00000070UL) +#define R_GPIO_PFC_25_PFC25_1_Pos (4UL) +#define R_GPIO_PFC_25_PFC25_2_Msk (0x00000700UL) +#define R_GPIO_PFC_25_PFC25_2_Pos (8UL) +#define R_GPIO_PFC_25_PFC25_3_Msk (0x00007000UL) +#define R_GPIO_PFC_25_PFC25_3_Pos (12UL) +#define R_GPIO_PFC_25_PFC25_4_Msk (0x00070000UL) +#define R_GPIO_PFC_25_PFC25_4_Pos (16UL) +#define R_GPIO_PFC_26_PFC26_0_Msk (0x00000007UL) +#define R_GPIO_PFC_26_PFC26_0_Pos (0UL) +#define R_GPIO_PFC_26_PFC26_1_Msk (0x00000070UL) +#define R_GPIO_PFC_26_PFC26_1_Pos (4UL) +#define R_GPIO_PFC_26_PFC26_2_Msk (0x00000700UL) +#define R_GPIO_PFC_26_PFC26_2_Pos (8UL) +#define R_GPIO_PFC_27_PFC27_0_Msk (0x00000007UL) +#define R_GPIO_PFC_27_PFC27_0_Pos (0UL) +#define R_GPIO_PFC_27_PFC27_1_Msk (0x00000070UL) +#define R_GPIO_PFC_27_PFC27_1_Pos (4UL) +#define R_GPIO_PFC_27_PFC27_2_Msk (0x00000700UL) +#define R_GPIO_PFC_27_PFC27_2_Pos (8UL) +#define R_GPIO_PFC_27_PFC27_3_Msk (0x00007000UL) +#define R_GPIO_PFC_27_PFC27_3_Pos (12UL) +#define R_GPIO_PFC_28_PFC28_0_Msk (0x00000007UL) +#define R_GPIO_PFC_28_PFC28_0_Pos (0UL) +#define R_GPIO_PFC_28_PFC28_1_Msk (0x00000070UL) +#define R_GPIO_PFC_28_PFC28_1_Pos (4UL) +#define R_GPIO_PFC_29_PFC29_0_Msk (0x00000007UL) +#define R_GPIO_PFC_29_PFC29_0_Pos (0UL) +#define R_GPIO_PFC_29_PFC29_1_Msk (0x00000070UL) +#define R_GPIO_PFC_29_PFC29_1_Pos (4UL) +#define R_GPIO_PFC_29_PFC29_2_Msk (0x00000700UL) +#define R_GPIO_PFC_29_PFC29_2_Pos (8UL) +#define R_GPIO_PFC_29_PFC29_3_Msk (0x00007000UL) +#define R_GPIO_PFC_29_PFC29_3_Pos (12UL) +#define R_GPIO_PFC_2A_PFC2A_0_Msk (0x00000007UL) +#define R_GPIO_PFC_2A_PFC2A_0_Pos (0UL) +#define R_GPIO_PFC_2A_PFC2A_1_Msk (0x00000070UL) +#define R_GPIO_PFC_2A_PFC2A_1_Pos (4UL) +#define R_GPIO_PFC_2A_PFC2A_2_Msk (0x00000700UL) +#define R_GPIO_PFC_2A_PFC2A_2_Pos (8UL) +#define R_GPIO_PFC_2A_PFC2A_3_Msk (0x00007000UL) +#define R_GPIO_PFC_2A_PFC2A_3_Pos (12UL) +#define R_GPIO_PFC_2A_PFC2A_4_Msk (0x00070000UL) +#define R_GPIO_PFC_2A_PFC2A_4_Pos (16UL) +#define R_GPIO_PFC_2A_PFC2A_5_Msk (0x00700000UL) +#define R_GPIO_PFC_2A_PFC2A_5_Pos (20UL) +#define R_GPIO_PFC_30_PFC30_0_Msk (0x00000007UL) +#define R_GPIO_PFC_30_PFC30_0_Pos (0UL) +#define R_GPIO_PFC_30_PFC30_1_Msk (0x00000070UL) +#define R_GPIO_PFC_30_PFC30_1_Pos (4UL) +#define R_GPIO_PFC_30_PFC30_2_Msk (0x00000700UL) +#define R_GPIO_PFC_30_PFC30_2_Pos (8UL) +#define R_GPIO_PFC_30_PFC30_3_Msk (0x00007000UL) +#define R_GPIO_PFC_30_PFC30_3_Pos (12UL) +#define R_GPIO_PFC_30_PFC30_4_Msk (0x00070000UL) +#define R_GPIO_PFC_30_PFC30_4_Pos (16UL) +#define R_GPIO_PFC_31_PFC31_0_Msk (0x00000007UL) +#define R_GPIO_PFC_31_PFC31_0_Pos (0UL) +#define R_GPIO_PFC_31_PFC31_1_Msk (0x00000070UL) +#define R_GPIO_PFC_31_PFC31_1_Pos (4UL) +#define R_GPIO_PFC_31_PFC31_2_Msk (0x00000700UL) +#define R_GPIO_PFC_31_PFC31_2_Pos (8UL) +#define R_GPIO_PFC_31_PFC31_3_Msk (0x00007000UL) +#define R_GPIO_PFC_31_PFC31_3_Pos (12UL) +#define R_GPIO_PFC_32_PFC32_0_Msk (0x00000007UL) +#define R_GPIO_PFC_32_PFC32_0_Pos (0UL) +#define R_GPIO_PFC_32_PFC32_1_Msk (0x00000070UL) +#define R_GPIO_PFC_32_PFC32_1_Pos (4UL) +#define R_GPIO_PFC_32_PFC32_2_Msk (0x00000700UL) +#define R_GPIO_PFC_32_PFC32_2_Pos (8UL) +#define R_GPIO_PFC_32_PFC32_3_Msk (0x00007000UL) +#define R_GPIO_PFC_32_PFC32_3_Pos (12UL) +#define R_GPIO_PFC_33_PFC33_0_Msk (0x00000007UL) +#define R_GPIO_PFC_33_PFC33_0_Pos (0UL) +#define R_GPIO_PFC_33_PFC33_1_Msk (0x00000070UL) +#define R_GPIO_PFC_33_PFC33_1_Pos (4UL) +#define R_GPIO_PFC_33_PFC33_2_Msk (0x00000700UL) +#define R_GPIO_PFC_33_PFC33_2_Pos (8UL) +#define R_GPIO_PFC_33_PFC33_3_Msk (0x00007000UL) +#define R_GPIO_PFC_33_PFC33_3_Pos (12UL) +#define R_GPIO_PFC_33_PFC33_4_Msk (0x00070000UL) +#define R_GPIO_PFC_33_PFC33_4_Pos (16UL) +#define R_GPIO_PFC_33_PFC33_5_Msk (0x00700000UL) +#define R_GPIO_PFC_33_PFC33_5_Pos (20UL) +#define R_GPIO_PFC_34_PFC34_0_Msk (0x00000007UL) +#define R_GPIO_PFC_34_PFC34_0_Pos (0UL) +#define R_GPIO_PFC_34_PFC34_1_Msk (0x00000070UL) +#define R_GPIO_PFC_34_PFC34_1_Pos (4UL) +#define R_GPIO_PFC_34_PFC34_2_Msk (0x00000700UL) +#define R_GPIO_PFC_34_PFC34_2_Pos (8UL) +#define R_GPIO_PFC_34_PFC34_3_Msk (0x00007000UL) +#define R_GPIO_PFC_34_PFC34_3_Pos (12UL) +#define R_GPIO_PFC_34_PFC34_4_Msk (0x00070000UL) +#define R_GPIO_PFC_34_PFC34_4_Pos (16UL) +#define R_GPIO_PFC_35_PFC35_0_Msk (0x00000007UL) +#define R_GPIO_PFC_35_PFC35_0_Pos (0UL) +#define R_GPIO_PFC_35_PFC35_1_Msk (0x00000070UL) +#define R_GPIO_PFC_35_PFC35_1_Pos (4UL) +#define R_GPIO_PFC_35_PFC35_2_Msk (0x00000700UL) +#define R_GPIO_PFC_35_PFC35_2_Pos (8UL) +#define R_GPIO_PFC_35_PFC35_3_Msk (0x00007000UL) +#define R_GPIO_PFC_35_PFC35_3_Pos (12UL) +#define R_GPIO_PFC_35_PFC35_4_Msk (0x00070000UL) +#define R_GPIO_PFC_35_PFC35_4_Pos (16UL) +#define R_GPIO_PFC_36_PFC36_0_Msk (0x00000007UL) +#define R_GPIO_PFC_36_PFC36_0_Pos (0UL) +#define R_GPIO_PFC_36_PFC36_1_Msk (0x00000070UL) +#define R_GPIO_PFC_36_PFC36_1_Pos (4UL) +#define R_GPIO_PFC_36_PFC36_2_Msk (0x00000700UL) +#define R_GPIO_PFC_36_PFC36_2_Pos (8UL) +#define R_GPIO_PFC_36_PFC36_3_Msk (0x00007000UL) +#define R_GPIO_PFC_36_PFC36_3_Pos (12UL) +#define R_GPIO_PFC_37_PFC37_0_Msk (0x00000007UL) +#define R_GPIO_PFC_37_PFC37_0_Pos (0UL) +#define R_GPIO_PFC_37_PFC37_1_Msk (0x00000070UL) +#define R_GPIO_PFC_37_PFC37_1_Pos (4UL) +#define R_GPIO_PFC_37_PFC37_2_Msk (0x00000700UL) +#define R_GPIO_PFC_37_PFC37_2_Pos (8UL) +#define R_GPIO_PFC_37_PFC37_3_Msk (0x00007000UL) +#define R_GPIO_PFC_37_PFC37_3_Pos (12UL) +#define R_GPIO_PFC_37_PFC37_4_Msk (0x00070000UL) +#define R_GPIO_PFC_37_PFC37_4_Pos (16UL) +#define R_GPIO_PIN_20_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_20_PIN0_Pos (0UL) +#define R_GPIO_PIN_20_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_20_PIN1_Pos (1UL) +#define R_GPIO_PIN_20_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_20_PIN2_Pos (2UL) +#define R_GPIO_PIN_20_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_20_PIN3_Pos (3UL) +#define R_GPIO_PIN_21_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_21_PIN0_Pos (0UL) +#define R_GPIO_PIN_21_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_21_PIN1_Pos (1UL) +#define R_GPIO_PIN_21_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_21_PIN2_Pos (2UL) +#define R_GPIO_PIN_21_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_21_PIN3_Pos (3UL) +#define R_GPIO_PIN_21_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_21_PIN4_Pos (4UL) +#define R_GPIO_PIN_22_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_22_PIN0_Pos (0UL) +#define R_GPIO_PIN_22_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_22_PIN1_Pos (1UL) +#define R_GPIO_PIN_22_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_22_PIN2_Pos (2UL) +#define R_GPIO_PIN_22_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_22_PIN3_Pos (3UL) +#define R_GPIO_PIN_22_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_22_PIN4_Pos (4UL) +#define R_GPIO_PIN_23_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_23_PIN0_Pos (0UL) +#define R_GPIO_PIN_23_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_23_PIN1_Pos (1UL) +#define R_GPIO_PIN_23_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_23_PIN2_Pos (2UL) +#define R_GPIO_PIN_23_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_23_PIN3_Pos (3UL) +#define R_GPIO_PIN_24_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_24_PIN0_Pos (0UL) +#define R_GPIO_PIN_24_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_24_PIN1_Pos (1UL) +#define R_GPIO_PIN_25_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_25_PIN0_Pos (0UL) +#define R_GPIO_PIN_25_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_25_PIN1_Pos (1UL) +#define R_GPIO_PIN_25_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_25_PIN2_Pos (2UL) +#define R_GPIO_PIN_25_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_25_PIN3_Pos (3UL) +#define R_GPIO_PIN_25_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_25_PIN4_Pos (4UL) +#define R_GPIO_PIN_26_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_26_PIN0_Pos (0UL) +#define R_GPIO_PIN_26_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_26_PIN1_Pos (1UL) +#define R_GPIO_PIN_26_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_26_PIN2_Pos (2UL) +#define R_GPIO_PIN_27_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_27_PIN0_Pos (0UL) +#define R_GPIO_PIN_27_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_27_PIN1_Pos (1UL) +#define R_GPIO_PIN_27_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_27_PIN2_Pos (2UL) +#define R_GPIO_PIN_27_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_27_PIN3_Pos (3UL) +#define R_GPIO_PIN_28_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_28_PIN0_Pos (0UL) +#define R_GPIO_PIN_28_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_28_PIN1_Pos (1UL) +#define R_GPIO_PIN_29_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_29_PIN0_Pos (0UL) +#define R_GPIO_PIN_29_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_29_PIN1_Pos (1UL) +#define R_GPIO_PIN_29_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_29_PIN2_Pos (2UL) +#define R_GPIO_PIN_29_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_29_PIN3_Pos (3UL) +#define R_GPIO_PIN_2A_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_2A_PIN0_Pos (0UL) +#define R_GPIO_PIN_2A_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_2A_PIN1_Pos (1UL) +#define R_GPIO_PIN_2A_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_2A_PIN2_Pos (2UL) +#define R_GPIO_PIN_2A_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_2A_PIN3_Pos (3UL) +#define R_GPIO_PIN_2A_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_2A_PIN4_Pos (4UL) +#define R_GPIO_PIN_2A_PIN5_Msk (0x20UL) +#define R_GPIO_PIN_2A_PIN5_Pos (5UL) +#define R_GPIO_PIN_30_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_30_PIN0_Pos (0UL) +#define R_GPIO_PIN_30_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_30_PIN1_Pos (1UL) +#define R_GPIO_PIN_30_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_30_PIN2_Pos (2UL) +#define R_GPIO_PIN_30_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_30_PIN3_Pos (3UL) +#define R_GPIO_PIN_30_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_30_PIN4_Pos (4UL) +#define R_GPIO_PIN_31_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_31_PIN0_Pos (0UL) +#define R_GPIO_PIN_31_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_31_PIN1_Pos (1UL) +#define R_GPIO_PIN_31_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_31_PIN2_Pos (2UL) +#define R_GPIO_PIN_31_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_31_PIN3_Pos (3UL) +#define R_GPIO_PIN_32_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_32_PIN0_Pos (0UL) +#define R_GPIO_PIN_32_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_32_PIN1_Pos (1UL) +#define R_GPIO_PIN_32_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_32_PIN2_Pos (2UL) +#define R_GPIO_PIN_32_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_32_PIN3_Pos (3UL) +#define R_GPIO_PIN_33_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_33_PIN0_Pos (0UL) +#define R_GPIO_PIN_33_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_33_PIN1_Pos (1UL) +#define R_GPIO_PIN_33_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_33_PIN2_Pos (2UL) +#define R_GPIO_PIN_33_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_33_PIN3_Pos (3UL) +#define R_GPIO_PIN_33_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_33_PIN4_Pos (4UL) +#define R_GPIO_PIN_33_PIN5_Msk (0x20UL) +#define R_GPIO_PIN_33_PIN5_Pos (5UL) +#define R_GPIO_PIN_34_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_34_PIN0_Pos (0UL) +#define R_GPIO_PIN_34_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_34_PIN1_Pos (1UL) +#define R_GPIO_PIN_34_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_34_PIN2_Pos (2UL) +#define R_GPIO_PIN_34_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_34_PIN3_Pos (3UL) +#define R_GPIO_PIN_34_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_34_PIN4_Pos (4UL) +#define R_GPIO_PIN_35_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_35_PIN0_Pos (0UL) +#define R_GPIO_PIN_35_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_35_PIN1_Pos (1UL) +#define R_GPIO_PIN_35_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_35_PIN2_Pos (2UL) +#define R_GPIO_PIN_35_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_35_PIN3_Pos (3UL) +#define R_GPIO_PIN_35_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_35_PIN4_Pos (4UL) +#define R_GPIO_PIN_36_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_36_PIN0_Pos (0UL) +#define R_GPIO_PIN_36_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_36_PIN1_Pos (1UL) +#define R_GPIO_PIN_36_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_36_PIN2_Pos (2UL) +#define R_GPIO_PIN_36_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_36_PIN3_Pos (3UL) +#define R_GPIO_PIN_37_PIN0_Msk (0x01UL) +#define R_GPIO_PIN_37_PIN0_Pos (0UL) +#define R_GPIO_PIN_37_PIN1_Msk (0x02UL) +#define R_GPIO_PIN_37_PIN1_Pos (1UL) +#define R_GPIO_PIN_37_PIN2_Msk (0x04UL) +#define R_GPIO_PIN_37_PIN2_Pos (2UL) +#define R_GPIO_PIN_37_PIN3_Msk (0x08UL) +#define R_GPIO_PIN_37_PIN3_Pos (3UL) +#define R_GPIO_PIN_37_PIN4_Msk (0x10UL) +#define R_GPIO_PIN_37_PIN4_Pos (4UL) +#define R_GPIO_IOLH_01_TMS_SWDIO_Msk (0x00000003UL) +#define R_GPIO_IOLH_01_TMS_SWDIO_Pos (0UL) +#define R_GPIO_IOLH_01_TDO_Msk (0x00000300UL) +#define R_GPIO_IOLH_01_TDO_Pos (8UL) +#define R_GPIO_IOLH_04_L_XSPI_SPCLK_Msk (0x00000003UL) +#define R_GPIO_IOLH_04_L_XSPI_SPCLK_Pos (0UL) +#define R_GPIO_IOLH_04_L_XSPI_RESET_N_Msk (0x00000300UL) +#define R_GPIO_IOLH_04_L_XSPI_RESET_N_Pos (8UL) +#define R_GPIO_IOLH_04_L_XSPI_WP_N_Msk (0x00030000UL) +#define R_GPIO_IOLH_04_L_XSPI_WP_N_Pos (16UL) +#define R_GPIO_IOLH_04_L_XSPI_DS_Msk (0x03000000UL) +#define R_GPIO_IOLH_04_L_XSPI_DS_Pos (24UL) +#define R_GPIO_IOLH_04_H_XSPI_CS0_N_Msk (0x00000003UL) +#define R_GPIO_IOLH_04_H_XSPI_CS0_N_Pos (0UL) +#define R_GPIO_IOLH_04_H_XSPI_CS1_N_Msk (0x00000300UL) +#define R_GPIO_IOLH_04_H_XSPI_CS1_N_Pos (8UL) +#define R_GPIO_IOLH_05_L_XSPI_IO0_Msk (0x00000003UL) +#define R_GPIO_IOLH_05_L_XSPI_IO0_Pos (0UL) +#define R_GPIO_IOLH_05_L_XSPI_IO1_Msk (0x00000300UL) +#define R_GPIO_IOLH_05_L_XSPI_IO1_Pos (8UL) +#define R_GPIO_IOLH_05_L_XSPI_IO2_Msk (0x00030000UL) +#define R_GPIO_IOLH_05_L_XSPI_IO2_Pos (16UL) +#define R_GPIO_IOLH_05_L_XSPI_IO3_Msk (0x03000000UL) +#define R_GPIO_IOLH_05_L_XSPI_IO3_Pos (24UL) +#define R_GPIO_IOLH_05_H_XSPI_IO4_Msk (0x00000003UL) +#define R_GPIO_IOLH_05_H_XSPI_IO4_Pos (0UL) +#define R_GPIO_IOLH_05_H_XSPI_IO5_Msk (0x00000300UL) +#define R_GPIO_IOLH_05_H_XSPI_IO5_Pos (8UL) +#define R_GPIO_IOLH_05_H_XSPI_IO6_Msk (0x00030000UL) +#define R_GPIO_IOLH_05_H_XSPI_IO6_Pos (16UL) +#define R_GPIO_IOLH_05_H_XSPI_IO7_Msk (0x03000000UL) +#define R_GPIO_IOLH_05_H_XSPI_IO7_Pos (24UL) +#define R_GPIO_IOLH_06_WDTOVF_PERROUT_Msk (0x00000003UL) +#define R_GPIO_IOLH_06_WDTOVF_PERROUT_Pos (0UL) +#define R_GPIO_IOLH_10_SD0_CLK_Msk (0x00000003UL) +#define R_GPIO_IOLH_10_SD0_CLK_Pos (0UL) +#define R_GPIO_IOLH_10_SD0_CMD_Msk (0x00000300UL) +#define R_GPIO_IOLH_10_SD0_CMD_Pos (8UL) +#define R_GPIO_IOLH_10_SD0_RST_N_Msk (0x00030000UL) +#define R_GPIO_IOLH_10_SD0_RST_N_Pos (16UL) +#define R_GPIO_IOLH_11_L_SD0_DATA0_Msk (0x00000003UL) +#define R_GPIO_IOLH_11_L_SD0_DATA0_Pos (0UL) +#define R_GPIO_IOLH_11_L_SD0_DATA1_Msk (0x00000300UL) +#define R_GPIO_IOLH_11_L_SD0_DATA1_Pos (8UL) +#define R_GPIO_IOLH_11_L_SD0_DATA2_Msk (0x00030000UL) +#define R_GPIO_IOLH_11_L_SD0_DATA2_Pos (16UL) +#define R_GPIO_IOLH_11_L_SD0_DATA3_Msk (0x03000000UL) +#define R_GPIO_IOLH_11_L_SD0_DATA3_Pos (24UL) +#define R_GPIO_IOLH_11_H_SD0_DATA4_Msk (0x00000003UL) +#define R_GPIO_IOLH_11_H_SD0_DATA4_Pos (0UL) +#define R_GPIO_IOLH_11_H_SD0_DATA5_Msk (0x00000300UL) +#define R_GPIO_IOLH_11_H_SD0_DATA5_Pos (8UL) +#define R_GPIO_IOLH_11_H_SD0_DATA6_Msk (0x00030000UL) +#define R_GPIO_IOLH_11_H_SD0_DATA6_Pos (16UL) +#define R_GPIO_IOLH_11_H_SD0_DATA7_Msk (0x03000000UL) +#define R_GPIO_IOLH_11_H_SD0_DATA7_Pos (24UL) +#define R_GPIO_IOLH_12_SD1_CLK_Msk (0x00000003UL) +#define R_GPIO_IOLH_12_SD1_CLK_Pos (0UL) +#define R_GPIO_IOLH_12_SD1_CMD_Msk (0x00000300UL) +#define R_GPIO_IOLH_12_SD1_CMD_Pos (8UL) +#define R_GPIO_IOLH_13_SD1_DATA0_Msk (0x00000003UL) +#define R_GPIO_IOLH_13_SD1_DATA0_Pos (0UL) +#define R_GPIO_IOLH_13_SD1_DATA1_Msk (0x00000300UL) +#define R_GPIO_IOLH_13_SD1_DATA1_Pos (8UL) +#define R_GPIO_IOLH_13_SD1_DATA2_Msk (0x00030000UL) +#define R_GPIO_IOLH_13_SD1_DATA2_Pos (16UL) +#define R_GPIO_IOLH_13_SD1_DATA3_Msk (0x03000000UL) +#define R_GPIO_IOLH_13_SD1_DATA3_Pos (24UL) +#define R_GPIO_IOLH_20_IOLH20_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_20_IOLH20_0_Pos (0UL) +#define R_GPIO_IOLH_20_IOLH20_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_20_IOLH20_1_Pos (8UL) +#define R_GPIO_IOLH_20_IOLH20_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_20_IOLH20_2_Pos (16UL) +#define R_GPIO_IOLH_20_IOLH20_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_20_IOLH20_3_Pos (24UL) +#define R_GPIO_IOLH_21_L_IOLH21_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_21_L_IOLH21_L_0_Pos (0UL) +#define R_GPIO_IOLH_21_L_IOLH21_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_21_L_IOLH21_L_1_Pos (8UL) +#define R_GPIO_IOLH_21_L_IOLH21_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_21_L_IOLH21_L_2_Pos (16UL) +#define R_GPIO_IOLH_21_L_IOLH21_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_21_L_IOLH21_L_3_Pos (24UL) +#define R_GPIO_IOLH_21_H_IOLH21_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_21_H_IOLH21_H_0_Pos (0UL) +#define R_GPIO_IOLH_22_L_IOLH22_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_22_L_IOLH22_L_0_Pos (0UL) +#define R_GPIO_IOLH_22_L_IOLH22_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_22_L_IOLH22_L_1_Pos (8UL) +#define R_GPIO_IOLH_22_L_IOLH22_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_22_L_IOLH22_L_2_Pos (16UL) +#define R_GPIO_IOLH_22_L_IOLH22_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_22_L_IOLH22_L_3_Pos (24UL) +#define R_GPIO_IOLH_22_H_IOLH22_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_22_H_IOLH22_H_0_Pos (0UL) +#define R_GPIO_IOLH_23_IOLH23_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_23_IOLH23_0_Pos (0UL) +#define R_GPIO_IOLH_23_IOLH23_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_23_IOLH23_1_Pos (8UL) +#define R_GPIO_IOLH_23_IOLH23_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_23_IOLH23_2_Pos (16UL) +#define R_GPIO_IOLH_23_IOLH23_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_23_IOLH23_3_Pos (24UL) +#define R_GPIO_IOLH_24_IOLH24_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_24_IOLH24_0_Pos (0UL) +#define R_GPIO_IOLH_24_IOLH24_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_24_IOLH24_1_Pos (8UL) +#define R_GPIO_IOLH_25_L_IOLH25_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_25_L_IOLH25_L_0_Pos (0UL) +#define R_GPIO_IOLH_25_L_IOLH25_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_25_L_IOLH25_L_1_Pos (8UL) +#define R_GPIO_IOLH_25_L_IOLH25_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_25_L_IOLH25_L_2_Pos (16UL) +#define R_GPIO_IOLH_25_L_IOLH25_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_25_L_IOLH25_L_3_Pos (24UL) +#define R_GPIO_IOLH_25_H_IOLH25_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_25_H_IOLH25_H_0_Pos (0UL) +#define R_GPIO_IOLH_26_IOLH26_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_26_IOLH26_0_Pos (0UL) +#define R_GPIO_IOLH_26_IOLH26_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_26_IOLH26_1_Pos (8UL) +#define R_GPIO_IOLH_26_IOLH26_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_26_IOLH26_2_Pos (16UL) +#define R_GPIO_IOLH_27_IOLH27_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_27_IOLH27_0_Pos (0UL) +#define R_GPIO_IOLH_27_IOLH27_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_27_IOLH27_1_Pos (8UL) +#define R_GPIO_IOLH_27_IOLH27_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_27_IOLH27_2_Pos (16UL) +#define R_GPIO_IOLH_27_IOLH27_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_27_IOLH27_3_Pos (24UL) +#define R_GPIO_IOLH_28_IOLH28_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_28_IOLH28_0_Pos (0UL) +#define R_GPIO_IOLH_28_IOLH28_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_28_IOLH28_1_Pos (8UL) +#define R_GPIO_IOLH_29_IOLH29_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_29_IOLH29_0_Pos (0UL) +#define R_GPIO_IOLH_29_IOLH29_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_29_IOLH29_1_Pos (8UL) +#define R_GPIO_IOLH_29_IOLH29_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_29_IOLH29_2_Pos (16UL) +#define R_GPIO_IOLH_29_IOLH29_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_29_IOLH29_3_Pos (24UL) +#define R_GPIO_IOLH_2A_L_IOLH2A_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_2A_L_IOLH2A_L_0_Pos (0UL) +#define R_GPIO_IOLH_2A_L_IOLH2A_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_2A_L_IOLH2A_L_1_Pos (8UL) +#define R_GPIO_IOLH_2A_L_IOLH2A_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_2A_L_IOLH2A_L_2_Pos (16UL) +#define R_GPIO_IOLH_2A_L_IOLH2A_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_2A_L_IOLH2A_L_3_Pos (24UL) +#define R_GPIO_IOLH_2A_H_IOLH2A_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_2A_H_IOLH2A_H_0_Pos (0UL) +#define R_GPIO_IOLH_2A_H_IOLH2A_H_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_2A_H_IOLH2A_H_1_Pos (8UL) +#define R_GPIO_IOLH_30_L_IOLH30_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_30_L_IOLH30_L_0_Pos (0UL) +#define R_GPIO_IOLH_30_L_IOLH30_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_30_L_IOLH30_L_1_Pos (8UL) +#define R_GPIO_IOLH_30_L_IOLH30_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_30_L_IOLH30_L_2_Pos (16UL) +#define R_GPIO_IOLH_30_L_IOLH30_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_30_L_IOLH30_L_3_Pos (24UL) +#define R_GPIO_IOLH_30_H_IOLH30_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_30_H_IOLH30_H_0_Pos (0UL) +#define R_GPIO_IOLH_31_IOLH31_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_31_IOLH31_0_Pos (0UL) +#define R_GPIO_IOLH_31_IOLH31_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_31_IOLH31_1_Pos (8UL) +#define R_GPIO_IOLH_31_IOLH31_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_31_IOLH31_2_Pos (16UL) +#define R_GPIO_IOLH_31_IOLH31_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_31_IOLH31_3_Pos (24UL) +#define R_GPIO_IOLH_32_IOLH32_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_32_IOLH32_0_Pos (0UL) +#define R_GPIO_IOLH_32_IOLH32_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_32_IOLH32_1_Pos (8UL) +#define R_GPIO_IOLH_32_IOLH32_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_32_IOLH32_2_Pos (16UL) +#define R_GPIO_IOLH_32_IOLH32_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_32_IOLH32_3_Pos (24UL) +#define R_GPIO_IOLH_33_L_IOLH33_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_33_L_IOLH33_L_0_Pos (0UL) +#define R_GPIO_IOLH_33_L_IOLH33_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_33_L_IOLH33_L_1_Pos (8UL) +#define R_GPIO_IOLH_33_L_IOLH33_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_33_L_IOLH33_L_2_Pos (16UL) +#define R_GPIO_IOLH_33_L_IOLH33_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_33_L_IOLH33_L_3_Pos (24UL) +#define R_GPIO_IOLH_33_H_IOLH33_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_33_H_IOLH33_H_0_Pos (0UL) +#define R_GPIO_IOLH_33_H_IOLH33_H_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_33_H_IOLH33_H_1_Pos (8UL) +#define R_GPIO_IOLH_34_L_IOLH34_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_34_L_IOLH34_L_0_Pos (0UL) +#define R_GPIO_IOLH_34_L_IOLH34_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_34_L_IOLH34_L_1_Pos (8UL) +#define R_GPIO_IOLH_34_L_IOLH34_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_34_L_IOLH34_L_2_Pos (16UL) +#define R_GPIO_IOLH_34_L_IOLH34_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_34_L_IOLH34_L_3_Pos (24UL) +#define R_GPIO_IOLH_34_H_IOLH34_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_34_H_IOLH34_H_0_Pos (0UL) +#define R_GPIO_IOLH_35_L_IOLH35_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_35_L_IOLH35_L_0_Pos (0UL) +#define R_GPIO_IOLH_35_L_IOLH35_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_35_L_IOLH35_L_1_Pos (8UL) +#define R_GPIO_IOLH_35_L_IOLH35_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_35_L_IOLH35_L_2_Pos (16UL) +#define R_GPIO_IOLH_35_L_IOLH35_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_35_L_IOLH35_L_3_Pos (24UL) +#define R_GPIO_IOLH_35_H_IOLH35_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_35_H_IOLH35_H_0_Pos (0UL) +#define R_GPIO_IOLH_36_IOLH36_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_36_IOLH36_0_Pos (0UL) +#define R_GPIO_IOLH_36_IOLH36_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_36_IOLH36_1_Pos (8UL) +#define R_GPIO_IOLH_36_IOLH36_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_36_IOLH36_2_Pos (16UL) +#define R_GPIO_IOLH_36_IOLH36_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_36_IOLH36_3_Pos (24UL) +#define R_GPIO_IOLH_37_L_IOLH37_L_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_37_L_IOLH37_L_0_Pos (0UL) +#define R_GPIO_IOLH_37_L_IOLH37_L_1_Msk (0x00000300UL) +#define R_GPIO_IOLH_37_L_IOLH37_L_1_Pos (8UL) +#define R_GPIO_IOLH_37_L_IOLH37_L_2_Msk (0x00030000UL) +#define R_GPIO_IOLH_37_L_IOLH37_L_2_Pos (16UL) +#define R_GPIO_IOLH_37_L_IOLH37_L_3_Msk (0x03000000UL) +#define R_GPIO_IOLH_37_L_IOLH37_L_3_Pos (24UL) +#define R_GPIO_IOLH_37_H_IOLH37_H_0_Msk (0x00000003UL) +#define R_GPIO_IOLH_37_H_IOLH37_H_0_Pos (0UL) +#define R_GPIO_IEN_01_TMS_SWDIO_Msk (0x00000001UL) +#define R_GPIO_IEN_01_TMS_SWDIO_Pos (0UL) +#define R_GPIO_IEN_02_AUDIO_CLK1_Msk (0x00000001UL) +#define R_GPIO_IEN_02_AUDIO_CLK1_Pos (0UL) +#define R_GPIO_IEN_02_AUDIO_CLK2_Msk (0x00000100UL) +#define R_GPIO_IEN_02_AUDIO_CLK2_Pos (8UL) +#define R_GPIO_IEN_09_I3C_SDA_Msk (0x00000001UL) +#define R_GPIO_IEN_09_I3C_SDA_Pos (0UL) +#define R_GPIO_IEN_09_I3C_SCL_Msk (0x00000100UL) +#define R_GPIO_IEN_09_I3C_SCL_Pos (8UL) +#define R_GPIO_IEN_10_SD0_CMD_Msk (0x00000100UL) +#define R_GPIO_IEN_10_SD0_CMD_Pos (8UL) +#define R_GPIO_IEN_11_L_SD0_DATA0_Msk (0x00000001UL) +#define R_GPIO_IEN_11_L_SD0_DATA0_Pos (0UL) +#define R_GPIO_IEN_11_L_SD0_DATA1_Msk (0x00000100UL) +#define R_GPIO_IEN_11_L_SD0_DATA1_Pos (8UL) +#define R_GPIO_IEN_11_L_SD0_DATA2_Msk (0x00010000UL) +#define R_GPIO_IEN_11_L_SD0_DATA2_Pos (16UL) +#define R_GPIO_IEN_11_L_SD0_DATA3_Msk (0x01000000UL) +#define R_GPIO_IEN_11_L_SD0_DATA3_Pos (24UL) +#define R_GPIO_IEN_11_H_SD0_DATA4_Msk (0x00000001UL) +#define R_GPIO_IEN_11_H_SD0_DATA4_Pos (0UL) +#define R_GPIO_IEN_11_H_SD0_DATA5_Msk (0x00000100UL) +#define R_GPIO_IEN_11_H_SD0_DATA5_Pos (8UL) +#define R_GPIO_IEN_11_H_SD0_DATA6_Msk (0x00010000UL) +#define R_GPIO_IEN_11_H_SD0_DATA6_Pos (16UL) +#define R_GPIO_IEN_11_H_SD0_DATA7_Msk (0x01000000UL) +#define R_GPIO_IEN_11_H_SD0_DATA7_Pos (24UL) +#define R_GPIO_IEN_12_SD1_CMD_Msk (0x00000100UL) +#define R_GPIO_IEN_12_SD1_CMD_Pos (8UL) +#define R_GPIO_IEN_13_SD1_DATA0_Msk (0x00000001UL) +#define R_GPIO_IEN_13_SD1_DATA0_Pos (0UL) +#define R_GPIO_IEN_13_SD1_DATA1_Msk (0x00000100UL) +#define R_GPIO_IEN_13_SD1_DATA1_Pos (8UL) +#define R_GPIO_IEN_13_SD1_DATA2_Msk (0x00010000UL) +#define R_GPIO_IEN_13_SD1_DATA2_Pos (16UL) +#define R_GPIO_IEN_13_SD1_DATA3_Msk (0x01000000UL) +#define R_GPIO_IEN_13_SD1_DATA3_Pos (24UL) +#define R_GPIO_IEN_23_P11_1_Msk (0x00000100UL) +#define R_GPIO_IEN_23_P11_1_Pos (8UL) +#define R_GPIO_IEN_23_P11_2_Msk (0x00010000UL) +#define R_GPIO_IEN_23_P11_2_Pos (16UL) +#define R_GPIO_IEN_23_P11_3_Msk (0x01000000UL) +#define R_GPIO_IEN_23_P11_3_Pos (24UL) +#define R_GPIO_IEN_24_P12_0_Msk (0x00000001UL) +#define R_GPIO_IEN_24_P12_0_Pos (0UL) +#define R_GPIO_IEN_24_P12_1_Msk (0x00000100UL) +#define R_GPIO_IEN_24_P12_1_Pos (8UL) +#define R_GPIO_IEN_30_P1_0_Msk (0x00000001UL) +#define R_GPIO_IEN_30_P1_0_Pos (0UL) +#define R_GPIO_IEN_34_P7_0_Msk (0x00000001UL) +#define R_GPIO_IEN_34_P7_0_Pos (0UL) +#define R_GPIO_PUPD_20_PUPD20_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_20_PUPD20_0_Pos (0UL) +#define R_GPIO_PUPD_20_PUPD20_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_20_PUPD20_1_Pos (8UL) +#define R_GPIO_PUPD_20_PUPD20_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_20_PUPD20_2_Pos (16UL) +#define R_GPIO_PUPD_20_PUPD20_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_20_PUPD20_3_Pos (24UL) +#define R_GPIO_PUPD_21_L_PUPD21_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_21_L_PUPD21_L_0_Pos (0UL) +#define R_GPIO_PUPD_21_L_PUPD21_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_21_L_PUPD21_L_1_Pos (8UL) +#define R_GPIO_PUPD_21_L_PUPD21_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_21_L_PUPD21_L_2_Pos (16UL) +#define R_GPIO_PUPD_21_L_PUPD21_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_21_L_PUPD21_L_3_Pos (24UL) +#define R_GPIO_PUPD_21_H_PUPD21_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_21_H_PUPD21_H_0_Pos (0UL) +#define R_GPIO_PUPD_22_L_PUPD22_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_22_L_PUPD22_L_0_Pos (0UL) +#define R_GPIO_PUPD_22_L_PUPD22_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_22_L_PUPD22_L_1_Pos (8UL) +#define R_GPIO_PUPD_22_L_PUPD22_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_22_L_PUPD22_L_2_Pos (16UL) +#define R_GPIO_PUPD_22_L_PUPD22_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_22_L_PUPD22_L_3_Pos (24UL) +#define R_GPIO_PUPD_22_H_PUPD22_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_22_H_PUPD22_H_0_Pos (0UL) +#define R_GPIO_PUPD_23_PUPD23_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_23_PUPD23_0_Pos (0UL) +#define R_GPIO_PUPD_23_PUPD23_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_23_PUPD23_1_Pos (8UL) +#define R_GPIO_PUPD_23_PUPD23_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_23_PUPD23_2_Pos (16UL) +#define R_GPIO_PUPD_23_PUPD23_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_23_PUPD23_3_Pos (24UL) +#define R_GPIO_PUPD_24_PUPD24_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_24_PUPD24_0_Pos (0UL) +#define R_GPIO_PUPD_24_PUPD24_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_24_PUPD24_1_Pos (8UL) +#define R_GPIO_PUPD_25_L_PUPD25_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_25_L_PUPD25_L_0_Pos (0UL) +#define R_GPIO_PUPD_25_L_PUPD25_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_25_L_PUPD25_L_1_Pos (8UL) +#define R_GPIO_PUPD_25_L_PUPD25_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_25_L_PUPD25_L_2_Pos (16UL) +#define R_GPIO_PUPD_25_L_PUPD25_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_25_L_PUPD25_L_3_Pos (24UL) +#define R_GPIO_PUPD_25_H_PUPD25_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_25_H_PUPD25_H_0_Pos (0UL) +#define R_GPIO_PUPD_26_PUPD26_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_26_PUPD26_0_Pos (0UL) +#define R_GPIO_PUPD_26_PUPD26_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_26_PUPD26_1_Pos (8UL) +#define R_GPIO_PUPD_26_PUPD26_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_26_PUPD26_2_Pos (16UL) +#define R_GPIO_PUPD_27_PUPD27_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_27_PUPD27_0_Pos (0UL) +#define R_GPIO_PUPD_27_PUPD27_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_27_PUPD27_1_Pos (8UL) +#define R_GPIO_PUPD_27_PUPD27_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_27_PUPD27_2_Pos (16UL) +#define R_GPIO_PUPD_27_PUPD27_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_27_PUPD27_3_Pos (24UL) +#define R_GPIO_PUPD_28_PUPD28_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_28_PUPD28_0_Pos (0UL) +#define R_GPIO_PUPD_28_PUPD28_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_28_PUPD28_1_Pos (8UL) +#define R_GPIO_PUPD_29_PUPD29_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_29_PUPD29_0_Pos (0UL) +#define R_GPIO_PUPD_29_PUPD29_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_29_PUPD29_1_Pos (8UL) +#define R_GPIO_PUPD_29_PUPD29_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_29_PUPD29_2_Pos (16UL) +#define R_GPIO_PUPD_29_PUPD29_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_29_PUPD29_3_Pos (24UL) +#define R_GPIO_PUPD_2A_L_PUPD2A_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_2A_L_PUPD2A_L_0_Pos (0UL) +#define R_GPIO_PUPD_2A_L_PUPD2A_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_2A_L_PUPD2A_L_1_Pos (8UL) +#define R_GPIO_PUPD_2A_L_PUPD2A_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_2A_L_PUPD2A_L_2_Pos (16UL) +#define R_GPIO_PUPD_2A_L_PUPD2A_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_2A_L_PUPD2A_L_3_Pos (24UL) +#define R_GPIO_PUPD_2A_H_PUPD2A_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_2A_H_PUPD2A_H_0_Pos (0UL) +#define R_GPIO_PUPD_2A_H_PUPD2A_H_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_2A_H_PUPD2A_H_1_Pos (8UL) +#define R_GPIO_PUPD_30_L_PUPD30_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_30_L_PUPD30_L_0_Pos (0UL) +#define R_GPIO_PUPD_30_L_PUPD30_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_30_L_PUPD30_L_1_Pos (8UL) +#define R_GPIO_PUPD_30_L_PUPD30_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_30_L_PUPD30_L_2_Pos (16UL) +#define R_GPIO_PUPD_30_L_PUPD30_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_30_L_PUPD30_L_3_Pos (24UL) +#define R_GPIO_PUPD_30_H_PUPD30_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_30_H_PUPD30_H_0_Pos (0UL) +#define R_GPIO_PUPD_31_PUPD31_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_31_PUPD31_0_Pos (0UL) +#define R_GPIO_PUPD_31_PUPD31_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_31_PUPD31_1_Pos (8UL) +#define R_GPIO_PUPD_31_PUPD31_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_31_PUPD31_2_Pos (16UL) +#define R_GPIO_PUPD_31_PUPD31_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_31_PUPD31_3_Pos (24UL) +#define R_GPIO_PUPD_32_PUPD32_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_32_PUPD32_0_Pos (0UL) +#define R_GPIO_PUPD_32_PUPD32_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_32_PUPD32_1_Pos (8UL) +#define R_GPIO_PUPD_32_PUPD32_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_32_PUPD32_2_Pos (16UL) +#define R_GPIO_PUPD_32_PUPD32_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_32_PUPD32_3_Pos (24UL) +#define R_GPIO_PUPD_33_L_PUPD33_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_33_L_PUPD33_L_0_Pos (0UL) +#define R_GPIO_PUPD_33_L_PUPD33_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_33_L_PUPD33_L_1_Pos (8UL) +#define R_GPIO_PUPD_33_L_PUPD33_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_33_L_PUPD33_L_2_Pos (16UL) +#define R_GPIO_PUPD_33_L_PUPD33_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_33_L_PUPD33_L_3_Pos (24UL) +#define R_GPIO_PUPD_33_H_PUPD33_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_33_H_PUPD33_H_0_Pos (0UL) +#define R_GPIO_PUPD_33_H_PUPD33_H_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_33_H_PUPD33_H_1_Pos (8UL) +#define R_GPIO_PUPD_34_L_PUPD34_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_34_L_PUPD34_L_0_Pos (0UL) +#define R_GPIO_PUPD_34_L_PUPD34_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_34_L_PUPD34_L_1_Pos (8UL) +#define R_GPIO_PUPD_34_L_PUPD34_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_34_L_PUPD34_L_2_Pos (16UL) +#define R_GPIO_PUPD_34_L_PUPD34_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_34_L_PUPD34_L_3_Pos (24UL) +#define R_GPIO_PUPD_34_H_PUPD34_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_34_H_PUPD34_H_0_Pos (0UL) +#define R_GPIO_PUPD_35_L_PUPD35_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_35_L_PUPD35_L_0_Pos (0UL) +#define R_GPIO_PUPD_35_L_PUPD35_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_35_L_PUPD35_L_1_Pos (8UL) +#define R_GPIO_PUPD_35_L_PUPD35_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_35_L_PUPD35_L_2_Pos (16UL) +#define R_GPIO_PUPD_35_L_PUPD35_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_35_L_PUPD35_L_3_Pos (24UL) +#define R_GPIO_PUPD_35_H_PUPD35_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_35_H_PUPD35_H_0_Pos (0UL) +#define R_GPIO_PUPD_36_PUPD36_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_36_PUPD36_0_Pos (0UL) +#define R_GPIO_PUPD_36_PUPD36_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_36_PUPD36_1_Pos (8UL) +#define R_GPIO_PUPD_36_PUPD36_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_36_PUPD36_2_Pos (16UL) +#define R_GPIO_PUPD_36_PUPD36_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_36_PUPD36_3_Pos (24UL) +#define R_GPIO_PUPD_37_L_PUPD37_L_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_37_L_PUPD37_L_0_Pos (0UL) +#define R_GPIO_PUPD_37_L_PUPD37_L_1_Msk (0x00000300UL) +#define R_GPIO_PUPD_37_L_PUPD37_L_1_Pos (8UL) +#define R_GPIO_PUPD_37_L_PUPD37_L_2_Msk (0x00030000UL) +#define R_GPIO_PUPD_37_L_PUPD37_L_2_Pos (16UL) +#define R_GPIO_PUPD_37_L_PUPD37_L_3_Msk (0x03000000UL) +#define R_GPIO_PUPD_37_L_PUPD37_L_3_Pos (24UL) +#define R_GPIO_PUPD_37_H_PUPD37_H_0_Msk (0x00000003UL) +#define R_GPIO_PUPD_37_H_PUPD37_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_00_FILONOFF00_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_00_FILONOFF00_0_Pos (0UL) +#define R_GPIO_FILONOFF_20_FILONOFF20_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_20_FILONOFF20_0_Pos (0UL) +#define R_GPIO_FILONOFF_20_FILONOFF20_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_20_FILONOFF20_1_Pos (8UL) +#define R_GPIO_FILONOFF_20_FILONOFF20_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_20_FILONOFF20_2_Pos (16UL) +#define R_GPIO_FILONOFF_20_FILONOFF20_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_20_FILONOFF20_3_Pos (24UL) +#define R_GPIO_FILONOFF_21_L_FILONOFF21_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_21_L_FILONOFF21_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_21_L_FILONOFF21_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_21_L_FILONOFF21_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_21_L_FILONOFF21_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_21_L_FILONOFF21_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_21_L_FILONOFF21_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_21_L_FILONOFF21_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_21_H_FILONOFF21_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_21_H_FILONOFF21_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_22_L_FILONOFF22_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_22_L_FILONOFF22_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_22_L_FILONOFF22_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_22_L_FILONOFF22_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_22_L_FILONOFF22_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_22_L_FILONOFF22_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_22_L_FILONOFF22_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_22_L_FILONOFF22_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_22_H_FILONOFF22_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_22_H_FILONOFF22_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_23_FILONOFF23_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_23_FILONOFF23_0_Pos (0UL) +#define R_GPIO_FILONOFF_23_FILONOFF23_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_23_FILONOFF23_1_Pos (8UL) +#define R_GPIO_FILONOFF_23_FILONOFF23_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_23_FILONOFF23_2_Pos (16UL) +#define R_GPIO_FILONOFF_23_FILONOFF23_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_23_FILONOFF23_3_Pos (24UL) +#define R_GPIO_FILONOFF_24_FILONOFF24_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_24_FILONOFF24_0_Pos (0UL) +#define R_GPIO_FILONOFF_24_FILONOFF24_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_24_FILONOFF24_1_Pos (8UL) +#define R_GPIO_FILONOFF_25_L_FILONOFF25_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_25_L_FILONOFF25_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_25_L_FILONOFF25_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_25_L_FILONOFF25_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_25_L_FILONOFF25_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_25_L_FILONOFF25_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_25_L_FILONOFF25_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_25_L_FILONOFF25_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_25_H_FILONOFF25_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_25_H_FILONOFF25_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_26_FILONOFF26_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_26_FILONOFF26_0_Pos (0UL) +#define R_GPIO_FILONOFF_26_FILONOFF26_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_26_FILONOFF26_1_Pos (8UL) +#define R_GPIO_FILONOFF_26_FILONOFF26_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_26_FILONOFF26_2_Pos (16UL) +#define R_GPIO_FILONOFF_27_FILONOFF27_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_27_FILONOFF27_0_Pos (0UL) +#define R_GPIO_FILONOFF_27_FILONOFF27_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_27_FILONOFF27_1_Pos (8UL) +#define R_GPIO_FILONOFF_27_FILONOFF27_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_27_FILONOFF27_2_Pos (16UL) +#define R_GPIO_FILONOFF_27_FILONOFF27_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_27_FILONOFF27_3_Pos (24UL) +#define R_GPIO_FILONOFF_28_FILONOFF28_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_28_FILONOFF28_0_Pos (0UL) +#define R_GPIO_FILONOFF_28_FILONOFF28_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_28_FILONOFF28_1_Pos (8UL) +#define R_GPIO_FILONOFF_29_FILONOFF29_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_29_FILONOFF29_0_Pos (0UL) +#define R_GPIO_FILONOFF_29_FILONOFF29_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_29_FILONOFF29_1_Pos (8UL) +#define R_GPIO_FILONOFF_29_FILONOFF29_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_29_FILONOFF29_2_Pos (16UL) +#define R_GPIO_FILONOFF_29_FILONOFF29_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_29_FILONOFF29_3_Pos (24UL) +#define R_GPIO_FILONOFF_2A_L_FILONOFF2A_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_2A_L_FILONOFF2A_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_2A_L_FILONOFF2A_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_2A_L_FILONOFF2A_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_2A_L_FILONOFF2A_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_2A_L_FILONOFF2A_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_2A_L_FILONOFF2A_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_2A_L_FILONOFF2A_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_2A_H_FILONOFF2A_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_2A_H_FILONOFF2A_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_2A_H_FILONOFF2A_H_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_2A_H_FILONOFF2A_H_1_Pos (8UL) +#define R_GPIO_FILONOFF_30_L_FILONOFF30_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_30_L_FILONOFF30_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_30_L_FILONOFF30_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_30_L_FILONOFF30_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_30_L_FILONOFF30_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_30_L_FILONOFF30_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_30_L_FILONOFF30_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_30_L_FILONOFF30_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_30_H_FILONOFF30_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_30_H_FILONOFF30_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_31_FILONOFF31_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_31_FILONOFF31_0_Pos (0UL) +#define R_GPIO_FILONOFF_31_FILONOFF31_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_31_FILONOFF31_1_Pos (8UL) +#define R_GPIO_FILONOFF_31_FILONOFF31_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_31_FILONOFF31_2_Pos (16UL) +#define R_GPIO_FILONOFF_31_FILONOFF31_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_31_FILONOFF31_3_Pos (24UL) +#define R_GPIO_FILONOFF_32_FILONOFF32_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_32_FILONOFF32_0_Pos (0UL) +#define R_GPIO_FILONOFF_32_FILONOFF32_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_32_FILONOFF32_1_Pos (8UL) +#define R_GPIO_FILONOFF_32_FILONOFF32_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_32_FILONOFF32_2_Pos (16UL) +#define R_GPIO_FILONOFF_32_FILONOFF32_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_32_FILONOFF32_3_Pos (24UL) +#define R_GPIO_FILONOFF_33_L_FILONOFF33_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_33_L_FILONOFF33_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_33_L_FILONOFF33_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_33_L_FILONOFF33_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_33_L_FILONOFF33_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_33_L_FILONOFF33_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_33_L_FILONOFF33_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_33_L_FILONOFF33_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_33_H_FILONOFF33_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_33_H_FILONOFF33_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_33_H_FILONOFF33_H_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_33_H_FILONOFF33_H_1_Pos (8UL) +#define R_GPIO_FILONOFF_34_L_FILONOFF34_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_34_L_FILONOFF34_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_34_L_FILONOFF34_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_34_L_FILONOFF34_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_34_L_FILONOFF34_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_34_L_FILONOFF34_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_34_L_FILONOFF34_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_34_L_FILONOFF34_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_34_H_FILONOFF34_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_34_H_FILONOFF34_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_35_L_FILONOFF35_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_35_L_FILONOFF35_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_35_L_FILONOFF35_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_35_L_FILONOFF35_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_35_L_FILONOFF35_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_35_L_FILONOFF35_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_35_L_FILONOFF35_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_35_L_FILONOFF35_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_35_H_FILONOFF35_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_35_H_FILONOFF35_H_0_Pos (0UL) +#define R_GPIO_FILONOFF_36_FILONOFF36_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_36_FILONOFF36_0_Pos (0UL) +#define R_GPIO_FILONOFF_36_FILONOFF36_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_36_FILONOFF36_1_Pos (8UL) +#define R_GPIO_FILONOFF_36_FILONOFF36_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_36_FILONOFF36_2_Pos (16UL) +#define R_GPIO_FILONOFF_36_FILONOFF36_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_36_FILONOFF36_3_Pos (24UL) +#define R_GPIO_FILONOFF_37_L_FILONOFF37_L_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_37_L_FILONOFF37_L_0_Pos (0UL) +#define R_GPIO_FILONOFF_37_L_FILONOFF37_L_1_Msk (0x00000100UL) +#define R_GPIO_FILONOFF_37_L_FILONOFF37_L_1_Pos (8UL) +#define R_GPIO_FILONOFF_37_L_FILONOFF37_L_2_Msk (0x00010000UL) +#define R_GPIO_FILONOFF_37_L_FILONOFF37_L_2_Pos (16UL) +#define R_GPIO_FILONOFF_37_L_FILONOFF37_L_3_Msk (0x01000000UL) +#define R_GPIO_FILONOFF_37_L_FILONOFF37_L_3_Pos (24UL) +#define R_GPIO_FILONOFF_37_H_FILONOFF37_H_0_Msk (0x00000001UL) +#define R_GPIO_FILONOFF_37_H_FILONOFF37_H_0_Pos (0UL) +#define R_GPIO_FILNUM_00_FILNUM00_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_00_FILNUM00_0_Pos (0UL) +#define R_GPIO_FILNUM_20_FILNUM20_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_20_FILNUM20_0_Pos (0UL) +#define R_GPIO_FILNUM_20_FILNUM20_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_20_FILNUM20_1_Pos (8UL) +#define R_GPIO_FILNUM_20_FILNUM20_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_20_FILNUM20_2_Pos (16UL) +#define R_GPIO_FILNUM_20_FILNUM20_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_20_FILNUM20_3_Pos (24UL) +#define R_GPIO_FILNUM_21_L_FILNUM21_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_21_L_FILNUM21_L_0_Pos (0UL) +#define R_GPIO_FILNUM_21_L_FILNUM21_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_21_L_FILNUM21_L_1_Pos (8UL) +#define R_GPIO_FILNUM_21_L_FILNUM21_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_21_L_FILNUM21_L_2_Pos (16UL) +#define R_GPIO_FILNUM_21_L_FILNUM21_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_21_L_FILNUM21_L_3_Pos (24UL) +#define R_GPIO_FILNUM_21_H_FILNUM21_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_21_H_FILNUM21_H_0_Pos (0UL) +#define R_GPIO_FILNUM_22_L_FILNUM22_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_22_L_FILNUM22_L_0_Pos (0UL) +#define R_GPIO_FILNUM_22_L_FILNUM22_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_22_L_FILNUM22_L_1_Pos (8UL) +#define R_GPIO_FILNUM_22_L_FILNUM22_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_22_L_FILNUM22_L_2_Pos (16UL) +#define R_GPIO_FILNUM_22_L_FILNUM22_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_22_L_FILNUM22_L_3_Pos (24UL) +#define R_GPIO_FILNUM_22_H_FILNUM22_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_22_H_FILNUM22_H_0_Pos (0UL) +#define R_GPIO_FILNUM_23_FILNUM23_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_23_FILNUM23_0_Pos (0UL) +#define R_GPIO_FILNUM_23_FILNUM23_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_23_FILNUM23_1_Pos (8UL) +#define R_GPIO_FILNUM_23_FILNUM23_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_23_FILNUM23_2_Pos (16UL) +#define R_GPIO_FILNUM_23_FILNUM23_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_23_FILNUM23_3_Pos (24UL) +#define R_GPIO_FILNUM_24_FILNUM24_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_24_FILNUM24_0_Pos (0UL) +#define R_GPIO_FILNUM_24_FILNUM24_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_24_FILNUM24_1_Pos (8UL) +#define R_GPIO_FILNUM_25_L_FILNUM25_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_25_L_FILNUM25_L_0_Pos (0UL) +#define R_GPIO_FILNUM_25_L_FILNUM25_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_25_L_FILNUM25_L_1_Pos (8UL) +#define R_GPIO_FILNUM_25_L_FILNUM25_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_25_L_FILNUM25_L_2_Pos (16UL) +#define R_GPIO_FILNUM_25_L_FILNUM25_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_25_L_FILNUM25_L_3_Pos (24UL) +#define R_GPIO_FILNUM_25_H_FILNUM25_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_25_H_FILNUM25_H_0_Pos (0UL) +#define R_GPIO_FILNUM_26_FILNUM26_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_26_FILNUM26_0_Pos (0UL) +#define R_GPIO_FILNUM_26_FILNUM26_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_26_FILNUM26_1_Pos (8UL) +#define R_GPIO_FILNUM_26_FILNUM26_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_26_FILNUM26_2_Pos (16UL) +#define R_GPIO_FILNUM_27_FILNUM27_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_27_FILNUM27_0_Pos (0UL) +#define R_GPIO_FILNUM_27_FILNUM27_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_27_FILNUM27_1_Pos (8UL) +#define R_GPIO_FILNUM_27_FILNUM27_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_27_FILNUM27_2_Pos (16UL) +#define R_GPIO_FILNUM_27_FILNUM27_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_27_FILNUM27_3_Pos (24UL) +#define R_GPIO_FILNUM_28_FILNUM28_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_28_FILNUM28_0_Pos (0UL) +#define R_GPIO_FILNUM_28_FILNUM28_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_28_FILNUM28_1_Pos (8UL) +#define R_GPIO_FILNUM_29_FILNUM29_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_29_FILNUM29_0_Pos (0UL) +#define R_GPIO_FILNUM_29_FILNUM29_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_29_FILNUM29_1_Pos (8UL) +#define R_GPIO_FILNUM_29_FILNUM29_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_29_FILNUM29_2_Pos (16UL) +#define R_GPIO_FILNUM_29_FILNUM29_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_29_FILNUM29_3_Pos (24UL) +#define R_GPIO_FILNUM_2A_L_FILNUM2A_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_2A_L_FILNUM2A_L_0_Pos (0UL) +#define R_GPIO_FILNUM_2A_L_FILNUM2A_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_2A_L_FILNUM2A_L_1_Pos (8UL) +#define R_GPIO_FILNUM_2A_L_FILNUM2A_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_2A_L_FILNUM2A_L_2_Pos (16UL) +#define R_GPIO_FILNUM_2A_L_FILNUM2A_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_2A_L_FILNUM2A_L_3_Pos (24UL) +#define R_GPIO_FILNUM_2A_H_FILNUM2A_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_2A_H_FILNUM2A_H_0_Pos (0UL) +#define R_GPIO_FILNUM_2A_H_FILNUM2A_H_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_2A_H_FILNUM2A_H_1_Pos (8UL) +#define R_GPIO_FILNUM_30_L_FILNUM30_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_30_L_FILNUM30_L_0_Pos (0UL) +#define R_GPIO_FILNUM_30_L_FILNUM30_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_30_L_FILNUM30_L_1_Pos (8UL) +#define R_GPIO_FILNUM_30_L_FILNUM30_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_30_L_FILNUM30_L_2_Pos (16UL) +#define R_GPIO_FILNUM_30_L_FILNUM30_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_30_L_FILNUM30_L_3_Pos (24UL) +#define R_GPIO_FILNUM_30_H_FILNUM30_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_30_H_FILNUM30_H_0_Pos (0UL) +#define R_GPIO_FILNUM_31_FILNUM31_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_31_FILNUM31_0_Pos (0UL) +#define R_GPIO_FILNUM_31_FILNUM31_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_31_FILNUM31_1_Pos (8UL) +#define R_GPIO_FILNUM_31_FILNUM31_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_31_FILNUM31_2_Pos (16UL) +#define R_GPIO_FILNUM_31_FILNUM31_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_31_FILNUM31_3_Pos (24UL) +#define R_GPIO_FILNUM_32_FILNUM32_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_32_FILNUM32_0_Pos (0UL) +#define R_GPIO_FILNUM_32_FILNUM32_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_32_FILNUM32_1_Pos (8UL) +#define R_GPIO_FILNUM_32_FILNUM32_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_32_FILNUM32_2_Pos (16UL) +#define R_GPIO_FILNUM_32_FILNUM32_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_32_FILNUM32_3_Pos (24UL) +#define R_GPIO_FILNUM_33_L_FILNUM33_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_33_L_FILNUM33_L_0_Pos (0UL) +#define R_GPIO_FILNUM_33_L_FILNUM33_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_33_L_FILNUM33_L_1_Pos (8UL) +#define R_GPIO_FILNUM_33_L_FILNUM33_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_33_L_FILNUM33_L_2_Pos (16UL) +#define R_GPIO_FILNUM_33_L_FILNUM33_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_33_L_FILNUM33_L_3_Pos (24UL) +#define R_GPIO_FILNUM_33_H_FILNUM33_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_33_H_FILNUM33_H_0_Pos (0UL) +#define R_GPIO_FILNUM_33_H_FILNUM33_H_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_33_H_FILNUM33_H_1_Pos (8UL) +#define R_GPIO_FILNUM_34_L_FILNUM34_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_34_L_FILNUM34_L_0_Pos (0UL) +#define R_GPIO_FILNUM_34_L_FILNUM34_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_34_L_FILNUM34_L_1_Pos (8UL) +#define R_GPIO_FILNUM_34_L_FILNUM34_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_34_L_FILNUM34_L_2_Pos (16UL) +#define R_GPIO_FILNUM_34_L_FILNUM34_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_34_L_FILNUM34_L_3_Pos (24UL) +#define R_GPIO_FILNUM_34_H_FILNUM34_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_34_H_FILNUM34_H_0_Pos (0UL) +#define R_GPIO_FILNUM_35_L_FILNUM35_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_35_L_FILNUM35_L_0_Pos (0UL) +#define R_GPIO_FILNUM_35_L_FILNUM35_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_35_L_FILNUM35_L_1_Pos (8UL) +#define R_GPIO_FILNUM_35_L_FILNUM35_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_35_L_FILNUM35_L_2_Pos (16UL) +#define R_GPIO_FILNUM_35_L_FILNUM35_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_35_L_FILNUM35_L_3_Pos (24UL) +#define R_GPIO_FILNUM_35_H_FILNUM35_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_35_H_FILNUM35_H_0_Pos (0UL) +#define R_GPIO_FILNUM_36_FILNUM36_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_36_FILNUM36_0_Pos (0UL) +#define R_GPIO_FILNUM_36_FILNUM36_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_36_FILNUM36_1_Pos (8UL) +#define R_GPIO_FILNUM_36_FILNUM36_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_36_FILNUM36_2_Pos (16UL) +#define R_GPIO_FILNUM_36_FILNUM36_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_36_FILNUM36_3_Pos (24UL) +#define R_GPIO_FILNUM_37_L_FILNUM37_L_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_37_L_FILNUM37_L_0_Pos (0UL) +#define R_GPIO_FILNUM_37_L_FILNUM37_L_1_Msk (0x00000300UL) +#define R_GPIO_FILNUM_37_L_FILNUM37_L_1_Pos (8UL) +#define R_GPIO_FILNUM_37_L_FILNUM37_L_2_Msk (0x00030000UL) +#define R_GPIO_FILNUM_37_L_FILNUM37_L_2_Pos (16UL) +#define R_GPIO_FILNUM_37_L_FILNUM37_L_3_Msk (0x03000000UL) +#define R_GPIO_FILNUM_37_L_FILNUM37_L_3_Pos (24UL) +#define R_GPIO_FILNUM_37_H_FILNUM37_H_0_Msk (0x00000003UL) +#define R_GPIO_FILNUM_37_H_FILNUM37_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_00_FILCLKSEL00_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_00_FILCLKSEL00_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_20_FILCLKSEL20_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_20_FILCLKSEL20_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_20_FILCLKSEL20_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_20_FILCLKSEL20_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_20_FILCLKSEL20_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_20_FILCLKSEL20_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_20_FILCLKSEL20_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_20_FILCLKSEL20_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_21_L_FILCLKSEL21_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_21_L_FILCLKSEL21_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_21_L_FILCLKSEL21_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_21_L_FILCLKSEL21_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_21_L_FILCLKSEL21_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_21_L_FILCLKSEL21_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_21_L_FILCLKSEL21_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_21_L_FILCLKSEL21_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_21_H_FILCLKSEL21_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_21_H_FILCLKSEL21_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_22_L_FILCLKSEL22_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_22_L_FILCLKSEL22_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_22_L_FILCLKSEL22_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_22_L_FILCLKSEL22_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_22_L_FILCLKSEL22_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_22_L_FILCLKSEL22_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_22_L_FILCLKSEL22_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_22_L_FILCLKSEL22_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_22_H_FILCLKSEL22_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_22_H_FILCLKSEL22_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_23_FILCLKSEL23_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_23_FILCLKSEL23_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_23_FILCLKSEL23_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_23_FILCLKSEL23_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_23_FILCLKSEL23_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_23_FILCLKSEL23_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_23_FILCLKSEL23_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_23_FILCLKSEL23_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_24_FILCLKSEL24_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_24_FILCLKSEL24_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_24_FILCLKSEL24_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_24_FILCLKSEL24_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_25_L_FILCLKSEL25_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_25_L_FILCLKSEL25_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_25_L_FILCLKSEL25_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_25_L_FILCLKSEL25_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_25_L_FILCLKSEL25_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_25_L_FILCLKSEL25_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_25_L_FILCLKSEL25_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_25_L_FILCLKSEL25_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_25_H_FILCLKSEL25_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_25_H_FILCLKSEL25_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_26_FILCLKSEL26_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_26_FILCLKSEL26_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_26_FILCLKSEL26_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_26_FILCLKSEL26_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_26_FILCLKSEL26_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_26_FILCLKSEL26_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_27_FILCLKSEL27_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_27_FILCLKSEL27_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_27_FILCLKSEL27_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_27_FILCLKSEL27_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_27_FILCLKSEL27_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_27_FILCLKSEL27_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_27_FILCLKSEL27_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_27_FILCLKSEL27_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_28_FILCLKSEL28_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_28_FILCLKSEL28_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_28_FILCLKSEL28_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_28_FILCLKSEL28_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_29_FILCLKSEL29_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_29_FILCLKSEL29_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_29_FILCLKSEL29_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_29_FILCLKSEL29_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_29_FILCLKSEL29_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_29_FILCLKSEL29_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_29_FILCLKSEL29_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_29_FILCLKSEL29_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_2A_L_FILCLKSEL2A_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_2A_L_FILCLKSEL2A_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_2A_L_FILCLKSEL2A_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_2A_L_FILCLKSEL2A_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_2A_L_FILCLKSEL2A_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_2A_L_FILCLKSEL2A_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_2A_L_FILCLKSEL2A_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_2A_L_FILCLKSEL2A_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_2A_H_FILCLKSEL2A_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_2A_H_FILCLKSEL2A_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_2A_H_FILCLKSEL2A_H_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_2A_H_FILCLKSEL2A_H_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_30_L_FILCLKSEL30_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_30_L_FILCLKSEL30_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_30_L_FILCLKSEL30_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_30_L_FILCLKSEL30_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_30_L_FILCLKSEL30_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_30_L_FILCLKSEL30_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_30_L_FILCLKSEL30_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_30_L_FILCLKSEL30_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_30_H_FILCLKSEL30_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_30_H_FILCLKSEL30_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_31_FILCLKSEL31_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_31_FILCLKSEL31_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_31_FILCLKSEL31_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_31_FILCLKSEL31_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_31_FILCLKSEL31_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_31_FILCLKSEL31_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_31_FILCLKSEL31_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_31_FILCLKSEL31_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_32_FILCLKSEL32_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_32_FILCLKSEL32_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_32_FILCLKSEL32_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_32_FILCLKSEL32_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_32_FILCLKSEL32_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_32_FILCLKSEL32_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_32_FILCLKSEL32_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_32_FILCLKSEL32_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_33_L_FILCLKSEL33_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_33_L_FILCLKSEL33_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_33_L_FILCLKSEL33_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_33_L_FILCLKSEL33_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_33_L_FILCLKSEL33_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_33_L_FILCLKSEL33_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_33_L_FILCLKSEL33_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_33_L_FILCLKSEL33_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_33_H_FILCLKSEL33_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_33_H_FILCLKSEL33_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_33_H_FILCLKSEL33_H_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_33_H_FILCLKSEL33_H_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_34_L_FILCLKSEL34_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_34_L_FILCLKSEL34_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_34_L_FILCLKSEL34_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_34_L_FILCLKSEL34_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_34_L_FILCLKSEL34_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_34_L_FILCLKSEL34_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_34_L_FILCLKSEL34_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_34_L_FILCLKSEL34_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_34_H_FILCLKSEL34_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_34_H_FILCLKSEL34_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_35_L_FILCLKSEL35_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_35_L_FILCLKSEL35_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_35_L_FILCLKSEL35_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_35_L_FILCLKSEL35_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_35_L_FILCLKSEL35_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_35_L_FILCLKSEL35_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_35_L_FILCLKSEL35_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_35_L_FILCLKSEL35_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_35_H_FILCLKSEL35_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_35_H_FILCLKSEL35_H_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_36_FILCLKSEL36_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_36_FILCLKSEL36_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_36_FILCLKSEL36_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_36_FILCLKSEL36_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_36_FILCLKSEL36_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_36_FILCLKSEL36_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_36_FILCLKSEL36_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_36_FILCLKSEL36_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_37_L_FILCLKSEL37_L_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_37_L_FILCLKSEL37_L_0_Pos (0UL) +#define R_GPIO_FILCLKSEL_37_L_FILCLKSEL37_L_1_Msk (0x00000300UL) +#define R_GPIO_FILCLKSEL_37_L_FILCLKSEL37_L_1_Pos (8UL) +#define R_GPIO_FILCLKSEL_37_L_FILCLKSEL37_L_2_Msk (0x00030000UL) +#define R_GPIO_FILCLKSEL_37_L_FILCLKSEL37_L_2_Pos (16UL) +#define R_GPIO_FILCLKSEL_37_L_FILCLKSEL37_L_3_Msk (0x03000000UL) +#define R_GPIO_FILCLKSEL_37_L_FILCLKSEL37_L_3_Pos (24UL) +#define R_GPIO_FILCLKSEL_37_H_FILCLKSEL37_H_0_Msk (0x00000003UL) +#define R_GPIO_FILCLKSEL_37_H_FILCLKSEL37_H_0_Pos (0UL) +#define R_GPIO_ISEL_20_ISEL20_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_20_ISEL20_0_Pos (0UL) +#define R_GPIO_ISEL_20_ISEL20_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_20_ISEL20_1_Pos (8UL) +#define R_GPIO_ISEL_20_ISEL20_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_20_ISEL20_2_Pos (16UL) +#define R_GPIO_ISEL_20_ISEL20_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_20_ISEL20_3_Pos (24UL) +#define R_GPIO_ISEL_21_L_ISEL21_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_21_L_ISEL21_L_0_Pos (0UL) +#define R_GPIO_ISEL_21_L_ISEL21_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_21_L_ISEL21_L_1_Pos (8UL) +#define R_GPIO_ISEL_21_L_ISEL21_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_21_L_ISEL21_L_2_Pos (16UL) +#define R_GPIO_ISEL_21_L_ISEL21_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_21_L_ISEL21_L_3_Pos (24UL) +#define R_GPIO_ISEL_21_H_ISEL21_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_21_H_ISEL21_H_0_Pos (0UL) +#define R_GPIO_ISEL_22_L_ISEL22_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_22_L_ISEL22_L_0_Pos (0UL) +#define R_GPIO_ISEL_22_L_ISEL22_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_22_L_ISEL22_L_1_Pos (8UL) +#define R_GPIO_ISEL_22_L_ISEL22_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_22_L_ISEL22_L_2_Pos (16UL) +#define R_GPIO_ISEL_22_L_ISEL22_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_22_L_ISEL22_L_3_Pos (24UL) +#define R_GPIO_ISEL_22_H_ISEL22_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_22_H_ISEL22_H_0_Pos (0UL) +#define R_GPIO_ISEL_23_ISEL23_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_23_ISEL23_0_Pos (0UL) +#define R_GPIO_ISEL_23_ISEL23_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_23_ISEL23_1_Pos (8UL) +#define R_GPIO_ISEL_23_ISEL23_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_23_ISEL23_2_Pos (16UL) +#define R_GPIO_ISEL_23_ISEL23_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_23_ISEL23_3_Pos (24UL) +#define R_GPIO_ISEL_24_ISEL24_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_24_ISEL24_0_Pos (0UL) +#define R_GPIO_ISEL_24_ISEL24_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_24_ISEL24_1_Pos (8UL) +#define R_GPIO_ISEL_25_L_ISEL25_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_25_L_ISEL25_L_0_Pos (0UL) +#define R_GPIO_ISEL_25_L_ISEL25_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_25_L_ISEL25_L_1_Pos (8UL) +#define R_GPIO_ISEL_25_L_ISEL25_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_25_L_ISEL25_L_2_Pos (16UL) +#define R_GPIO_ISEL_25_L_ISEL25_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_25_L_ISEL25_L_3_Pos (24UL) +#define R_GPIO_ISEL_25_H_ISEL25_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_25_H_ISEL25_H_0_Pos (0UL) +#define R_GPIO_ISEL_26_ISEL26_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_26_ISEL26_0_Pos (0UL) +#define R_GPIO_ISEL_26_ISEL26_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_26_ISEL26_1_Pos (8UL) +#define R_GPIO_ISEL_26_ISEL26_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_26_ISEL26_2_Pos (16UL) +#define R_GPIO_ISEL_27_ISEL27_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_27_ISEL27_0_Pos (0UL) +#define R_GPIO_ISEL_27_ISEL27_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_27_ISEL27_1_Pos (8UL) +#define R_GPIO_ISEL_27_ISEL27_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_27_ISEL27_2_Pos (16UL) +#define R_GPIO_ISEL_27_ISEL27_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_27_ISEL27_3_Pos (24UL) +#define R_GPIO_ISEL_28_ISEL28_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_28_ISEL28_0_Pos (0UL) +#define R_GPIO_ISEL_28_ISEL28_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_28_ISEL28_1_Pos (8UL) +#define R_GPIO_ISEL_29_ISEL29_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_29_ISEL29_0_Pos (0UL) +#define R_GPIO_ISEL_29_ISEL29_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_29_ISEL29_1_Pos (8UL) +#define R_GPIO_ISEL_29_ISEL29_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_29_ISEL29_2_Pos (16UL) +#define R_GPIO_ISEL_29_ISEL29_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_29_ISEL29_3_Pos (24UL) +#define R_GPIO_ISEL_2A_L_ISEL2A_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_2A_L_ISEL2A_L_0_Pos (0UL) +#define R_GPIO_ISEL_2A_L_ISEL2A_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_2A_L_ISEL2A_L_1_Pos (8UL) +#define R_GPIO_ISEL_2A_L_ISEL2A_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_2A_L_ISEL2A_L_2_Pos (16UL) +#define R_GPIO_ISEL_2A_L_ISEL2A_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_2A_L_ISEL2A_L_3_Pos (24UL) +#define R_GPIO_ISEL_2A_H_ISEL2A_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_2A_H_ISEL2A_H_0_Pos (0UL) +#define R_GPIO_ISEL_2A_H_ISEL2A_H_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_2A_H_ISEL2A_H_1_Pos (8UL) +#define R_GPIO_ISEL_30_L_ISEL30_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_30_L_ISEL30_L_0_Pos (0UL) +#define R_GPIO_ISEL_30_L_ISEL30_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_30_L_ISEL30_L_1_Pos (8UL) +#define R_GPIO_ISEL_30_L_ISEL30_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_30_L_ISEL30_L_2_Pos (16UL) +#define R_GPIO_ISEL_30_L_ISEL30_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_30_L_ISEL30_L_3_Pos (24UL) +#define R_GPIO_ISEL_30_H_ISEL30_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_30_H_ISEL30_H_0_Pos (0UL) +#define R_GPIO_ISEL_31_ISEL31_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_31_ISEL31_0_Pos (0UL) +#define R_GPIO_ISEL_31_ISEL31_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_31_ISEL31_1_Pos (8UL) +#define R_GPIO_ISEL_31_ISEL31_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_31_ISEL31_2_Pos (16UL) +#define R_GPIO_ISEL_31_ISEL31_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_31_ISEL31_3_Pos (24UL) +#define R_GPIO_ISEL_32_ISEL32_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_32_ISEL32_0_Pos (0UL) +#define R_GPIO_ISEL_32_ISEL32_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_32_ISEL32_1_Pos (8UL) +#define R_GPIO_ISEL_32_ISEL32_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_32_ISEL32_2_Pos (16UL) +#define R_GPIO_ISEL_32_ISEL32_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_32_ISEL32_3_Pos (24UL) +#define R_GPIO_ISEL_33_L_ISEL33_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_33_L_ISEL33_L_0_Pos (0UL) +#define R_GPIO_ISEL_33_L_ISEL33_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_33_L_ISEL33_L_1_Pos (8UL) +#define R_GPIO_ISEL_33_L_ISEL33_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_33_L_ISEL33_L_2_Pos (16UL) +#define R_GPIO_ISEL_33_L_ISEL33_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_33_L_ISEL33_L_3_Pos (24UL) +#define R_GPIO_ISEL_33_H_ISEL33_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_33_H_ISEL33_H_0_Pos (0UL) +#define R_GPIO_ISEL_33_H_ISEL33_H_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_33_H_ISEL33_H_1_Pos (8UL) +#define R_GPIO_ISEL_34_L_ISEL34_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_34_L_ISEL34_L_0_Pos (0UL) +#define R_GPIO_ISEL_34_L_ISEL34_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_34_L_ISEL34_L_1_Pos (8UL) +#define R_GPIO_ISEL_34_L_ISEL34_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_34_L_ISEL34_L_2_Pos (16UL) +#define R_GPIO_ISEL_34_L_ISEL34_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_34_L_ISEL34_L_3_Pos (24UL) +#define R_GPIO_ISEL_34_H_ISEL34_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_34_H_ISEL34_H_0_Pos (0UL) +#define R_GPIO_ISEL_35_L_ISEL35_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_35_L_ISEL35_L_0_Pos (0UL) +#define R_GPIO_ISEL_35_L_ISEL35_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_35_L_ISEL35_L_1_Pos (8UL) +#define R_GPIO_ISEL_35_L_ISEL35_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_35_L_ISEL35_L_2_Pos (16UL) +#define R_GPIO_ISEL_35_L_ISEL35_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_35_L_ISEL35_L_3_Pos (24UL) +#define R_GPIO_ISEL_35_H_ISEL35_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_35_H_ISEL35_H_0_Pos (0UL) +#define R_GPIO_ISEL_36_ISEL36_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_36_ISEL36_0_Pos (0UL) +#define R_GPIO_ISEL_36_ISEL36_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_36_ISEL36_1_Pos (8UL) +#define R_GPIO_ISEL_36_ISEL36_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_36_ISEL36_2_Pos (16UL) +#define R_GPIO_ISEL_36_ISEL36_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_36_ISEL36_3_Pos (24UL) +#define R_GPIO_ISEL_37_L_ISEL37_L_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_37_L_ISEL37_L_0_Pos (0UL) +#define R_GPIO_ISEL_37_L_ISEL37_L_1_Msk (0x00000100UL) +#define R_GPIO_ISEL_37_L_ISEL37_L_1_Pos (8UL) +#define R_GPIO_ISEL_37_L_ISEL37_L_2_Msk (0x00010000UL) +#define R_GPIO_ISEL_37_L_ISEL37_L_2_Pos (16UL) +#define R_GPIO_ISEL_37_L_ISEL37_L_3_Msk (0x01000000UL) +#define R_GPIO_ISEL_37_L_ISEL37_L_3_Pos (24UL) +#define R_GPIO_ISEL_37_H_ISEL37_H_0_Msk (0x00000001UL) +#define R_GPIO_ISEL_37_H_ISEL37_H_0_Pos (0UL) +#define R_GPIO_PWPR_PFCWE_Msk (0x00000040UL) +#define R_GPIO_PWPR_PFCWE_Pos (6UL) +#define R_GPIO_PWPR_BOWI_Msk (0x00000080UL) +#define R_GPIO_PWPR_BOWI_Pos (7UL) +#define R_GPIO_SD_CH0_POC_SD0_POC_Msk (0x00000001UL) +#define R_GPIO_SD_CH0_POC_SD0_POC_Pos (0UL) +#define R_GPIO_SD_CH1_POC_SD1_POC_Msk (0x00000001UL) +#define R_GPIO_SD_CH1_POC_SD1_POC_Pos (0UL) +#define R_GPIO_XSPI_POC_XSPI_POC_Msk (0x00000003UL) +#define R_GPIO_XSPI_POC_XSPI_POC_Pos (0UL) +#define R_GPIO_ETH0_POC_ETH0_POC_Msk (0x00000003UL) +#define R_GPIO_ETH0_POC_ETH0_POC_Pos (0UL) +#define R_GPIO_ETH1_POC_ETH1_POC_Msk (0x00000003UL) +#define R_GPIO_ETH1_POC_ETH1_POC_Pos (0UL) +#define R_GPIO_ETH_MODE_OEN0_Msk (0x00000001UL) +#define R_GPIO_ETH_MODE_OEN0_Pos (0UL) +#define R_GPIO_ETH_MODE_OEN1_Msk (0x00000002UL) +#define R_GPIO_ETH_MODE_OEN1_Pos (1UL) +#define R_GPIO_ETH_MODE_OEN2_Msk (0x00000004UL) +#define R_GPIO_ETH_MODE_OEN2_Pos (2UL) +#define R_GPIO_ETH_MODE_OEN3_Msk (0x00000008UL) +#define R_GPIO_ETH_MODE_OEN3_Pos (3UL) +#define R_GPIO_I3C_SET_STBN_Msk (0x00000001UL) +#define R_GPIO_I3C_SET_STBN_Pos (0UL) +#define R_GPIO_I3C_SET_POC_Msk (0x00000004UL) +#define R_GPIO_I3C_SET_POC_Pos (2UL) +#define R_GPIO_SPI_OCTA_RESET_SORST_N_Msk (0x00000001UL) +#define R_GPIO_SPI_OCTA_RESET_SORST_N_Pos (0UL) + +#endif /* GPIO_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gpt_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gpt_iobitmask.h new file mode 100644 index 00000000..cfe59c97 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gpt_iobitmask.h @@ -0,0 +1,505 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : gpt_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for gpt. + *********************************************************************************************************************/ + +#ifndef GPT_IOBITMASK_H +#define GPT_IOBITMASK_H + +#define R_GPT0_GTWP_WP_Msk (0x00000001UL) +#define R_GPT0_GTWP_WP_Pos (0UL) +#define R_GPT0_GTWP_PRKEY_Msk (0x0000FF00UL) +#define R_GPT0_GTWP_PRKEY_Pos (8UL) +#define R_GPT0_GTSTR_CSTRT0_Msk (0x00000001UL) +#define R_GPT0_GTSTR_CSTRT0_Pos (0UL) +#define R_GPT0_GTSTR_CSTRT1_Msk (0x00000002UL) +#define R_GPT0_GTSTR_CSTRT1_Pos (1UL) +#define R_GPT0_GTSTR_CSTRT2_Msk (0x00000004UL) +#define R_GPT0_GTSTR_CSTRT2_Pos (2UL) +#define R_GPT0_GTSTR_CSTRT3_Msk (0x00000008UL) +#define R_GPT0_GTSTR_CSTRT3_Pos (3UL) +#define R_GPT0_GTSTR_CSTRT4_Msk (0x00000010UL) +#define R_GPT0_GTSTR_CSTRT4_Pos (4UL) +#define R_GPT0_GTSTR_CSTRT5_Msk (0x00000020UL) +#define R_GPT0_GTSTR_CSTRT5_Pos (5UL) +#define R_GPT0_GTSTR_CSTRT6_Msk (0x00000040UL) +#define R_GPT0_GTSTR_CSTRT6_Pos (6UL) +#define R_GPT0_GTSTR_CSTRT7_Msk (0x00000080UL) +#define R_GPT0_GTSTR_CSTRT7_Pos (7UL) +#define R_GPT0_GTSTP_CSTOP0_Msk (0x00000001UL) +#define R_GPT0_GTSTP_CSTOP0_Pos (0UL) +#define R_GPT0_GTSTP_CSTOP1_Msk (0x00000002UL) +#define R_GPT0_GTSTP_CSTOP1_Pos (1UL) +#define R_GPT0_GTSTP_CSTOP2_Msk (0x00000004UL) +#define R_GPT0_GTSTP_CSTOP2_Pos (2UL) +#define R_GPT0_GTSTP_CSTOP3_Msk (0x00000008UL) +#define R_GPT0_GTSTP_CSTOP3_Pos (3UL) +#define R_GPT0_GTSTP_CSTOP4_Msk (0x00000010UL) +#define R_GPT0_GTSTP_CSTOP4_Pos (4UL) +#define R_GPT0_GTSTP_CSTOP5_Msk (0x00000020UL) +#define R_GPT0_GTSTP_CSTOP5_Pos (5UL) +#define R_GPT0_GTSTP_CSTOP6_Msk (0x00000040UL) +#define R_GPT0_GTSTP_CSTOP6_Pos (6UL) +#define R_GPT0_GTSTP_CSTOP7_Msk (0x00000080UL) +#define R_GPT0_GTSTP_CSTOP7_Pos (7UL) +#define R_GPT0_GTCLR_CCLR0_Msk (0x00000001UL) +#define R_GPT0_GTCLR_CCLR0_Pos (0UL) +#define R_GPT0_GTCLR_CCLR1_Msk (0x00000002UL) +#define R_GPT0_GTCLR_CCLR1_Pos (1UL) +#define R_GPT0_GTCLR_CCLR2_Msk (0x00000004UL) +#define R_GPT0_GTCLR_CCLR2_Pos (2UL) +#define R_GPT0_GTCLR_CCLR3_Msk (0x00000008UL) +#define R_GPT0_GTCLR_CCLR3_Pos (3UL) +#define R_GPT0_GTCLR_CCLR4_Msk (0x00000010UL) +#define R_GPT0_GTCLR_CCLR4_Pos (4UL) +#define R_GPT0_GTCLR_CCLR5_Msk (0x00000020UL) +#define R_GPT0_GTCLR_CCLR5_Pos (5UL) +#define R_GPT0_GTCLR_CCLR6_Msk (0x00000040UL) +#define R_GPT0_GTCLR_CCLR6_Pos (6UL) +#define R_GPT0_GTCLR_CCLR7_Msk (0x00000080UL) +#define R_GPT0_GTCLR_CCLR7_Pos (7UL) +#define R_GPT0_GTSSR_SSGTRGAR_Msk (0x00000001UL) +#define R_GPT0_GTSSR_SSGTRGAR_Pos (0UL) +#define R_GPT0_GTSSR_SSGTRGAF_Msk (0x00000002UL) +#define R_GPT0_GTSSR_SSGTRGAF_Pos (1UL) +#define R_GPT0_GTSSR_SSGTRGBR_Msk (0x00000004UL) +#define R_GPT0_GTSSR_SSGTRGBR_Pos (2UL) +#define R_GPT0_GTSSR_SSGTRGBF_Msk (0x00000008UL) +#define R_GPT0_GTSSR_SSGTRGBF_Pos (3UL) +#define R_GPT0_GTSSR_SSGTRGCR_Msk (0x00000010UL) +#define R_GPT0_GTSSR_SSGTRGCR_Pos (4UL) +#define R_GPT0_GTSSR_SSGTRGCF_Msk (0x00000020UL) +#define R_GPT0_GTSSR_SSGTRGCF_Pos (5UL) +#define R_GPT0_GTSSR_SSGTRGDR_Msk (0x00000040UL) +#define R_GPT0_GTSSR_SSGTRGDR_Pos (6UL) +#define R_GPT0_GTSSR_SSGTRGDF_Msk (0x00000080UL) +#define R_GPT0_GTSSR_SSGTRGDF_Pos (7UL) +#define R_GPT0_GTSSR_SSCARBL_Msk (0x00000100UL) +#define R_GPT0_GTSSR_SSCARBL_Pos (8UL) +#define R_GPT0_GTSSR_SSCARBH_Msk (0x00000200UL) +#define R_GPT0_GTSSR_SSCARBH_Pos (9UL) +#define R_GPT0_GTSSR_SSCAFBL_Msk (0x00000400UL) +#define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) +#define R_GPT0_GTSSR_SSCAFBH_Msk (0x00000800UL) +#define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) +#define R_GPT0_GTSSR_SSCBRAL_Msk (0x00001000UL) +#define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) +#define R_GPT0_GTSSR_SSCBRAH_Msk (0x00002000UL) +#define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) +#define R_GPT0_GTSSR_SSCBFAL_Msk (0x00004000UL) +#define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) +#define R_GPT0_GTSSR_SSCBFAH_Msk (0x00008000UL) +#define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) +#define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) +#define R_GPT0_GTSSR_CSTRT_Pos (31UL) +#define R_GPT0_GTPSR_PSGTRGAR_Msk (0x00000001UL) +#define R_GPT0_GTPSR_PSGTRGAR_Pos (0UL) +#define R_GPT0_GTPSR_PSGTRGAF_Msk (0x00000002UL) +#define R_GPT0_GTPSR_PSGTRGAF_Pos (1UL) +#define R_GPT0_GTPSR_PSGTRGBR_Msk (0x00000004UL) +#define R_GPT0_GTPSR_PSGTRGBR_Pos (2UL) +#define R_GPT0_GTPSR_PSGTRGBF_Msk (0x00000008UL) +#define R_GPT0_GTPSR_PSGTRGBF_Pos (3UL) +#define R_GPT0_GTPSR_PSGTRGCR_Msk (0x00000010UL) +#define R_GPT0_GTPSR_PSGTRGCR_Pos (4UL) +#define R_GPT0_GTPSR_PSGTRGCF_Msk (0x00000020UL) +#define R_GPT0_GTPSR_PSGTRGCF_Pos (5UL) +#define R_GPT0_GTPSR_PSGTRGDR_Msk (0x00000040UL) +#define R_GPT0_GTPSR_PSGTRGDR_Pos (6UL) +#define R_GPT0_GTPSR_PSGTRGDF_Msk (0x00000080UL) +#define R_GPT0_GTPSR_PSGTRGDF_Pos (7UL) +#define R_GPT0_GTPSR_PSCARBL_Msk (0x00000100UL) +#define R_GPT0_GTPSR_PSCARBL_Pos (8UL) +#define R_GPT0_GTPSR_PSCARBH_Msk (0x00000200UL) +#define R_GPT0_GTPSR_PSCARBH_Pos (9UL) +#define R_GPT0_GTPSR_PSCAFBL_Msk (0x00000400UL) +#define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) +#define R_GPT0_GTPSR_PSCAFBH_Msk (0x00000800UL) +#define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) +#define R_GPT0_GTPSR_PSCBRAL_Msk (0x00001000UL) +#define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) +#define R_GPT0_GTPSR_PSCBRAH_Msk (0x00002000UL) +#define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) +#define R_GPT0_GTPSR_PSCBFAL_Msk (0x00004000UL) +#define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) +#define R_GPT0_GTPSR_PSCBFAH_Msk (0x00008000UL) +#define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) +#define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) +#define R_GPT0_GTPSR_CSTOP_Pos (31UL) +#define R_GPT0_GTCSR_CSGTRGAR_Msk (0x00000001UL) +#define R_GPT0_GTCSR_CSGTRGAR_Pos (0UL) +#define R_GPT0_GTCSR_CSGTRGAF_Msk (0x00000002UL) +#define R_GPT0_GTCSR_CSGTRGAF_Pos (1UL) +#define R_GPT0_GTCSR_CSGTRGBR_Msk (0x00000004UL) +#define R_GPT0_GTCSR_CSGTRGBR_Pos (2UL) +#define R_GPT0_GTCSR_CSGTRGBF_Msk (0x00000008UL) +#define R_GPT0_GTCSR_CSGTRGBF_Pos (3UL) +#define R_GPT0_GTCSR_CSGTRGCR_Msk (0x00000010UL) +#define R_GPT0_GTCSR_CSGTRGCR_Pos (4UL) +#define R_GPT0_GTCSR_CSGTRGCF_Msk (0x00000020UL) +#define R_GPT0_GTCSR_CSGTRGCF_Pos (5UL) +#define R_GPT0_GTCSR_CSGTRGDR_Msk (0x00000040UL) +#define R_GPT0_GTCSR_CSGTRGDR_Pos (6UL) +#define R_GPT0_GTCSR_CSGTRGDF_Msk (0x00000080UL) +#define R_GPT0_GTCSR_CSGTRGDF_Pos (7UL) +#define R_GPT0_GTCSR_CSCARBL_Msk (0x00000100UL) +#define R_GPT0_GTCSR_CSCARBL_Pos (8UL) +#define R_GPT0_GTCSR_CSCARBH_Msk (0x00000200UL) +#define R_GPT0_GTCSR_CSCARBH_Pos (9UL) +#define R_GPT0_GTCSR_CSCAFBL_Msk (0x00000400UL) +#define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) +#define R_GPT0_GTCSR_CSCAFBH_Msk (0x00000800UL) +#define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) +#define R_GPT0_GTCSR_CSCBRAL_Msk (0x00001000UL) +#define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) +#define R_GPT0_GTCSR_CSCBRAH_Msk (0x00002000UL) +#define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) +#define R_GPT0_GTCSR_CSCBFAL_Msk (0x00004000UL) +#define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) +#define R_GPT0_GTCSR_CSCBFAH_Msk (0x00008000UL) +#define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) +#define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) +#define R_GPT0_GTCSR_CCLR_Pos (31UL) +#define R_GPT0_GTUPSR_USGTRGAR_Msk (0x00000001UL) +#define R_GPT0_GTUPSR_USGTRGAR_Pos (0UL) +#define R_GPT0_GTUPSR_USGTRGAF_Msk (0x00000002UL) +#define R_GPT0_GTUPSR_USGTRGAF_Pos (1UL) +#define R_GPT0_GTUPSR_USGTRGBR_Msk (0x00000004UL) +#define R_GPT0_GTUPSR_USGTRGBR_Pos (2UL) +#define R_GPT0_GTUPSR_USGTRGBF_Msk (0x00000008UL) +#define R_GPT0_GTUPSR_USGTRGBF_Pos (3UL) +#define R_GPT0_GTUPSR_USGTRGCR_Msk (0x00000010UL) +#define R_GPT0_GTUPSR_USGTRGCR_Pos (4UL) +#define R_GPT0_GTUPSR_USGTRGCF_Msk (0x00000020UL) +#define R_GPT0_GTUPSR_USGTRGCF_Pos (5UL) +#define R_GPT0_GTUPSR_USGTRGDR_Msk (0x00000040UL) +#define R_GPT0_GTUPSR_USGTRGDR_Pos (6UL) +#define R_GPT0_GTUPSR_USGTRGDF_Msk (0x00000080UL) +#define R_GPT0_GTUPSR_USGTRGDF_Pos (7UL) +#define R_GPT0_GTUPSR_USCARBL_Msk (0x00000100UL) +#define R_GPT0_GTUPSR_USCARBL_Pos (8UL) +#define R_GPT0_GTUPSR_USCARBH_Msk (0x00000200UL) +#define R_GPT0_GTUPSR_USCARBH_Pos (9UL) +#define R_GPT0_GTUPSR_USCAFBL_Msk (0x00000400UL) +#define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) +#define R_GPT0_GTUPSR_USCAFBH_Msk (0x00000800UL) +#define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) +#define R_GPT0_GTUPSR_USCBRAL_Msk (0x00001000UL) +#define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) +#define R_GPT0_GTUPSR_USCBRAH_Msk (0x00002000UL) +#define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) +#define R_GPT0_GTUPSR_USCBFAL_Msk (0x00004000UL) +#define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) +#define R_GPT0_GTUPSR_USCBFAH_Msk (0x00008000UL) +#define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) +#define R_GPT0_GTDNSR_DSGTRGAR_Msk (0x00000001UL) +#define R_GPT0_GTDNSR_DSGTRGAR_Pos (0UL) +#define R_GPT0_GTDNSR_DSGTRGAF_Msk (0x00000002UL) +#define R_GPT0_GTDNSR_DSGTRGAF_Pos (1UL) +#define R_GPT0_GTDNSR_DSGTRGBR_Msk (0x00000004UL) +#define R_GPT0_GTDNSR_DSGTRGBR_Pos (2UL) +#define R_GPT0_GTDNSR_DSGTRGBF_Msk (0x00000008UL) +#define R_GPT0_GTDNSR_DSGTRGBF_Pos (3UL) +#define R_GPT0_GTDNSR_DSGTRGCR_Msk (0x00000010UL) +#define R_GPT0_GTDNSR_DSGTRGCR_Pos (4UL) +#define R_GPT0_GTDNSR_DSGTRGCF_Msk (0x00000020UL) +#define R_GPT0_GTDNSR_DSGTRGCF_Pos (5UL) +#define R_GPT0_GTDNSR_DSGTRGDR_Msk (0x00000040UL) +#define R_GPT0_GTDNSR_DSGTRGDR_Pos (6UL) +#define R_GPT0_GTDNSR_DSGTRGDF_Msk (0x00000080UL) +#define R_GPT0_GTDNSR_DSGTRGDF_Pos (7UL) +#define R_GPT0_GTDNSR_DSCARBL_Msk (0x00000100UL) +#define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) +#define R_GPT0_GTDNSR_DSCARBH_Msk (0x00000200UL) +#define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) +#define R_GPT0_GTDNSR_DSCAFBL_Msk (0x00000400UL) +#define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) +#define R_GPT0_GTDNSR_DSCAFBH_Msk (0x00000800UL) +#define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) +#define R_GPT0_GTDNSR_DSCBRAL_Msk (0x00001000UL) +#define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) +#define R_GPT0_GTDNSR_DSCBRAH_Msk (0x00002000UL) +#define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) +#define R_GPT0_GTDNSR_DSCBFAL_Msk (0x00004000UL) +#define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) +#define R_GPT0_GTDNSR_DSCBFAH_Msk (0x00008000UL) +#define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) +#define R_GPT0_GTICASR_ASGTRGAR_Msk (0x00000001UL) +#define R_GPT0_GTICASR_ASGTRGAR_Pos (0UL) +#define R_GPT0_GTICASR_ASGTRGAF_Msk (0x00000002UL) +#define R_GPT0_GTICASR_ASGTRGAF_Pos (1UL) +#define R_GPT0_GTICASR_ASGTRGBR_Msk (0x00000004UL) +#define R_GPT0_GTICASR_ASGTRGBR_Pos (2UL) +#define R_GPT0_GTICASR_ASGTRGBF_Msk (0x00000008UL) +#define R_GPT0_GTICASR_ASGTRGBF_Pos (3UL) +#define R_GPT0_GTICASR_ASGTRGCR_Msk (0x00000010UL) +#define R_GPT0_GTICASR_ASGTRGCR_Pos (4UL) +#define R_GPT0_GTICASR_ASGTRGCF_Msk (0x00000020UL) +#define R_GPT0_GTICASR_ASGTRGCF_Pos (5UL) +#define R_GPT0_GTICASR_ASGTRGDR_Msk (0x00000040UL) +#define R_GPT0_GTICASR_ASGTRGDR_Pos (6UL) +#define R_GPT0_GTICASR_ASGTRGDF_Msk (0x00000080UL) +#define R_GPT0_GTICASR_ASGTRGDF_Pos (7UL) +#define R_GPT0_GTICASR_ASCARBL_Msk (0x00000100UL) +#define R_GPT0_GTICASR_ASCARBL_Pos (8UL) +#define R_GPT0_GTICASR_ASCARBH_Msk (0x00000200UL) +#define R_GPT0_GTICASR_ASCARBH_Pos (9UL) +#define R_GPT0_GTICASR_ASCAFBL_Msk (0x00000400UL) +#define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) +#define R_GPT0_GTICASR_ASCAFBH_Msk (0x00000800UL) +#define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) +#define R_GPT0_GTICASR_ASCBRAL_Msk (0x00001000UL) +#define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) +#define R_GPT0_GTICASR_ASCBRAH_Msk (0x00002000UL) +#define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) +#define R_GPT0_GTICASR_ASCBFAL_Msk (0x00004000UL) +#define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) +#define R_GPT0_GTICASR_ASCBFAH_Msk (0x00008000UL) +#define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) +#define R_GPT0_GTICBSR_BSGTRGAR_Msk (0x00000001UL) +#define R_GPT0_GTICBSR_BSGTRGAR_Pos (0UL) +#define R_GPT0_GTICBSR_BSGTRGAF_Msk (0x00000002UL) +#define R_GPT0_GTICBSR_BSGTRGAF_Pos (1UL) +#define R_GPT0_GTICBSR_BSGTRGBR_Msk (0x00000004UL) +#define R_GPT0_GTICBSR_BSGTRGBR_Pos (2UL) +#define R_GPT0_GTICBSR_BSGTRGBF_Msk (0x00000008UL) +#define R_GPT0_GTICBSR_BSGTRGBF_Pos (3UL) +#define R_GPT0_GTICBSR_BSGTRGCR_Msk (0x00000010UL) +#define R_GPT0_GTICBSR_BSGTRGCR_Pos (4UL) +#define R_GPT0_GTICBSR_BSGTRGCF_Msk (0x00000020UL) +#define R_GPT0_GTICBSR_BSGTRGCF_Pos (5UL) +#define R_GPT0_GTICBSR_BSGTRGDR_Msk (0x00000040UL) +#define R_GPT0_GTICBSR_BSGTRGDR_Pos (6UL) +#define R_GPT0_GTICBSR_BSGTRGDF_Msk (0x00000080UL) +#define R_GPT0_GTICBSR_BSGTRGDF_Pos (7UL) +#define R_GPT0_GTICBSR_BSCARBL_Msk (0x00000100UL) +#define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) +#define R_GPT0_GTICBSR_BSCARBH_Msk (0x00000200UL) +#define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) +#define R_GPT0_GTICBSR_BSCAFBL_Msk (0x00000400UL) +#define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) +#define R_GPT0_GTICBSR_BSCAFBH_Msk (0x00000800UL) +#define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) +#define R_GPT0_GTICBSR_BSCBRAL_Msk (0x00001000UL) +#define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) +#define R_GPT0_GTICBSR_BSCBRAH_Msk (0x00002000UL) +#define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) +#define R_GPT0_GTICBSR_BSCBFAL_Msk (0x00004000UL) +#define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) +#define R_GPT0_GTICBSR_BSCBFAH_Msk (0x00008000UL) +#define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) +#define R_GPT0_GTCR_CST_Msk (0x00000001UL) +#define R_GPT0_GTCR_CST_Pos (0UL) +#define R_GPT0_GTCR_MD_Msk (0x00070000UL) +#define R_GPT0_GTCR_MD_Pos (16UL) +#define R_GPT0_GTCR_TPCS_Msk (0x07000000UL) +#define R_GPT0_GTCR_TPCS_Pos (24UL) +#define R_GPT0_GTUDDTYC_UD_Msk (0x00000001UL) +#define R_GPT0_GTUDDTYC_UD_Pos (0UL) +#define R_GPT0_GTUDDTYC_UDF_Msk (0x00000002UL) +#define R_GPT0_GTUDDTYC_UDF_Pos (1UL) +#define R_GPT0_GTUDDTYC_OADTY_Msk (0x00030000UL) +#define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) +#define R_GPT0_GTUDDTYC_OADTYF_Msk (0x00040000UL) +#define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) +#define R_GPT0_GTUDDTYC_OADTYR_Msk (0x00080000UL) +#define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) +#define R_GPT0_GTUDDTYC_OBDTY_Msk (0x03000000UL) +#define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) +#define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x04000000UL) +#define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) +#define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x08000000UL) +#define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) +#define R_GPT0_GTIOR_GTIOA_Msk (0x0000001FUL) +#define R_GPT0_GTIOR_GTIOA_Pos (0UL) +#define R_GPT0_GTIOR_OADFLT_Msk (0x00000040UL) +#define R_GPT0_GTIOR_OADFLT_Pos (6UL) +#define R_GPT0_GTIOR_OAHLD_Msk (0x00000080UL) +#define R_GPT0_GTIOR_OAHLD_Pos (7UL) +#define R_GPT0_GTIOR_OAE_Msk (0x00000100UL) +#define R_GPT0_GTIOR_OAE_Pos (8UL) +#define R_GPT0_GTIOR_OADF_Msk (0x00000600UL) +#define R_GPT0_GTIOR_OADF_Pos (9UL) +#define R_GPT0_GTIOR_NFAEN_Msk (0x00002000UL) +#define R_GPT0_GTIOR_NFAEN_Pos (13UL) +#define R_GPT0_GTIOR_NFCSA_Msk (0x0000C000UL) +#define R_GPT0_GTIOR_NFCSA_Pos (14UL) +#define R_GPT0_GTIOR_GTIOB_Msk (0x001F0000UL) +#define R_GPT0_GTIOR_GTIOB_Pos (16UL) +#define R_GPT0_GTIOR_OBDFLT_Msk (0x00400000UL) +#define R_GPT0_GTIOR_OBDFLT_Pos (22UL) +#define R_GPT0_GTIOR_OBHLD_Msk (0x00800000UL) +#define R_GPT0_GTIOR_OBHLD_Pos (23UL) +#define R_GPT0_GTIOR_OBE_Msk (0x01000000UL) +#define R_GPT0_GTIOR_OBE_Pos (24UL) +#define R_GPT0_GTIOR_OBDF_Msk (0x06000000UL) +#define R_GPT0_GTIOR_OBDF_Pos (25UL) +#define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) +#define R_GPT0_GTIOR_NFBEN_Pos (29UL) +#define R_GPT0_GTIOR_NFCSB_Msk (0xC0000000UL) +#define R_GPT0_GTIOR_NFCSB_Pos (30UL) +#define R_GPT0_GTINTAD_GTINTA_Msk (0x00000001UL) +#define R_GPT0_GTINTAD_GTINTA_Pos (0UL) +#define R_GPT0_GTINTAD_GTINTB_Msk (0x00000002UL) +#define R_GPT0_GTINTAD_GTINTB_Pos (1UL) +#define R_GPT0_GTINTAD_GTINTC_Msk (0x00000004UL) +#define R_GPT0_GTINTAD_GTINTC_Pos (2UL) +#define R_GPT0_GTINTAD_GTINTD_Msk (0x00000008UL) +#define R_GPT0_GTINTAD_GTINTD_Pos (3UL) +#define R_GPT0_GTINTAD_GTINTE_Msk (0x00000010UL) +#define R_GPT0_GTINTAD_GTINTE_Pos (4UL) +#define R_GPT0_GTINTAD_GTINTF_Msk (0x00000020UL) +#define R_GPT0_GTINTAD_GTINTF_Pos (5UL) +#define R_GPT0_GTINTAD_GTINTPR_Msk (0x000000C0UL) +#define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) +#define R_GPT0_GTINTAD_ADTRAUEN_Msk (0x00010000UL) +#define R_GPT0_GTINTAD_ADTRAUEN_Pos (16UL) +#define R_GPT0_GTINTAD_ADTRADEN_Msk (0x00020000UL) +#define R_GPT0_GTINTAD_ADTRADEN_Pos (17UL) +#define R_GPT0_GTINTAD_ADTRBUEN_Msk (0x00040000UL) +#define R_GPT0_GTINTAD_ADTRBUEN_Pos (18UL) +#define R_GPT0_GTINTAD_ADTRBDEN_Msk (0x00080000UL) +#define R_GPT0_GTINTAD_ADTRBDEN_Pos (19UL) +#define R_GPT0_GTINTAD_GRP_Msk (0x03000000UL) +#define R_GPT0_GTINTAD_GRP_Pos (24UL) +#define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) +#define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) +#define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) +#define R_GPT0_GTINTAD_GRPABH_Pos (29UL) +#define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) +#define R_GPT0_GTINTAD_GRPABL_Pos (30UL) +#define R_GPT0_GTST_TCFA_Msk (0x00000001UL) +#define R_GPT0_GTST_TCFA_Pos (0UL) +#define R_GPT0_GTST_TCFB_Msk (0x00000002UL) +#define R_GPT0_GTST_TCFB_Pos (1UL) +#define R_GPT0_GTST_TCFC_Msk (0x00000004UL) +#define R_GPT0_GTST_TCFC_Pos (2UL) +#define R_GPT0_GTST_TCFD_Msk (0x00000008UL) +#define R_GPT0_GTST_TCFD_Pos (3UL) +#define R_GPT0_GTST_TCFE_Msk (0x00000010UL) +#define R_GPT0_GTST_TCFE_Pos (4UL) +#define R_GPT0_GTST_TCFF_Msk (0x00000020UL) +#define R_GPT0_GTST_TCFF_Pos (5UL) +#define R_GPT0_GTST_TCFPO_Msk (0x00000040UL) +#define R_GPT0_GTST_TCFPO_Pos (6UL) +#define R_GPT0_GTST_TCFPU_Msk (0x00000080UL) +#define R_GPT0_GTST_TCFPU_Pos (7UL) +#define R_GPT0_GTST_ITCNT_Msk (0x00000700UL) +#define R_GPT0_GTST_ITCNT_Pos (8UL) +#define R_GPT0_GTST_TUCF_Msk (0x00008000UL) +#define R_GPT0_GTST_TUCF_Pos (15UL) +#define R_GPT0_GTST_ADTRAUF_Msk (0x00010000UL) +#define R_GPT0_GTST_ADTRAUF_Pos (16UL) +#define R_GPT0_GTST_ADTRADF_Msk (0x00020000UL) +#define R_GPT0_GTST_ADTRADF_Pos (17UL) +#define R_GPT0_GTST_ADTRBUF_Msk (0x00040000UL) +#define R_GPT0_GTST_ADTRBUF_Pos (18UL) +#define R_GPT0_GTST_ADTRBDF_Msk (0x00080000UL) +#define R_GPT0_GTST_ADTRBDF_Pos (19UL) +#define R_GPT0_GTST_ODF_Msk (0x01000000UL) +#define R_GPT0_GTST_ODF_Pos (24UL) +#define R_GPT0_GTST_DTEF_Msk (0x10000000UL) +#define R_GPT0_GTST_DTEF_Pos (28UL) +#define R_GPT0_GTST_OABHF_Msk (0x20000000UL) +#define R_GPT0_GTST_OABHF_Pos (29UL) +#define R_GPT0_GTST_OABLF_Msk (0x40000000UL) +#define R_GPT0_GTST_OABLF_Pos (30UL) +#define R_GPT0_GTBER_BD_Msk (0x0000000FUL) +#define R_GPT0_GTBER_BD_Pos (0UL) +#define R_GPT0_GTBER_CCRA_Msk (0x00030000UL) +#define R_GPT0_GTBER_CCRA_Pos (16UL) +#define R_GPT0_GTBER_CCRB_Msk (0x000C0000UL) +#define R_GPT0_GTBER_CCRB_Pos (18UL) +#define R_GPT0_GTBER_PR_Msk (0x00300000UL) +#define R_GPT0_GTBER_PR_Pos (20UL) +#define R_GPT0_GTBER_CCRSWT_Msk (0x00400000UL) +#define R_GPT0_GTBER_CCRSWT_Pos (22UL) +#define R_GPT0_GTBER_ADTTA_Msk (0x03000000UL) +#define R_GPT0_GTBER_ADTTA_Pos (24UL) +#define R_GPT0_GTBER_ADTDA_Msk (0x04000000UL) +#define R_GPT0_GTBER_ADTDA_Pos (26UL) +#define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) +#define R_GPT0_GTBER_ADTTB_Pos (28UL) +#define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) +#define R_GPT0_GTBER_ADTDB_Pos (30UL) +#define R_GPT0_GTITC_ITLA_Msk (0x00000001UL) +#define R_GPT0_GTITC_ITLA_Pos (0UL) +#define R_GPT0_GTITC_ITLB_Msk (0x00000002UL) +#define R_GPT0_GTITC_ITLB_Pos (1UL) +#define R_GPT0_GTITC_ITLC_Msk (0x00000004UL) +#define R_GPT0_GTITC_ITLC_Pos (2UL) +#define R_GPT0_GTITC_ITLD_Msk (0x00000008UL) +#define R_GPT0_GTITC_ITLD_Pos (3UL) +#define R_GPT0_GTITC_ITLE_Msk (0x00000010UL) +#define R_GPT0_GTITC_ITLE_Pos (4UL) +#define R_GPT0_GTITC_ITLF_Msk (0x00000020UL) +#define R_GPT0_GTITC_ITLF_Pos (5UL) +#define R_GPT0_GTITC_IVTC_Msk (0x000000C0UL) +#define R_GPT0_GTITC_IVTC_Pos (6UL) +#define R_GPT0_GTITC_IVTT_Msk (0x00000700UL) +#define R_GPT0_GTITC_IVTT_Pos (8UL) +#define R_GPT0_GTITC_ADTAL_Msk (0x00001000UL) +#define R_GPT0_GTITC_ADTAL_Pos (12UL) +#define R_GPT0_GTITC_ADTBL_Msk (0x00004000UL) +#define R_GPT0_GTITC_ADTBL_Pos (14UL) +#define R_GPT0_GTCNT_GTCNT_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTCNT_GTCNT_Pos (0UL) +#define R_GPT0_GTCCRA_GTCCRA_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTCCRA_GTCCRA_Pos (0UL) +#define R_GPT0_GTCCRB_GTCCRB_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTCCRB_GTCCRB_Pos (0UL) +#define R_GPT0_GTCCRC_GTCCRC_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTCCRC_GTCCRC_Pos (0UL) +#define R_GPT0_GTCCRE_GTCCRE_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTCCRE_GTCCRE_Pos (0UL) +#define R_GPT0_GTCCRD_GTCCRD_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTCCRD_GTCCRD_Pos (0UL) +#define R_GPT0_GTCCRF_GTCCRF_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTCCRF_GTCCRF_Pos (0UL) +#define R_GPT0_GTPR_GTPR_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTPR_GTPR_Pos (0UL) +#define R_GPT0_GTPBR_GTPBR_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTPBR_GTPBR_Pos (0UL) +#define R_GPT0_GTPDBR_GTPDBR_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) +#define R_GPT0_GTADTRA_GTADTRA_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) +#define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) +#define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) +#define R_GPT0_GTADTRB_GTADTRB_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) +#define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) +#define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) +#define R_GPT0_GTDTCR_TDE_Msk (0x00000001UL) +#define R_GPT0_GTDTCR_TDE_Pos (0UL) +#define R_GPT0_GTDTCR_TDBUE_Msk (0x00000010UL) +#define R_GPT0_GTDTCR_TDBUE_Pos (4UL) +#define R_GPT0_GTDTCR_TDBDE_Msk (0x00000020UL) +#define R_GPT0_GTDTCR_TDBDE_Pos (5UL) +#define R_GPT0_GTDTCR_TDFER_Msk (0x00000100UL) +#define R_GPT0_GTDTCR_TDFER_Pos (8UL) +#define R_GPT0_GTDVU_GTDVU_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTDVU_GTDVU_Pos (0UL) +#define R_GPT0_GTDVD_GTDVD_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTDVD_GTDVD_Pos (0UL) +#define R_GPT0_GTDBU_GTDBU_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTDBU_GTDBU_Pos (0UL) +#define R_GPT0_GTDBD_GTDBD_Msk (0xFFFFFFFFUL) +#define R_GPT0_GTDBD_GTDBD_Pos (0UL) +#define R_GPT0_GTSOS_SOS_Msk (0x00000003UL) +#define R_GPT0_GTSOS_SOS_Pos (0UL) +#define R_GPT0_GTSOTR_SOTR_Msk (0x00000001UL) +#define R_GPT0_GTSOTR_SOTR_Pos (0UL) + +#endif /* GPT_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gtm_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gtm_iobitmask.h new file mode 100644 index 00000000..543b5c2f --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/gtm_iobitmask.h @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : gtm_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for gtm. + *********************************************************************************************************************/ + +#ifndef GTM_IOBITMASK_H +#define GTM_IOBITMASK_H + +#define R_GTM0_OSTMnCMP_OSTMnCMP_Msk (0xFFFFFFFFUL) +#define R_GTM0_OSTMnCMP_OSTMnCMP_Pos (0UL) +#define R_GTM0_OSTMnCNT_OSTMnCNT_Msk (0xFFFFFFFFUL) +#define R_GTM0_OSTMnCNT_OSTMnCNT_Pos (0UL) +#define R_GTM0_OSTMnTE_OSTMnTE_Msk (0x01UL) +#define R_GTM0_OSTMnTE_OSTMnTE_Pos (0UL) +#define R_GTM0_OSTMnTS_OSTMnTS_Msk (0x01UL) +#define R_GTM0_OSTMnTS_OSTMnTS_Pos (0UL) +#define R_GTM0_OSTMnTT_OSTMnTT_Msk (0x01UL) +#define R_GTM0_OSTMnTT_OSTMnTT_Pos (0UL) +#define R_GTM0_OSTMnCTL_OSTMnMD0_Msk (0x01UL) +#define R_GTM0_OSTMnCTL_OSTMnMD0_Pos (0UL) +#define R_GTM0_OSTMnCTL_OSTMnMD1_Msk (0x02UL) +#define R_GTM0_OSTMnCTL_OSTMnMD1_Pos (1UL) + +#endif /* GTM_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/intc_im33_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/intc_im33_iobitmask.h new file mode 100644 index 00000000..500c9470 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/intc_im33_iobitmask.h @@ -0,0 +1,685 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : intc_im33_iobitmask.h.h + * Version : 1.00 + * Description : IO bit mask file for intc_im33. + *********************************************************************************************************************/ + +#ifndef INTC_IM33_IOBITMASK_H +#define INTC_IM33_IOBITMASK_H + +#define R_INTC_IM33_NSCR_NSTAT_Msk (0x00000001UL) +#define R_INTC_IM33_NSCR_NSTAT_Pos (0UL) +#define R_INTC_IM33_NSCR_NSMON_Msk (0x00010000UL) +#define R_INTC_IM33_NSCR_NSMON_Pos (16UL) +#define R_INTC_IM33_NITSR_NTSEL_Msk (0x00000001UL) +#define R_INTC_IM33_NITSR_NTSEL_Pos (0UL) +#define R_INTC_IM33_ISCR_ISTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_ISCR_ISTAT0_Pos (0UL) +#define R_INTC_IM33_ISCR_ISTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_ISCR_ISTAT1_Pos (1UL) +#define R_INTC_IM33_ISCR_ISTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_ISCR_ISTAT2_Pos (2UL) +#define R_INTC_IM33_ISCR_ISTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_ISCR_ISTAT3_Pos (3UL) +#define R_INTC_IM33_ISCR_ISTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_ISCR_ISTAT4_Pos (4UL) +#define R_INTC_IM33_ISCR_ISTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_ISCR_ISTAT5_Pos (5UL) +#define R_INTC_IM33_ISCR_ISTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_ISCR_ISTAT6_Pos (6UL) +#define R_INTC_IM33_ISCR_ISTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_ISCR_ISTAT7_Pos (7UL) +#define R_INTC_IM33_IITSR_IITSEL0_Msk (0x00000003UL) +#define R_INTC_IM33_IITSR_IITSEL0_Pos (0UL) +#define R_INTC_IM33_IITSR_IITSEL1_Msk (0x0000000CUL) +#define R_INTC_IM33_IITSR_IITSEL1_Pos (2UL) +#define R_INTC_IM33_IITSR_IITSEL2_Msk (0x00000030UL) +#define R_INTC_IM33_IITSR_IITSEL2_Pos (4UL) +#define R_INTC_IM33_IITSR_IITSEL3_Msk (0x000000C0UL) +#define R_INTC_IM33_IITSR_IITSEL3_Pos (6UL) +#define R_INTC_IM33_IITSR_IITSEL4_Msk (0x00000300UL) +#define R_INTC_IM33_IITSR_IITSEL4_Pos (8UL) +#define R_INTC_IM33_IITSR_IITSEL5_Msk (0x00000C00UL) +#define R_INTC_IM33_IITSR_IITSEL5_Pos (10UL) +#define R_INTC_IM33_IITSR_IITSEL6_Msk (0x00003000UL) +#define R_INTC_IM33_IITSR_IITSEL6_Pos (12UL) +#define R_INTC_IM33_IITSR_IITSEL7_Msk (0x0000C000UL) +#define R_INTC_IM33_IITSR_IITSEL7_Pos (14UL) +#define R_INTC_IM33_TSCR_TSTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_TSCR_TSTAT0_Pos (0UL) +#define R_INTC_IM33_TSCR_TSTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_TSCR_TSTAT1_Pos (1UL) +#define R_INTC_IM33_TSCR_TSTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_TSCR_TSTAT2_Pos (2UL) +#define R_INTC_IM33_TSCR_TSTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_TSCR_TSTAT3_Pos (3UL) +#define R_INTC_IM33_TSCR_TSTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_TSCR_TSTAT4_Pos (4UL) +#define R_INTC_IM33_TSCR_TSTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_TSCR_TSTAT5_Pos (5UL) +#define R_INTC_IM33_TSCR_TSTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_TSCR_TSTAT6_Pos (6UL) +#define R_INTC_IM33_TSCR_TSTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_TSCR_TSTAT7_Pos (7UL) +#define R_INTC_IM33_TSCR_TSTAT8_Msk (0x00000100UL) +#define R_INTC_IM33_TSCR_TSTAT8_Pos (8UL) +#define R_INTC_IM33_TSCR_TSTAT9_Msk (0x00000200UL) +#define R_INTC_IM33_TSCR_TSTAT9_Pos (9UL) +#define R_INTC_IM33_TSCR_TSTAT10_Msk (0x00000400UL) +#define R_INTC_IM33_TSCR_TSTAT10_Pos (10UL) +#define R_INTC_IM33_TSCR_TSTAT11_Msk (0x00000800UL) +#define R_INTC_IM33_TSCR_TSTAT11_Pos (11UL) +#define R_INTC_IM33_TSCR_TSTAT12_Msk (0x00001000UL) +#define R_INTC_IM33_TSCR_TSTAT12_Pos (12UL) +#define R_INTC_IM33_TSCR_TSTAT13_Msk (0x00002000UL) +#define R_INTC_IM33_TSCR_TSTAT13_Pos (13UL) +#define R_INTC_IM33_TSCR_TSTAT14_Msk (0x00004000UL) +#define R_INTC_IM33_TSCR_TSTAT14_Pos (14UL) +#define R_INTC_IM33_TSCR_TSTAT15_Msk (0x00008000UL) +#define R_INTC_IM33_TSCR_TSTAT15_Pos (15UL) +#define R_INTC_IM33_TSCR_TSTAT16_Msk (0x00010000UL) +#define R_INTC_IM33_TSCR_TSTAT16_Pos (16UL) +#define R_INTC_IM33_TSCR_TSTAT17_Msk (0x00020000UL) +#define R_INTC_IM33_TSCR_TSTAT17_Pos (17UL) +#define R_INTC_IM33_TSCR_TSTAT18_Msk (0x00040000UL) +#define R_INTC_IM33_TSCR_TSTAT18_Pos (18UL) +#define R_INTC_IM33_TSCR_TSTAT19_Msk (0x00080000UL) +#define R_INTC_IM33_TSCR_TSTAT19_Pos (19UL) +#define R_INTC_IM33_TSCR_TSTAT20_Msk (0x00100000UL) +#define R_INTC_IM33_TSCR_TSTAT20_Pos (20UL) +#define R_INTC_IM33_TSCR_TSTAT21_Msk (0x00200000UL) +#define R_INTC_IM33_TSCR_TSTAT21_Pos (21UL) +#define R_INTC_IM33_TSCR_TSTAT22_Msk (0x00400000UL) +#define R_INTC_IM33_TSCR_TSTAT22_Pos (22UL) +#define R_INTC_IM33_TSCR_TSTAT23_Msk (0x00800000UL) +#define R_INTC_IM33_TSCR_TSTAT23_Pos (23UL) +#define R_INTC_IM33_TSCR_TSTAT24_Msk (0x01000000UL) +#define R_INTC_IM33_TSCR_TSTAT24_Pos (24UL) +#define R_INTC_IM33_TSCR_TSTAT25_Msk (0x02000000UL) +#define R_INTC_IM33_TSCR_TSTAT25_Pos (25UL) +#define R_INTC_IM33_TSCR_TSTAT26_Msk (0x04000000UL) +#define R_INTC_IM33_TSCR_TSTAT26_Pos (26UL) +#define R_INTC_IM33_TSCR_TSTAT27_Msk (0x08000000UL) +#define R_INTC_IM33_TSCR_TSTAT27_Pos (27UL) +#define R_INTC_IM33_TSCR_TSTAT28_Msk (0x10000000UL) +#define R_INTC_IM33_TSCR_TSTAT28_Pos (28UL) +#define R_INTC_IM33_TSCR_TSTAT29_Msk (0x20000000UL) +#define R_INTC_IM33_TSCR_TSTAT29_Pos (29UL) +#define R_INTC_IM33_TSCR_TSTAT30_Msk (0x40000000UL) +#define R_INTC_IM33_TSCR_TSTAT30_Pos (30UL) +#define R_INTC_IM33_TSCR_TSTAT31_Msk (0x80000000UL) +#define R_INTC_IM33_TSCR_TSTAT31_Pos (31UL) +#define R_INTC_IM33_TITSR0_TITSEL0_Msk (0x00000003UL) +#define R_INTC_IM33_TITSR0_TITSEL0_Pos (0UL) +#define R_INTC_IM33_TITSR0_TITSEL1_Msk (0x0000000CUL) +#define R_INTC_IM33_TITSR0_TITSEL1_Pos (2UL) +#define R_INTC_IM33_TITSR0_TITSEL2_Msk (0x00000030UL) +#define R_INTC_IM33_TITSR0_TITSEL2_Pos (4UL) +#define R_INTC_IM33_TITSR0_TITSEL3_Msk (0x000000C0UL) +#define R_INTC_IM33_TITSR0_TITSEL3_Pos (6UL) +#define R_INTC_IM33_TITSR0_TITSEL4_Msk (0x00000300UL) +#define R_INTC_IM33_TITSR0_TITSEL4_Pos (8UL) +#define R_INTC_IM33_TITSR0_TITSEL5_Msk (0x00000C00UL) +#define R_INTC_IM33_TITSR0_TITSEL5_Pos (10UL) +#define R_INTC_IM33_TITSR0_TITSEL6_Msk (0x00003000UL) +#define R_INTC_IM33_TITSR0_TITSEL6_Pos (12UL) +#define R_INTC_IM33_TITSR0_TITSEL7_Msk (0x0000C000UL) +#define R_INTC_IM33_TITSR0_TITSEL7_Pos (14UL) +#define R_INTC_IM33_TITSR0_TITSEL8_Msk (0x00030000UL) +#define R_INTC_IM33_TITSR0_TITSEL8_Pos (16UL) +#define R_INTC_IM33_TITSR0_TITSEL9_Msk (0x000C0000UL) +#define R_INTC_IM33_TITSR0_TITSEL9_Pos (18UL) +#define R_INTC_IM33_TITSR0_TITSEL10_Msk (0x00300000UL) +#define R_INTC_IM33_TITSR0_TITSEL10_Pos (20UL) +#define R_INTC_IM33_TITSR0_TITSEL11_Msk (0x00C00000UL) +#define R_INTC_IM33_TITSR0_TITSEL11_Pos (22UL) +#define R_INTC_IM33_TITSR0_TITSEL12_Msk (0x03000000UL) +#define R_INTC_IM33_TITSR0_TITSEL12_Pos (24UL) +#define R_INTC_IM33_TITSR0_TITSEL13_Msk (0x0C000000UL) +#define R_INTC_IM33_TITSR0_TITSEL13_Pos (26UL) +#define R_INTC_IM33_TITSR0_TITSEL14_Msk (0x30000000UL) +#define R_INTC_IM33_TITSR0_TITSEL14_Pos (28UL) +#define R_INTC_IM33_TITSR0_TITSEL15_Msk (0xC0000000UL) +#define R_INTC_IM33_TITSR0_TITSEL15_Pos (30UL) +#define R_INTC_IM33_TITSR1_TITSEL16_Msk (0x00000003UL) +#define R_INTC_IM33_TITSR1_TITSEL16_Pos (0UL) +#define R_INTC_IM33_TITSR1_TITSEL17_Msk (0x0000000CUL) +#define R_INTC_IM33_TITSR1_TITSEL17_Pos (2UL) +#define R_INTC_IM33_TITSR1_TITSEL18_Msk (0x00000030UL) +#define R_INTC_IM33_TITSR1_TITSEL18_Pos (4UL) +#define R_INTC_IM33_TITSR1_TITSEL19_Msk (0x000000C0UL) +#define R_INTC_IM33_TITSR1_TITSEL19_Pos (6UL) +#define R_INTC_IM33_TITSR1_TITSEL20_Msk (0x00000300UL) +#define R_INTC_IM33_TITSR1_TITSEL20_Pos (8UL) +#define R_INTC_IM33_TITSR1_TITSEL21_Msk (0x00000C00UL) +#define R_INTC_IM33_TITSR1_TITSEL21_Pos (10UL) +#define R_INTC_IM33_TITSR1_TITSEL22_Msk (0x00003000UL) +#define R_INTC_IM33_TITSR1_TITSEL22_Pos (12UL) +#define R_INTC_IM33_TITSR1_TITSEL23_Msk (0x0000C000UL) +#define R_INTC_IM33_TITSR1_TITSEL23_Pos (14UL) +#define R_INTC_IM33_TITSR1_TITSEL24_Msk (0x00030000UL) +#define R_INTC_IM33_TITSR1_TITSEL24_Pos (16UL) +#define R_INTC_IM33_TITSR1_TITSEL25_Msk (0x000C0000UL) +#define R_INTC_IM33_TITSR1_TITSEL25_Pos (18UL) +#define R_INTC_IM33_TITSR1_TITSEL26_Msk (0x00300000UL) +#define R_INTC_IM33_TITSR1_TITSEL26_Pos (20UL) +#define R_INTC_IM33_TITSR1_TITSEL27_Msk (0x00C00000UL) +#define R_INTC_IM33_TITSR1_TITSEL27_Pos (22UL) +#define R_INTC_IM33_TITSR1_TITSEL28_Msk (0x03000000UL) +#define R_INTC_IM33_TITSR1_TITSEL28_Pos (24UL) +#define R_INTC_IM33_TITSR1_TITSEL29_Msk (0x0C000000UL) +#define R_INTC_IM33_TITSR1_TITSEL29_Pos (26UL) +#define R_INTC_IM33_TITSR1_TITSEL30_Msk (0x30000000UL) +#define R_INTC_IM33_TITSR1_TITSEL30_Pos (28UL) +#define R_INTC_IM33_TITSR1_TITSEL31_Msk (0xC0000000UL) +#define R_INTC_IM33_TITSR1_TITSEL31_Pos (30UL) +#define R_INTC_IM33_TSSR0_TSSEL0_Msk (0x0000007FUL) +#define R_INTC_IM33_TSSR0_TSSEL0_Pos (0UL) +#define R_INTC_IM33_TSSR0_TIEN0_Msk (0x00000080UL) +#define R_INTC_IM33_TSSR0_TIEN0_Pos (7UL) +#define R_INTC_IM33_TSSR0_TSSEL1_Msk (0x00007F00UL) +#define R_INTC_IM33_TSSR0_TSSEL1_Pos (8UL) +#define R_INTC_IM33_TSSR0_TIEN1_Msk (0x00008000UL) +#define R_INTC_IM33_TSSR0_TIEN1_Pos (15UL) +#define R_INTC_IM33_TSSR0_TSSEL2_Msk (0x007F0000UL) +#define R_INTC_IM33_TSSR0_TSSEL2_Pos (16UL) +#define R_INTC_IM33_TSSR0_TIEN2_Msk (0x00800000UL) +#define R_INTC_IM33_TSSR0_TIEN2_Pos (23UL) +#define R_INTC_IM33_TSSR0_TSSEL3_Msk (0x7F000000UL) +#define R_INTC_IM33_TSSR0_TSSEL3_Pos (24UL) +#define R_INTC_IM33_TSSR0_TIEN3_Msk (0x80000000UL) +#define R_INTC_IM33_TSSR0_TIEN3_Pos (31UL) +#define R_INTC_IM33_TSSR1_TSSEL4_Msk (0x0000007FUL) +#define R_INTC_IM33_TSSR1_TSSEL4_Pos (0UL) +#define R_INTC_IM33_TSSR1_TIEN4_Msk (0x00000080UL) +#define R_INTC_IM33_TSSR1_TIEN4_Pos (7UL) +#define R_INTC_IM33_TSSR1_TSSEL5_Msk (0x00007F00UL) +#define R_INTC_IM33_TSSR1_TSSEL5_Pos (8UL) +#define R_INTC_IM33_TSSR1_TIEN5_Msk (0x00008000UL) +#define R_INTC_IM33_TSSR1_TIEN5_Pos (15UL) +#define R_INTC_IM33_TSSR1_TSSEL6_Msk (0x007F0000UL) +#define R_INTC_IM33_TSSR1_TSSEL6_Pos (16UL) +#define R_INTC_IM33_TSSR1_TIEN6_Msk (0x00800000UL) +#define R_INTC_IM33_TSSR1_TIEN6_Pos (23UL) +#define R_INTC_IM33_TSSR1_TSSEL7_Msk (0x7F000000UL) +#define R_INTC_IM33_TSSR1_TSSEL7_Pos (24UL) +#define R_INTC_IM33_TSSR1_TIEN7_Msk (0x80000000UL) +#define R_INTC_IM33_TSSR1_TIEN7_Pos (31UL) +#define R_INTC_IM33_TSSR2_TSSEL8_Msk (0x0000007FUL) +#define R_INTC_IM33_TSSR2_TSSEL8_Pos (0UL) +#define R_INTC_IM33_TSSR2_TIEN8_Msk (0x00000080UL) +#define R_INTC_IM33_TSSR2_TIEN8_Pos (7UL) +#define R_INTC_IM33_TSSR2_TSSEL9_Msk (0x00007F00UL) +#define R_INTC_IM33_TSSR2_TSSEL9_Pos (8UL) +#define R_INTC_IM33_TSSR2_TIEN9_Msk (0x00008000UL) +#define R_INTC_IM33_TSSR2_TIEN9_Pos (15UL) +#define R_INTC_IM33_TSSR2_TSSEL10_Msk (0x007F0000UL) +#define R_INTC_IM33_TSSR2_TSSEL10_Pos (16UL) +#define R_INTC_IM33_TSSR2_TIEN10_Msk (0x00800000UL) +#define R_INTC_IM33_TSSR2_TIEN10_Pos (23UL) +#define R_INTC_IM33_TSSR2_TSSEL11_Msk (0x7F000000UL) +#define R_INTC_IM33_TSSR2_TSSEL11_Pos (24UL) +#define R_INTC_IM33_TSSR2_TIEN11_Msk (0x80000000UL) +#define R_INTC_IM33_TSSR2_TIEN11_Pos (31UL) +#define R_INTC_IM33_TSSR3_TSSEL12_Msk (0x0000007FUL) +#define R_INTC_IM33_TSSR3_TSSEL12_Pos (0UL) +#define R_INTC_IM33_TSSR3_TIEN12_Msk (0x00000080UL) +#define R_INTC_IM33_TSSR3_TIEN12_Pos (7UL) +#define R_INTC_IM33_TSSR3_TSSEL13_Msk (0x00007F00UL) +#define R_INTC_IM33_TSSR3_TSSEL13_Pos (8UL) +#define R_INTC_IM33_TSSR3_TIEN13_Msk (0x00008000UL) +#define R_INTC_IM33_TSSR3_TIEN13_Pos (15UL) +#define R_INTC_IM33_TSSR3_TSSEL14_Msk (0x007F0000UL) +#define R_INTC_IM33_TSSR3_TSSEL14_Pos (16UL) +#define R_INTC_IM33_TSSR3_TIEN14_Msk (0x00800000UL) +#define R_INTC_IM33_TSSR3_TIEN14_Pos (23UL) +#define R_INTC_IM33_TSSR3_TSSEL15_Msk (0x7F000000UL) +#define R_INTC_IM33_TSSR3_TSSEL15_Pos (24UL) +#define R_INTC_IM33_TSSR3_TIEN15_Msk (0x80000000UL) +#define R_INTC_IM33_TSSR3_TIEN15_Pos (31UL) +#define R_INTC_IM33_TSSR4_TSSEL16_Msk (0x0000007FUL) +#define R_INTC_IM33_TSSR4_TSSEL16_Pos (0UL) +#define R_INTC_IM33_TSSR4_TIEN16_Msk (0x00000080UL) +#define R_INTC_IM33_TSSR4_TIEN16_Pos (7UL) +#define R_INTC_IM33_TSSR4_TSSEL17_Msk (0x00007F00UL) +#define R_INTC_IM33_TSSR4_TSSEL17_Pos (8UL) +#define R_INTC_IM33_TSSR4_TIEN17_Msk (0x00008000UL) +#define R_INTC_IM33_TSSR4_TIEN17_Pos (15UL) +#define R_INTC_IM33_TSSR4_TSSEL18_Msk (0x007F0000UL) +#define R_INTC_IM33_TSSR4_TSSEL18_Pos (16UL) +#define R_INTC_IM33_TSSR4_TIEN18_Msk (0x00800000UL) +#define R_INTC_IM33_TSSR4_TIEN18_Pos (23UL) +#define R_INTC_IM33_TSSR4_TSSEL19_Msk (0x7F000000UL) +#define R_INTC_IM33_TSSR4_TSSEL19_Pos (24UL) +#define R_INTC_IM33_TSSR4_TIEN19_Msk (0x80000000UL) +#define R_INTC_IM33_TSSR4_TIEN19_Pos (31UL) +#define R_INTC_IM33_TSSR5_TSSEL20_Msk (0x0000007FUL) +#define R_INTC_IM33_TSSR5_TSSEL20_Pos (0UL) +#define R_INTC_IM33_TSSR5_TIEN20_Msk (0x00000080UL) +#define R_INTC_IM33_TSSR5_TIEN20_Pos (7UL) +#define R_INTC_IM33_TSSR5_TSSEL21_Msk (0x00007F00UL) +#define R_INTC_IM33_TSSR5_TSSEL21_Pos (8UL) +#define R_INTC_IM33_TSSR5_TIEN21_Msk (0x00008000UL) +#define R_INTC_IM33_TSSR5_TIEN21_Pos (15UL) +#define R_INTC_IM33_TSSR5_TSSEL22_Msk (0x007F0000UL) +#define R_INTC_IM33_TSSR5_TSSEL22_Pos (16UL) +#define R_INTC_IM33_TSSR5_TIEN22_Msk (0x00800000UL) +#define R_INTC_IM33_TSSR5_TIEN22_Pos (23UL) +#define R_INTC_IM33_TSSR5_TSSEL23_Msk (0x7F000000UL) +#define R_INTC_IM33_TSSR5_TSSEL23_Pos (24UL) +#define R_INTC_IM33_TSSR5_TIEN23_Msk (0x80000000UL) +#define R_INTC_IM33_TSSR5_TIEN23_Pos (31UL) +#define R_INTC_IM33_TSSR6_TSSEL24_Msk (0x0000007FUL) +#define R_INTC_IM33_TSSR6_TSSEL24_Pos (0UL) +#define R_INTC_IM33_TSSR6_TIEN24_Msk (0x00000080UL) +#define R_INTC_IM33_TSSR6_TIEN24_Pos (7UL) +#define R_INTC_IM33_TSSR6_TSSEL25_Msk (0x00007F00UL) +#define R_INTC_IM33_TSSR6_TSSEL25_Pos (8UL) +#define R_INTC_IM33_TSSR6_TIEN25_Msk (0x00008000UL) +#define R_INTC_IM33_TSSR6_TIEN25_Pos (15UL) +#define R_INTC_IM33_TSSR6_TSSEL26_Msk (0x007F0000UL) +#define R_INTC_IM33_TSSR6_TSSEL26_Pos (16UL) +#define R_INTC_IM33_TSSR6_TIEN26_Msk (0x00800000UL) +#define R_INTC_IM33_TSSR6_TIEN26_Pos (23UL) +#define R_INTC_IM33_TSSR6_TSSEL27_Msk (0x7F000000UL) +#define R_INTC_IM33_TSSR6_TSSEL27_Pos (24UL) +#define R_INTC_IM33_TSSR6_TIEN27_Msk (0x80000000UL) +#define R_INTC_IM33_TSSR6_TIEN27_Pos (31UL) +#define R_INTC_IM33_TSSR7_TSSEL28_Msk (0x0000007FUL) +#define R_INTC_IM33_TSSR7_TSSEL28_Pos (0UL) +#define R_INTC_IM33_TSSR7_TIEN28_Msk (0x00000080UL) +#define R_INTC_IM33_TSSR7_TIEN28_Pos (7UL) +#define R_INTC_IM33_TSSR7_TSSEL29_Msk (0x00007F00UL) +#define R_INTC_IM33_TSSR7_TSSEL29_Pos (8UL) +#define R_INTC_IM33_TSSR7_TIEN29_Msk (0x00008000UL) +#define R_INTC_IM33_TSSR7_TIEN29_Pos (15UL) +#define R_INTC_IM33_TSSR7_TSSEL30_Msk (0x007F0000UL) +#define R_INTC_IM33_TSSR7_TSSEL30_Pos (16UL) +#define R_INTC_IM33_TSSR7_TIEN30_Msk (0x00800000UL) +#define R_INTC_IM33_TSSR7_TIEN30_Pos (23UL) +#define R_INTC_IM33_TSSR7_TSSEL31_Msk (0x7F000000UL) +#define R_INTC_IM33_TSSR7_TSSEL31_Pos (24UL) +#define R_INTC_IM33_TSSR7_TIEN31_Msk (0x80000000UL) +#define R_INTC_IM33_TSSR7_TIEN31_Pos (31UL) +#define R_INTC_IM33_BEISR0_BESTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_BEISR0_BESTAT0_Pos (0UL) +#define R_INTC_IM33_BEISR0_BESTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_BEISR0_BESTAT1_Pos (1UL) +#define R_INTC_IM33_BEISR0_BESTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_BEISR0_BESTAT2_Pos (2UL) +#define R_INTC_IM33_BEISR0_BESTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_BEISR0_BESTAT3_Pos (3UL) +#define R_INTC_IM33_BEISR0_BESTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_BEISR0_BESTAT4_Pos (4UL) +#define R_INTC_IM33_BEISR0_BESTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_BEISR0_BESTAT5_Pos (5UL) +#define R_INTC_IM33_BEISR0_BESTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_BEISR0_BESTAT6_Pos (6UL) +#define R_INTC_IM33_BEISR0_BESTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_BEISR0_BESTAT7_Pos (7UL) +#define R_INTC_IM33_BEISR0_BESTAT8_Msk (0x00000100UL) +#define R_INTC_IM33_BEISR0_BESTAT8_Pos (8UL) +#define R_INTC_IM33_BEISR0_BESTAT9_Msk (0x00000200UL) +#define R_INTC_IM33_BEISR0_BESTAT9_Pos (9UL) +#define R_INTC_IM33_BEISR0_BESTAT10_Msk (0x00000400UL) +#define R_INTC_IM33_BEISR0_BESTAT10_Pos (10UL) +#define R_INTC_IM33_BEISR0_BESTAT11_Msk (0x00000800UL) +#define R_INTC_IM33_BEISR0_BESTAT11_Pos (11UL) +#define R_INTC_IM33_BEISR0_BESTAT12_Msk (0x00001000UL) +#define R_INTC_IM33_BEISR0_BESTAT12_Pos (12UL) +#define R_INTC_IM33_BEISR0_BESTAT13_Msk (0x00002000UL) +#define R_INTC_IM33_BEISR0_BESTAT13_Pos (13UL) +#define R_INTC_IM33_BEISR0_BESTAT14_Msk (0x00004000UL) +#define R_INTC_IM33_BEISR0_BESTAT14_Pos (14UL) +#define R_INTC_IM33_BEISR0_BESTAT15_Msk (0x00008000UL) +#define R_INTC_IM33_BEISR0_BESTAT15_Pos (15UL) +#define R_INTC_IM33_BEISR0_BESTAT16_Msk (0x00010000UL) +#define R_INTC_IM33_BEISR0_BESTAT16_Pos (16UL) +#define R_INTC_IM33_BEISR0_BESTAT17_Msk (0x00020000UL) +#define R_INTC_IM33_BEISR0_BESTAT17_Pos (17UL) +#define R_INTC_IM33_BEISR0_BESTAT18_Msk (0x00040000UL) +#define R_INTC_IM33_BEISR0_BESTAT18_Pos (18UL) +#define R_INTC_IM33_BEISR0_BESTAT19_Msk (0x00080000UL) +#define R_INTC_IM33_BEISR0_BESTAT19_Pos (19UL) +#define R_INTC_IM33_BEISR0_BESTAT20_Msk (0x00100000UL) +#define R_INTC_IM33_BEISR0_BESTAT20_Pos (20UL) +#define R_INTC_IM33_BEISR0_BESTAT21_Msk (0x00200000UL) +#define R_INTC_IM33_BEISR0_BESTAT21_Pos (21UL) +#define R_INTC_IM33_BEISR0_BESTAT22_Msk (0x00400000UL) +#define R_INTC_IM33_BEISR0_BESTAT22_Pos (22UL) +#define R_INTC_IM33_BEISR0_BESTAT23_Msk (0x00800000UL) +#define R_INTC_IM33_BEISR0_BESTAT23_Pos (23UL) +#define R_INTC_IM33_BEISR0_BESTAT24_Msk (0x01000000UL) +#define R_INTC_IM33_BEISR0_BESTAT24_Pos (24UL) +#define R_INTC_IM33_BEISR0_BESTAT25_Msk (0x02000000UL) +#define R_INTC_IM33_BEISR0_BESTAT25_Pos (25UL) +#define R_INTC_IM33_BEISR0_BESTAT26_Msk (0x04000000UL) +#define R_INTC_IM33_BEISR0_BESTAT26_Pos (26UL) +#define R_INTC_IM33_BEISR0_BESTAT27_Msk (0x08000000UL) +#define R_INTC_IM33_BEISR0_BESTAT27_Pos (27UL) +#define R_INTC_IM33_BEISR0_BESTAT28_Msk (0x10000000UL) +#define R_INTC_IM33_BEISR0_BESTAT28_Pos (28UL) +#define R_INTC_IM33_BEISR0_BESTAT29_Msk (0x20000000UL) +#define R_INTC_IM33_BEISR0_BESTAT29_Pos (29UL) +#define R_INTC_IM33_BEISR0_BESTAT30_Msk (0x40000000UL) +#define R_INTC_IM33_BEISR0_BESTAT30_Pos (30UL) +#define R_INTC_IM33_BEISR0_BESTAT31_Msk (0x80000000UL) +#define R_INTC_IM33_BEISR0_BESTAT31_Pos (31UL) +#define R_INTC_IM33_BEISR1_BESTAT32_Msk (0x00000001UL) +#define R_INTC_IM33_BEISR1_BESTAT32_Pos (0UL) +#define R_INTC_IM33_BEISR1_BESTAT33_Msk (0x00000002UL) +#define R_INTC_IM33_BEISR1_BESTAT33_Pos (1UL) +#define R_INTC_IM33_BEISR1_BESTAT34_Msk (0x00000004UL) +#define R_INTC_IM33_BEISR1_BESTAT34_Pos (2UL) +#define R_INTC_IM33_BEISR1_BESTAT35_Msk (0x00000008UL) +#define R_INTC_IM33_BEISR1_BESTAT35_Pos (3UL) +#define R_INTC_IM33_BEISR1_BESTAT36_Msk (0x00000010UL) +#define R_INTC_IM33_BEISR1_BESTAT36_Pos (4UL) +#define R_INTC_IM33_BEISR1_BESTAT37_Msk (0x00000020UL) +#define R_INTC_IM33_BEISR1_BESTAT37_Pos (5UL) +#define R_INTC_IM33_BEISR1_BESTAT38_Msk (0x00000040UL) +#define R_INTC_IM33_BEISR1_BESTAT38_Pos (6UL) +#define R_INTC_IM33_BEISR1_BESTAT39_Msk (0x00000080UL) +#define R_INTC_IM33_BEISR1_BESTAT39_Pos (7UL) +#define R_INTC_IM33_BEISR1_BESTAT40_Msk (0x00000100UL) +#define R_INTC_IM33_BEISR1_BESTAT40_Pos (8UL) +#define R_INTC_IM33_BEISR1_BESTAT41_Msk (0x00000200UL) +#define R_INTC_IM33_BEISR1_BESTAT41_Pos (9UL) +#define R_INTC_IM33_BEISR1_BESTAT42_Msk (0x00000400UL) +#define R_INTC_IM33_BEISR1_BESTAT42_Pos (10UL) +#define R_INTC_IM33_BEISR1_BESTAT43_Msk (0x00000800UL) +#define R_INTC_IM33_BEISR1_BESTAT43_Pos (11UL) +#define R_INTC_IM33_BEISR1_BESTAT44_Msk (0x00001000UL) +#define R_INTC_IM33_BEISR1_BESTAT44_Pos (12UL) +#define R_INTC_IM33_BEISR1_BESTAT45_Msk (0x00002000UL) +#define R_INTC_IM33_BEISR1_BESTAT45_Pos (13UL) +#define R_INTC_IM33_BEISR1_BESTAT46_Msk (0x00004000UL) +#define R_INTC_IM33_BEISR1_BESTAT46_Pos (14UL) +#define R_INTC_IM33_EREISR0_A01ESTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_EREISR0_A01ESTAT0_Pos (0UL) +#define R_INTC_IM33_EREISR0_A01ESTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_EREISR0_A01ESTAT1_Pos (1UL) +#define R_INTC_IM33_EREISR0_A01ESTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_EREISR0_A01ESTAT2_Pos (2UL) +#define R_INTC_IM33_EREISR0_A01ESTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_EREISR0_A01ESTAT3_Pos (3UL) +#define R_INTC_IM33_EREISR0_A01ESTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_EREISR0_A01ESTAT4_Pos (4UL) +#define R_INTC_IM33_EREISR0_A01ESTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_EREISR0_A01ESTAT5_Pos (5UL) +#define R_INTC_IM33_EREISR0_A01ESTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_EREISR0_A01ESTAT6_Pos (6UL) +#define R_INTC_IM33_EREISR0_A01ESTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_EREISR0_A01ESTAT7_Pos (7UL) +#define R_INTC_IM33_EREISR0_A11ESTAT0_Msk (0x00000100UL) +#define R_INTC_IM33_EREISR0_A11ESTAT0_Pos (8UL) +#define R_INTC_IM33_EREISR0_A11ESTAT1_Msk (0x00000200UL) +#define R_INTC_IM33_EREISR0_A11ESTAT1_Pos (9UL) +#define R_INTC_IM33_EREISR0_A11ESTAT2_Msk (0x00000400UL) +#define R_INTC_IM33_EREISR0_A11ESTAT2_Pos (10UL) +#define R_INTC_IM33_EREISR0_A11ESTAT3_Msk (0x00000800UL) +#define R_INTC_IM33_EREISR0_A11ESTAT3_Pos (11UL) +#define R_INTC_IM33_EREISR0_A11ESTAT4_Msk (0x00001000UL) +#define R_INTC_IM33_EREISR0_A11ESTAT4_Pos (12UL) +#define R_INTC_IM33_EREISR0_A11ESTAT5_Msk (0x00002000UL) +#define R_INTC_IM33_EREISR0_A11ESTAT5_Pos (13UL) +#define R_INTC_IM33_EREISR0_A11ESTAT6_Msk (0x00004000UL) +#define R_INTC_IM33_EREISR0_A11ESTAT6_Pos (14UL) +#define R_INTC_IM33_EREISR0_A11ESTAT7_Msk (0x00008000UL) +#define R_INTC_IM33_EREISR0_A11ESTAT7_Pos (15UL) +#define R_INTC_IM33_EREISR1_M01ESTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_EREISR1_M01ESTAT0_Pos (0UL) +#define R_INTC_IM33_EREISR1_M01ESTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_EREISR1_M01ESTAT1_Pos (1UL) +#define R_INTC_IM33_EREISR1_M01ESTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_EREISR1_M01ESTAT2_Pos (2UL) +#define R_INTC_IM33_EREISR1_M01ESTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_EREISR1_M01ESTAT3_Pos (3UL) +#define R_INTC_IM33_EREISR1_M01ESTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_EREISR1_M01ESTAT4_Pos (4UL) +#define R_INTC_IM33_EREISR1_M01ESTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_EREISR1_M01ESTAT5_Pos (5UL) +#define R_INTC_IM33_EREISR1_M01ESTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_EREISR1_M01ESTAT6_Pos (6UL) +#define R_INTC_IM33_EREISR1_M01ESTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_EREISR1_M01ESTAT7_Pos (7UL) +#define R_INTC_IM33_EREISR1_M11ESTAT0_Msk (0x00000100UL) +#define R_INTC_IM33_EREISR1_M11ESTAT0_Pos (8UL) +#define R_INTC_IM33_EREISR1_M11ESTAT1_Msk (0x00000200UL) +#define R_INTC_IM33_EREISR1_M11ESTAT1_Pos (9UL) +#define R_INTC_IM33_EREISR1_M11ESTAT2_Msk (0x00000400UL) +#define R_INTC_IM33_EREISR1_M11ESTAT2_Pos (10UL) +#define R_INTC_IM33_EREISR1_M11ESTAT3_Msk (0x00000800UL) +#define R_INTC_IM33_EREISR1_M11ESTAT3_Pos (11UL) +#define R_INTC_IM33_EREISR1_M11ESTAT4_Msk (0x00001000UL) +#define R_INTC_IM33_EREISR1_M11ESTAT4_Pos (12UL) +#define R_INTC_IM33_EREISR1_M11ESTAT5_Msk (0x00002000UL) +#define R_INTC_IM33_EREISR1_M11ESTAT5_Pos (13UL) +#define R_INTC_IM33_EREISR1_M11ESTAT6_Msk (0x00004000UL) +#define R_INTC_IM33_EREISR1_M11ESTAT6_Pos (14UL) +#define R_INTC_IM33_EREISR1_M11ESTAT7_Msk (0x00008000UL) +#define R_INTC_IM33_EREISR1_M11ESTAT7_Pos (15UL) +#define R_INTC_IM33_EREISR2_A02ESTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_EREISR2_A02ESTAT0_Pos (0UL) +#define R_INTC_IM33_EREISR2_A02ESTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_EREISR2_A02ESTAT1_Pos (1UL) +#define R_INTC_IM33_EREISR2_A02ESTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_EREISR2_A02ESTAT2_Pos (2UL) +#define R_INTC_IM33_EREISR2_A02ESTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_EREISR2_A02ESTAT3_Pos (3UL) +#define R_INTC_IM33_EREISR2_A02ESTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_EREISR2_A02ESTAT4_Pos (4UL) +#define R_INTC_IM33_EREISR2_A02ESTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_EREISR2_A02ESTAT5_Pos (5UL) +#define R_INTC_IM33_EREISR2_A02ESTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_EREISR2_A02ESTAT6_Pos (6UL) +#define R_INTC_IM33_EREISR2_A02ESTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_EREISR2_A02ESTAT7_Pos (7UL) +#define R_INTC_IM33_EREISR2_A12ESTAT0_Msk (0x00000100UL) +#define R_INTC_IM33_EREISR2_A12ESTAT0_Pos (8UL) +#define R_INTC_IM33_EREISR2_A12ESTAT1_Msk (0x00000200UL) +#define R_INTC_IM33_EREISR2_A12ESTAT1_Pos (9UL) +#define R_INTC_IM33_EREISR2_A12ESTAT2_Msk (0x00000400UL) +#define R_INTC_IM33_EREISR2_A12ESTAT2_Pos (10UL) +#define R_INTC_IM33_EREISR2_A12ESTAT3_Msk (0x00000800UL) +#define R_INTC_IM33_EREISR2_A12ESTAT3_Pos (11UL) +#define R_INTC_IM33_EREISR2_A12ESTAT4_Msk (0x00001000UL) +#define R_INTC_IM33_EREISR2_A12ESTAT4_Pos (12UL) +#define R_INTC_IM33_EREISR2_A12ESTAT5_Msk (0x00002000UL) +#define R_INTC_IM33_EREISR2_A12ESTAT5_Pos (13UL) +#define R_INTC_IM33_EREISR2_A12ESTAT6_Msk (0x00004000UL) +#define R_INTC_IM33_EREISR2_A12ESTAT6_Pos (14UL) +#define R_INTC_IM33_EREISR2_A12ESTAT7_Msk (0x00008000UL) +#define R_INTC_IM33_EREISR2_A12ESTAT7_Pos (15UL) +#define R_INTC_IM33_EREISR3_M02ESTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_EREISR3_M02ESTAT0_Pos (0UL) +#define R_INTC_IM33_EREISR3_M02ESTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_EREISR3_M02ESTAT1_Pos (1UL) +#define R_INTC_IM33_EREISR3_M02ESTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_EREISR3_M02ESTAT2_Pos (2UL) +#define R_INTC_IM33_EREISR3_M02ESTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_EREISR3_M02ESTAT3_Pos (3UL) +#define R_INTC_IM33_EREISR3_M02ESTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_EREISR3_M02ESTAT4_Pos (4UL) +#define R_INTC_IM33_EREISR3_M02ESTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_EREISR3_M02ESTAT5_Pos (5UL) +#define R_INTC_IM33_EREISR3_M02ESTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_EREISR3_M02ESTAT6_Pos (6UL) +#define R_INTC_IM33_EREISR3_M02ESTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_EREISR3_M02ESTAT7_Pos (7UL) +#define R_INTC_IM33_EREISR3_M12ESTAT0_Msk (0x00000100UL) +#define R_INTC_IM33_EREISR3_M12ESTAT0_Pos (8UL) +#define R_INTC_IM33_EREISR3_M12ESTAT1_Msk (0x00000200UL) +#define R_INTC_IM33_EREISR3_M12ESTAT1_Pos (9UL) +#define R_INTC_IM33_EREISR3_M12ESTAT2_Msk (0x00000400UL) +#define R_INTC_IM33_EREISR3_M12ESTAT2_Pos (10UL) +#define R_INTC_IM33_EREISR3_M12ESTAT3_Msk (0x00000800UL) +#define R_INTC_IM33_EREISR3_M12ESTAT3_Pos (11UL) +#define R_INTC_IM33_EREISR3_M12ESTAT4_Msk (0x00001000UL) +#define R_INTC_IM33_EREISR3_M12ESTAT4_Pos (12UL) +#define R_INTC_IM33_EREISR3_M12ESTAT5_Msk (0x00002000UL) +#define R_INTC_IM33_EREISR3_M12ESTAT5_Pos (13UL) +#define R_INTC_IM33_EREISR3_M12ESTAT6_Msk (0x00004000UL) +#define R_INTC_IM33_EREISR3_M12ESTAT6_Pos (14UL) +#define R_INTC_IM33_EREISR3_M12ESTAT7_Msk (0x00008000UL) +#define R_INTC_IM33_EREISR3_M12ESTAT7_Pos (15UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT0_Pos (0UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT1_Pos (1UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT2_Pos (2UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT3_Pos (3UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT4_Pos (4UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT5_Pos (5UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT6_Pos (6UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_EREISR4_A0OFSTAT7_Pos (7UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT0_Msk (0x00000100UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT0_Pos (8UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT1_Msk (0x00000200UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT1_Pos (9UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT2_Msk (0x00000400UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT2_Pos (10UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT3_Msk (0x00000800UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT3_Pos (11UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT4_Msk (0x00001000UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT4_Pos (12UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT5_Msk (0x00002000UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT5_Pos (13UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT6_Msk (0x00004000UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT6_Pos (14UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT7_Msk (0x00008000UL) +#define R_INTC_IM33_EREISR4_A1OFSTAT7_Pos (15UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT0_Msk (0x00000001UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT0_Pos (0UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT1_Msk (0x00000002UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT1_Pos (1UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT2_Msk (0x00000004UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT2_Pos (2UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT3_Msk (0x00000008UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT3_Pos (3UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT4_Msk (0x00000010UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT4_Pos (4UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT5_Msk (0x00000020UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT5_Pos (5UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT6_Msk (0x00000040UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT6_Pos (6UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT7_Msk (0x00000080UL) +#define R_INTC_IM33_EREISR5_M0OFSTAT7_Pos (7UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT0_Msk (0x00000100UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT0_Pos (8UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT1_Msk (0x00000200UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT1_Pos (9UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT2_Msk (0x00000400UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT2_Pos (10UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT3_Msk (0x00000800UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT3_Pos (11UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT4_Msk (0x00001000UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT4_Pos (12UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT5_Msk (0x00002000UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT5_Pos (13UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT6_Msk (0x00004000UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT6_Pos (14UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT7_Msk (0x00008000UL) +#define R_INTC_IM33_EREISR5_M1OFSTAT7_Pos (15UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL0_Msk (0x00000001UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL0_Pos (0UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL1_Msk (0x00000002UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL1_Pos (1UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL2_Msk (0x00000004UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL2_Pos (2UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL3_Msk (0x00000008UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL3_Pos (3UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL4_Msk (0x00000010UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL4_Pos (4UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL5_Msk (0x00000020UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL5_Pos (5UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL6_Msk (0x00000040UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL6_Pos (6UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL7_Msk (0x00000080UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL7_Pos (7UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL8_Msk (0x00000100UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL8_Pos (8UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL9_Msk (0x00000200UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL9_Pos (9UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL10_Msk (0x00000400UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL10_Pos (10UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL11_Msk (0x00000800UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL11_Pos (11UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL12_Msk (0x00001000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL12_Pos (12UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL13_Msk (0x00002000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL13_Pos (13UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL14_Msk (0x00004000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL14_Pos (14UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL15_Msk (0x00008000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL15_Pos (15UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL16_Msk (0x00010000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL16_Pos (16UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL17_Msk (0x00020000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL17_Pos (17UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL18_Msk (0x00040000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL18_Pos (18UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL19_Msk (0x00080000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL19_Pos (19UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL20_Msk (0x00100000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL20_Pos (20UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL21_Msk (0x00200000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL21_Pos (21UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL22_Msk (0x00400000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL22_Pos (22UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL23_Msk (0x00800000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL23_Pos (23UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL24_Msk (0x01000000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL24_Pos (24UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL25_Msk (0x02000000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL25_Pos (25UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL26_Msk (0x04000000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL26_Pos (26UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL27_Msk (0x08000000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL27_Pos (27UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL28_Msk (0x10000000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL28_Pos (28UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL29_Msk (0x20000000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL29_Pos (29UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL30_Msk (0x40000000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL30_Pos (30UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL31_Msk (0x80000000UL) +#define R_INTC_IM33_INTPMSEL0_PMINTSEL31_Pos (31UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL32_Msk (0x00000001UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL32_Pos (0UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL33_Msk (0x00000002UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL33_Pos (1UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL34_Msk (0x00000004UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL34_Pos (2UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL35_Msk (0x00000008UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL35_Pos (3UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL36_Msk (0x00000010UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL36_Pos (4UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL37_Msk (0x00000020UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL37_Pos (5UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL38_Msk (0x00000040UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL38_Pos (6UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL39_Msk (0x00000080UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL39_Pos (7UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL40_Msk (0x00000100UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL40_Pos (8UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL41_Msk (0x00000200UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL41_Pos (9UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL42_Msk (0x00000400UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL42_Pos (10UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL43_Msk (0x00000800UL) +#define R_INTC_IM33_INTPMSEL1_PMINTSEL43_Pos (11UL) + +#endif /* INTC_IM33_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/mhu_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/mhu_iobitmask.h new file mode 100644 index 00000000..70af45d6 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/mhu_iobitmask.h @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : mhu_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for mhu. + *********************************************************************************************************************/ + +#ifndef MHU_IOBITMASK_H +#define MHU_IOBITMASK_H + +#define R_MHU0_MSG_INT_STSn_STAT_Msk (0x00000001UL) +#define R_MHU0_MSG_INT_STSn_STAT_Pos (0UL) +#define R_MHU0_MSG_INT_SETn_SET_Msk (0x00000001UL) +#define R_MHU0_MSG_INT_SETn_SET_Pos (0UL) +#define R_MHU0_MSG_INT_CLRn_CLEAR_Msk (0x00000001UL) +#define R_MHU0_MSG_INT_CLRn_CLEAR_Pos (0UL) +#define R_MHU0_RSP_INT_STSn_STAT_Msk (0x00000001UL) +#define R_MHU0_RSP_INT_STSn_STAT_Pos (0UL) +#define R_MHU0_RSP_INT_SETn_SET_Msk (0x00000001UL) +#define R_MHU0_RSP_INT_SETn_SET_Pos (0UL) +#define R_MHU0_RSP_INT_CLRn_CLEAR_Msk (0x00000001UL) +#define R_MHU0_RSP_INT_CLRn_CLEAR_Pos (0UL) +#define R_MHU0_SW_INT_STSn_STAT_Msk (0x00000001UL) +#define R_MHU0_SW_INT_STSn_STAT_Pos (0UL) +#define R_MHU0_SW_INT_SETn_SET_Msk (0x00000001UL) +#define R_MHU0_SW_INT_SETn_SET_Pos (0UL) +#define R_MHU0_SW_INT_CLRn_CLEAR_Msk (0x00000001UL) +#define R_MHU0_SW_INT_CLRn_CLEAR_Pos (0UL) + +#endif /* MHU_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/poeg_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/poeg_iobitmask.h new file mode 100644 index 00000000..274cfb0e --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/poeg_iobitmask.h @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : poeg_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for poeg. + *********************************************************************************************************************/ + +#ifndef POEG_IOBITMASK_H +#define POEG_IOBITMASK_H + +#define R_POEG_POEGGn_PIDF_Msk (0x00000001UL) +#define R_POEG_POEGGn_PIDF_Pos (0UL) +#define R_POEG_POEGGn_IOCF_Msk (0x00000002UL) +#define R_POEG_POEGGn_IOCF_Pos (1UL) +#define R_POEG_POEGGn_SSF_Msk (0x00000008UL) +#define R_POEG_POEGGn_SSF_Pos (3UL) +#define R_POEG_POEGGn_PIDE_Msk (0x00000010UL) +#define R_POEG_POEGGn_PIDE_Pos (4UL) +#define R_POEG_POEGGn_IOCE_Msk (0x00000020UL) +#define R_POEG_POEGGn_IOCE_Pos (5UL) +#define R_POEG_POEGGn_ST_Msk (0x00010000UL) +#define R_POEG_POEGGn_ST_Pos (16UL) +#define R_POEG_POEGGn_INV_Msk (0x10000000UL) +#define R_POEG_POEGGn_INV_Pos (28UL) +#define R_POEG_POEGGn_NFEN_Msk (0x20000000UL) +#define R_POEG_POEGGn_NFEN_Pos (29UL) +#define R_POEG_POEGGn_NFCS_Msk (0xC0000000UL) +#define R_POEG_POEGGn_NFCS_Pos (30UL) + +#endif /* POEG_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/riic_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/riic_iobitmask.h new file mode 100644 index 00000000..b0bfe1bb --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/riic_iobitmask.h @@ -0,0 +1,342 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : riic_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for riic. + *********************************************************************************************************************/ + +#ifndef RIIC_IOBITMASK_H +#define RIIC_IOBITMASK_H + +#define R_RIIC_ICCR1_SDAI_Msk (0x01UL) +#define R_RIIC_ICCR1_SDAI_Pos (0UL) +#define R_RIIC_ICCR1_SCLI_Msk (0x02UL) +#define R_RIIC_ICCR1_SCLI_Pos (1UL) +#define R_RIIC_ICCR1_SDAO_Msk (0x04UL) +#define R_RIIC_ICCR1_SDAO_Pos (2UL) +#define R_RIIC_ICCR1_SCLO_Msk (0x08UL) +#define R_RIIC_ICCR1_SCLO_Pos (3UL) +#define R_RIIC_ICCR1_SOWP_Msk (0x10UL) +#define R_RIIC_ICCR1_SOWP_Pos (4UL) +#define R_RIIC_ICCR1_CLO_Msk (0x20UL) +#define R_RIIC_ICCR1_CLO_Pos (5UL) +#define R_RIIC_ICCR1_IICRST_Msk (0x40UL) +#define R_RIIC_ICCR1_IICRST_Pos (6UL) +#define R_RIIC_ICCR1_ICE_Msk (0x80UL) +#define R_RIIC_ICCR1_ICE_Pos (7UL) +#define R_RIIC_ICCR2_ST_Msk (0x02UL) +#define R_RIIC_ICCR2_ST_Pos (1UL) +#define R_RIIC_ICCR2_RS_Msk (0x04UL) +#define R_RIIC_ICCR2_RS_Pos (2UL) +#define R_RIIC_ICCR2_SP_Msk (0x08UL) +#define R_RIIC_ICCR2_SP_Pos (3UL) +#define R_RIIC_ICCR2_TRS_Msk (0x20UL) +#define R_RIIC_ICCR2_TRS_Pos (5UL) +#define R_RIIC_ICCR2_MST_Msk (0x40UL) +#define R_RIIC_ICCR2_MST_Pos (6UL) +#define R_RIIC_ICCR2_BBSY_Msk (0x80UL) +#define R_RIIC_ICCR2_BBSY_Pos (7UL) +#define R_RIIC_ICMR1_BC_Msk (0x07UL) +#define R_RIIC_ICMR1_BC_Pos (0UL) +#define R_RIIC_ICMR1_BCWP_Msk (0x08UL) +#define R_RIIC_ICMR1_BCWP_Pos (3UL) +#define R_RIIC_ICMR1_CKS_Msk (0x70UL) +#define R_RIIC_ICMR1_CKS_Pos (4UL) +#define R_RIIC_ICMR2_TMOS_Msk (0x01UL) +#define R_RIIC_ICMR2_TMOS_Pos (0UL) +#define R_RIIC_ICMR2_TMOL_Msk (0x02UL) +#define R_RIIC_ICMR2_TMOL_Pos (1UL) +#define R_RIIC_ICMR2_TMOH_Msk (0x04UL) +#define R_RIIC_ICMR2_TMOH_Pos (2UL) +#define R_RIIC_ICMR2_SDDL_Msk (0x70UL) +#define R_RIIC_ICMR2_SDDL_Pos (4UL) +#define R_RIIC_ICMR2_DLCS_Msk (0x80UL) +#define R_RIIC_ICMR2_DLCS_Pos (7UL) +#define R_RIIC_ICMR3_NF_Msk (0x03UL) +#define R_RIIC_ICMR3_NF_Pos (0UL) +#define R_RIIC_ICMR3_ACKBR_Msk (0x04UL) +#define R_RIIC_ICMR3_ACKBR_Pos (2UL) +#define R_RIIC_ICMR3_ACKBT_Msk (0x08UL) +#define R_RIIC_ICMR3_ACKBT_Pos (3UL) +#define R_RIIC_ICMR3_ACKWP_Msk (0x10UL) +#define R_RIIC_ICMR3_ACKWP_Pos (4UL) +#define R_RIIC_ICMR3_RDRFS_Msk (0x20UL) +#define R_RIIC_ICMR3_RDRFS_Pos (5UL) +#define R_RIIC_ICMR3_WAIT_Msk (0x40UL) +#define R_RIIC_ICMR3_WAIT_Pos (6UL) +#define R_RIIC_ICMR3_SMBE_Msk (0x80UL) +#define R_RIIC_ICMR3_SMBE_Pos (7UL) +#define R_RIIC_ICFER_TMOE_Msk (0x01UL) +#define R_RIIC_ICFER_TMOE_Pos (0UL) +#define R_RIIC_ICFER_MALE_Msk (0x02UL) +#define R_RIIC_ICFER_MALE_Pos (1UL) +#define R_RIIC_ICFER_NALE_Msk (0x04UL) +#define R_RIIC_ICFER_NALE_Pos (2UL) +#define R_RIIC_ICFER_SALE_Msk (0x08UL) +#define R_RIIC_ICFER_SALE_Pos (3UL) +#define R_RIIC_ICFER_NACKE_Msk (0x10UL) +#define R_RIIC_ICFER_NACKE_Pos (4UL) +#define R_RIIC_ICFER_NFE_Msk (0x20UL) +#define R_RIIC_ICFER_NFE_Pos (5UL) +#define R_RIIC_ICFER_SCLE_Msk (0x40UL) +#define R_RIIC_ICFER_SCLE_Pos (6UL) +#define R_RIIC_ICFER_FMPE_Msk (0x80UL) +#define R_RIIC_ICFER_FMPE_Pos (7UL) +#define R_RIIC_ICSER_SAR0_Msk (0x01UL) +#define R_RIIC_ICSER_SAR0_Pos (0UL) +#define R_RIIC_ICSER_SAR1_Msk (0x02UL) +#define R_RIIC_ICSER_SAR1_Pos (1UL) +#define R_RIIC_ICSER_SAR2_Msk (0x04UL) +#define R_RIIC_ICSER_SAR2_Pos (2UL) +#define R_RIIC_ICSER_GCE_Msk (0x08UL) +#define R_RIIC_ICSER_GCE_Pos (3UL) +#define R_RIIC_ICSER_DIDE_Msk (0x20UL) +#define R_RIIC_ICSER_DIDE_Pos (5UL) +#define R_RIIC_ICSER_HOAE_Msk (0x80UL) +#define R_RIIC_ICSER_HOAE_Pos (7UL) +#define R_RIIC_ICIER_TMOIE_Msk (0x01UL) +#define R_RIIC_ICIER_TMOIE_Pos (0UL) +#define R_RIIC_ICIER_ALIE_Msk (0x02UL) +#define R_RIIC_ICIER_ALIE_Pos (1UL) +#define R_RIIC_ICIER_STIE_Msk (0x04UL) +#define R_RIIC_ICIER_STIE_Pos (2UL) +#define R_RIIC_ICIER_SPIE_Msk (0x08UL) +#define R_RIIC_ICIER_SPIE_Pos (3UL) +#define R_RIIC_ICIER_NAKIE_Msk (0x10UL) +#define R_RIIC_ICIER_NAKIE_Pos (4UL) +#define R_RIIC_ICIER_RIE_Msk (0x20UL) +#define R_RIIC_ICIER_RIE_Pos (5UL) +#define R_RIIC_ICIER_TEIE_Msk (0x40UL) +#define R_RIIC_ICIER_TEIE_Pos (6UL) +#define R_RIIC_ICIER_TIE_Msk (0x80UL) +#define R_RIIC_ICIER_TIE_Pos (7UL) +#define R_RIIC_ICSR1_AAS0_Msk (0x01UL) +#define R_RIIC_ICSR1_AAS0_Pos (0UL) +#define R_RIIC_ICSR1_AAS1_Msk (0x02UL) +#define R_RIIC_ICSR1_AAS1_Pos (1UL) +#define R_RIIC_ICSR1_AAS2_Msk (0x04UL) +#define R_RIIC_ICSR1_AAS2_Pos (2UL) +#define R_RIIC_ICSR1_GCA_Msk (0x08UL) +#define R_RIIC_ICSR1_GCA_Pos (3UL) +#define R_RIIC_ICSR1_DID_Msk (0x20UL) +#define R_RIIC_ICSR1_DID_Pos (5UL) +#define R_RIIC_ICSR1_HOA_Msk (0x80UL) +#define R_RIIC_ICSR1_HOA_Pos (7UL) +#define R_RIIC_ICSR2_TMOF_Msk (0x01UL) +#define R_RIIC_ICSR2_TMOF_Pos (0UL) +#define R_RIIC_ICSR2_AL_Msk (0x02UL) +#define R_RIIC_ICSR2_AL_Pos (1UL) +#define R_RIIC_ICSR2_START_Msk (0x04UL) +#define R_RIIC_ICSR2_START_Pos (2UL) +#define R_RIIC_ICSR2_STOP_Msk (0x08UL) +#define R_RIIC_ICSR2_STOP_Pos (3UL) +#define R_RIIC_ICSR2_NACKF_Msk (0x10UL) +#define R_RIIC_ICSR2_NACKF_Pos (4UL) +#define R_RIIC_ICSR2_RDRF_Msk (0x20UL) +#define R_RIIC_ICSR2_RDRF_Pos (5UL) +#define R_RIIC_ICSR2_TEND_Msk (0x40UL) +#define R_RIIC_ICSR2_TEND_Pos (6UL) +#define R_RIIC_ICSR2_TDRE_Msk (0x80UL) +#define R_RIIC_ICSR2_TDRE_Pos (7UL) +#define R_RIIC_ICSAR0_SVA0_Msk (0x01UL) +#define R_RIIC_ICSAR0_SVA0_Pos (0UL) +#define R_RIIC_ICSAR0_SVA_Msk (0xFEUL) +#define R_RIIC_ICSAR0_SVA_Pos (1UL) +#define R_RIIC_ICSARU0_FS_Msk (0x01UL) +#define R_RIIC_ICSARU0_FS_Pos (0UL) +#define R_RIIC_ICSARU0_SVA_Msk (0x06UL) +#define R_RIIC_ICSARU0_SVA_Pos (1UL) +#define R_RIIC_ICSAR1_SVA0_Msk (0x01UL) +#define R_RIIC_ICSAR1_SVA0_Pos (0UL) +#define R_RIIC_ICSAR1_SVA_Msk (0xFEUL) +#define R_RIIC_ICSAR1_SVA_Pos (1UL) +#define R_RIIC_ICSARU1_FS_Msk (0x01UL) +#define R_RIIC_ICSARU1_FS_Pos (0UL) +#define R_RIIC_ICSARU1_SVA_Msk (0x06UL) +#define R_RIIC_ICSARU1_SVA_Pos (1UL) +#define R_RIIC_ICSAR2_SVA0_Msk (0x01UL) +#define R_RIIC_ICSAR2_SVA0_Pos (0UL) +#define R_RIIC_ICSAR2_SVA_Msk (0xFEUL) +#define R_RIIC_ICSAR2_SVA_Pos (1UL) +#define R_RIIC_ICSARU2_FS_Msk (0x01UL) +#define R_RIIC_ICSARU2_FS_Pos (0UL) +#define R_RIIC_ICSARU2_SVA_Msk (0x06UL) +#define R_RIIC_ICSARU2_SVA_Pos (1UL) +#define R_RIIC_ICBRL_BRL_Msk (0x1FUL) +#define R_RIIC_ICBRL_BRL_Pos (0UL) +#define R_RIIC_ICBRH_BRH_Msk (0x1FUL) +#define R_RIIC_ICBRH_BRH_Pos (0UL) +#define R_RIIC_ICDRT_DRT_Msk (0xFFUL) +#define R_RIIC_ICDRT_DRT_Pos (0UL) +#define R_RIIC_ICDRR_DRR_Msk (0xFFUL) +#define R_RIIC_ICDRR_DRR_Pos (0UL) + +#define R_RIIC0_ICCR1_SDAI_Msk R_RIIC_ICCR1_SDAI_Msk +#define R_RIIC0_ICCR1_SDAI_Pos R_RIIC_ICCR1_SDAI_Pos +#define R_RIIC0_ICCR1_SCLI_Msk R_RIIC_ICCR1_SCLI_Msk +#define R_RIIC0_ICCR1_SCLI_Pos R_RIIC_ICCR1_SCLI_Pos +#define R_RIIC0_ICCR1_SDAO_Msk R_RIIC_ICCR1_SDAO_Msk +#define R_RIIC0_ICCR1_SDAO_Pos R_RIIC_ICCR1_SDAO_Pos +#define R_RIIC0_ICCR1_SCLO_Msk R_RIIC_ICCR1_SCLO_Msk +#define R_RIIC0_ICCR1_SCLO_Pos R_RIIC_ICCR1_SCLO_Pos +#define R_RIIC0_ICCR1_SOWP_Msk R_RIIC_ICCR1_SOWP_Msk +#define R_RIIC0_ICCR1_SOWP_Pos R_RIIC_ICCR1_SOWP_Pos +#define R_RIIC0_ICCR1_CLO_Msk R_RIIC_ICCR1_CLO_Msk +#define R_RIIC0_ICCR1_CLO_Pos R_RIIC_ICCR1_CLO_Pos +#define R_RIIC0_ICCR1_IICRST_Msk R_RIIC_ICCR1_IICRST_Msk +#define R_RIIC0_ICCR1_IICRST_Pos R_RIIC_ICCR1_IICRST_Pos +#define R_RIIC0_ICCR1_ICE_Msk R_RIIC_ICCR1_ICE_Msk +#define R_RIIC0_ICCR1_ICE_Pos R_RIIC_ICCR1_ICE_Pos +#define R_RIIC0_ICCR2_ST_Msk R_RIIC_ICCR2_ST_Msk +#define R_RIIC0_ICCR2_ST_Pos R_RIIC_ICCR2_ST_Pos +#define R_RIIC0_ICCR2_RS_Msk R_RIIC_ICCR2_RS_Msk +#define R_RIIC0_ICCR2_RS_Pos R_RIIC_ICCR2_RS_Pos +#define R_RIIC0_ICCR2_SP_Msk R_RIIC_ICCR2_SP_Msk +#define R_RIIC0_ICCR2_SP_Pos R_RIIC_ICCR2_SP_Pos +#define R_RIIC0_ICCR2_TRS_Msk R_RIIC_ICCR2_TRS_Msk +#define R_RIIC0_ICCR2_TRS_Pos R_RIIC_ICCR2_TRS_Pos +#define R_RIIC0_ICCR2_MST_Msk R_RIIC_ICCR2_MST_Msk +#define R_RIIC0_ICCR2_MST_Pos R_RIIC_ICCR2_MST_Pos +#define R_RIIC0_ICCR2_BBSY_Msk R_RIIC_ICCR2_BBSY_Msk +#define R_RIIC0_ICCR2_BBSY_Pos R_RIIC_ICCR2_BBSY_Pos +#define R_RIIC0_ICMR1_BC_Msk R_RIIC_ICMR1_BC_Msk +#define R_RIIC0_ICMR1_BC_Pos R_RIIC_ICMR1_BC_Pos +#define R_RIIC0_ICMR1_BCWP_Msk R_RIIC_ICMR1_BCWP_Msk +#define R_RIIC0_ICMR1_BCWP_Pos R_RIIC_ICMR1_BCWP_Pos +#define R_RIIC0_ICMR1_CKS_Msk R_RIIC_ICMR1_CKS_Msk +#define R_RIIC0_ICMR1_CKS_Pos R_RIIC_ICMR1_CKS_Pos +#define R_RIIC0_ICMR2_TMOS_Msk R_RIIC_ICMR2_TMOS_Msk +#define R_RIIC0_ICMR2_TMOS_Pos R_RIIC_ICMR2_TMOS_Pos +#define R_RIIC0_ICMR2_TMOL_Msk R_RIIC_ICMR2_TMOL_Msk +#define R_RIIC0_ICMR2_TMOL_Pos R_RIIC_ICMR2_TMOL_Pos +#define R_RIIC0_ICMR2_TMOH_Msk R_RIIC_ICMR2_TMOH_Msk +#define R_RIIC0_ICMR2_TMOH_Pos R_RIIC_ICMR2_TMOH_Pos +#define R_RIIC0_ICMR2_SDDL_Msk R_RIIC_ICMR2_SDDL_Msk +#define R_RIIC0_ICMR2_SDDL_Pos R_RIIC_ICMR2_SDDL_Pos +#define R_RIIC0_ICMR2_DLCS_Msk R_RIIC_ICMR2_DLCS_Msk +#define R_RIIC0_ICMR2_DLCS_Pos R_RIIC_ICMR2_DLCS_Pos +#define R_RIIC0_ICMR3_NF_Msk R_RIIC_ICMR3_NF_Msk +#define R_RIIC0_ICMR3_NF_Pos R_RIIC_ICMR3_NF_Pos +#define R_RIIC0_ICMR3_ACKBR_Msk R_RIIC_ICMR3_ACKBR_Msk +#define R_RIIC0_ICMR3_ACKBR_Pos R_RIIC_ICMR3_ACKBR_Pos +#define R_RIIC0_ICMR3_ACKBT_Msk R_RIIC_ICMR3_ACKBT_Msk +#define R_RIIC0_ICMR3_ACKBT_Pos R_RIIC_ICMR3_ACKBT_Pos +#define R_RIIC0_ICMR3_ACKWP_Msk R_RIIC_ICMR3_ACKWP_Msk +#define R_RIIC0_ICMR3_ACKWP_Pos R_RIIC_ICMR3_ACKWP_Pos +#define R_RIIC0_ICMR3_RDRFS_Msk R_RIIC_ICMR3_RDRFS_Msk +#define R_RIIC0_ICMR3_RDRFS_Pos R_RIIC_ICMR3_RDRFS_Pos +#define R_RIIC0_ICMR3_WAIT_Msk R_RIIC_ICMR3_WAIT_Msk +#define R_RIIC0_ICMR3_WAIT_Pos R_RIIC_ICMR3_WAIT_Pos +#define R_RIIC0_ICMR3_SMBE_Msk R_RIIC_ICMR3_SMBE_Msk +#define R_RIIC0_ICMR3_SMBE_Pos R_RIIC_ICMR3_SMBE_Pos +#define R_RIIC0_ICFER_TMOE_Msk R_RIIC_ICFER_TMOE_Msk +#define R_RIIC0_ICFER_TMOE_Pos R_RIIC_ICFER_TMOE_Pos +#define R_RIIC0_ICFER_MALE_Msk R_RIIC_ICFER_MALE_Msk +#define R_RIIC0_ICFER_MALE_Pos R_RIIC_ICFER_MALE_Pos +#define R_RIIC0_ICFER_NALE_Msk R_RIIC_ICFER_NALE_Msk +#define R_RIIC0_ICFER_NALE_Pos R_RIIC_ICFER_NALE_Pos +#define R_RIIC0_ICFER_SALE_Msk R_RIIC_ICFER_SALE_Msk +#define R_RIIC0_ICFER_SALE_Pos R_RIIC_ICFER_SALE_Pos +#define R_RIIC0_ICFER_NACKE_Msk R_RIIC_ICFER_NACKE_Msk +#define R_RIIC0_ICFER_NACKE_Pos R_RIIC_ICFER_NACKE_Pos +#define R_RIIC0_ICFER_NFE_Msk R_RIIC_ICFER_NFE_Msk +#define R_RIIC0_ICFER_NFE_Pos R_RIIC_ICFER_NFE_Pos +#define R_RIIC0_ICFER_SCLE_Msk R_RIIC_ICFER_SCLE_Msk +#define R_RIIC0_ICFER_SCLE_Pos R_RIIC_ICFER_SCLE_Pos +#define R_RIIC0_ICFER_FMPE_Msk R_RIIC_ICFER_FMPE_Msk +#define R_RIIC0_ICFER_FMPE_Pos R_RIIC_ICFER_FMPE_Pos +#define R_RIIC0_ICSER_SAR0_Msk R_RIIC_ICSER_SAR0_Msk +#define R_RIIC0_ICSER_SAR0_Pos R_RIIC_ICSER_SAR0_Pos +#define R_RIIC0_ICSER_SAR1_Msk R_RIIC_ICSER_SAR1_Msk +#define R_RIIC0_ICSER_SAR1_Pos R_RIIC_ICSER_SAR1_Pos +#define R_RIIC0_ICSER_SAR2_Msk R_RIIC_ICSER_SAR2_Msk +#define R_RIIC0_ICSER_SAR2_Pos R_RIIC_ICSER_SAR2_Pos +#define R_RIIC0_ICSER_GCE_Msk R_RIIC_ICSER_GCE_Msk +#define R_RIIC0_ICSER_GCE_Pos R_RIIC_ICSER_GCE_Pos +#define R_RIIC0_ICSER_DIDE_Msk R_RIIC_ICSER_DIDE_Msk +#define R_RIIC0_ICSER_DIDE_Pos R_RIIC_ICSER_DIDE_Pos +#define R_RIIC0_ICSER_HOAE_Msk R_RIIC_ICSER_HOAE_Msk +#define R_RIIC0_ICSER_HOAE_Pos R_RIIC_ICSER_HOAE_Pos +#define R_RIIC0_ICIER_TMOIE_Msk R_RIIC_ICIER_TMOIE_Msk +#define R_RIIC0_ICIER_TMOIE_Pos R_RIIC_ICIER_TMOIE_Pos +#define R_RIIC0_ICIER_ALIE_Msk R_RIIC_ICIER_ALIE_Msk +#define R_RIIC0_ICIER_ALIE_Pos R_RIIC_ICIER_ALIE_Pos +#define R_RIIC0_ICIER_STIE_Msk R_RIIC_ICIER_STIE_Msk +#define R_RIIC0_ICIER_STIE_Pos R_RIIC_ICIER_STIE_Pos +#define R_RIIC0_ICIER_SPIE_Msk R_RIIC_ICIER_SPIE_Msk +#define R_RIIC0_ICIER_SPIE_Pos R_RIIC_ICIER_SPIE_Pos +#define R_RIIC0_ICIER_NAKIE_Msk R_RIIC_ICIER_NAKIE_Msk +#define R_RIIC0_ICIER_NAKIE_Pos R_RIIC_ICIER_NAKIE_Pos +#define R_RIIC0_ICIER_RIE_Msk R_RIIC_ICIER_RIE_Msk +#define R_RIIC0_ICIER_RIE_Pos R_RIIC_ICIER_RIE_Pos +#define R_RIIC0_ICIER_TEIE_Msk R_RIIC_ICIER_TEIE_Msk +#define R_RIIC0_ICIER_TEIE_Pos R_RIIC_ICIER_TEIE_Pos +#define R_RIIC0_ICIER_TIE_Msk R_RIIC_ICIER_TIE_Msk +#define R_RIIC0_ICIER_TIE_Pos R_RIIC_ICIER_TIE_Pos +#define R_RIIC0_ICSR1_AAS0_Msk R_RIIC_ICSR1_AAS0_Msk +#define R_RIIC0_ICSR1_AAS0_Pos R_RIIC_ICSR1_AAS0_Pos +#define R_RIIC0_ICSR1_AAS1_Msk R_RIIC_ICSR1_AAS1_Msk +#define R_RIIC0_ICSR1_AAS1_Pos R_RIIC_ICSR1_AAS1_Pos +#define R_RIIC0_ICSR1_AAS2_Msk R_RIIC_ICSR1_AAS2_Msk +#define R_RIIC0_ICSR1_AAS2_Pos R_RIIC_ICSR1_AAS2_Pos +#define R_RIIC0_ICSR1_GCA_Msk R_RIIC_ICSR1_GCA_Msk +#define R_RIIC0_ICSR1_GCA_Pos R_RIIC_ICSR1_GCA_Pos +#define R_RIIC0_ICSR1_DID_Msk R_RIIC_ICSR1_DID_Msk +#define R_RIIC0_ICSR1_DID_Pos R_RIIC_ICSR1_DID_Pos +#define R_RIIC0_ICSR1_HOA_Msk R_RIIC_ICSR1_HOA_Msk +#define R_RIIC0_ICSR1_HOA_Pos R_RIIC_ICSR1_HOA_Pos +#define R_RIIC0_ICSR2_TMOF_Msk R_RIIC_ICSR2_TMOF_Msk +#define R_RIIC0_ICSR2_TMOF_Pos R_RIIC_ICSR2_TMOF_Pos +#define R_RIIC0_ICSR2_AL_Msk R_RIIC_ICSR2_AL_Msk +#define R_RIIC0_ICSR2_AL_Pos R_RIIC_ICSR2_AL_Pos +#define R_RIIC0_ICSR2_START_Msk R_RIIC_ICSR2_START_Msk +#define R_RIIC0_ICSR2_START_Pos R_RIIC_ICSR2_START_Pos +#define R_RIIC0_ICSR2_STOP_Msk R_RIIC_ICSR2_STOP_Msk +#define R_RIIC0_ICSR2_STOP_Pos R_RIIC_ICSR2_STOP_Pos +#define R_RIIC0_ICSR2_NACKF_Msk R_RIIC_ICSR2_NACKF_Msk +#define R_RIIC0_ICSR2_NACKF_Pos R_RIIC_ICSR2_NACKF_Pos +#define R_RIIC0_ICSR2_RDRF_Msk R_RIIC_ICSR2_RDRF_Msk +#define R_RIIC0_ICSR2_RDRF_Pos R_RIIC_ICSR2_RDRF_Pos +#define R_RIIC0_ICSR2_TEND_Msk R_RIIC_ICSR2_TEND_Msk +#define R_RIIC0_ICSR2_TEND_Pos R_RIIC_ICSR2_TEND_Pos +#define R_RIIC0_ICSR2_TDRE_Msk R_RIIC_ICSR2_TDRE_Msk +#define R_RIIC0_ICSR2_TDRE_Pos R_RIIC_ICSR2_TDRE_Pos +#define R_RIIC0_ICSAR0_SVA0_Msk R_RIIC_ICSAR0_SVA0_Msk +#define R_RIIC0_ICSAR0_SVA0_Pos R_RIIC_ICSAR0_SVA0_Pos +#define R_RIIC0_ICSAR0_SVA_Msk R_RIIC_ICSAR0_SVA_Msk +#define R_RIIC0_ICSAR0_SVA_Pos R_RIIC_ICSAR0_SVA_Pos +#define R_RIIC0_ICSARU0_FS_Msk R_RIIC_ICSARU0_FS_Msk +#define R_RIIC0_ICSARU0_FS_Pos R_RIIC_ICSARU0_FS_Pos +#define R_RIIC0_ICSARU0_SVA_Msk R_RIIC_ICSARU0_SVA_Msk +#define R_RIIC0_ICSARU0_SVA_Pos R_RIIC_ICSARU0_SVA_Pos +#define R_RIIC0_ICSAR1_SVA0_Msk R_RIIC_ICSAR1_SVA0_Msk +#define R_RIIC0_ICSAR1_SVA0_Pos R_RIIC_ICSAR1_SVA0_Pos +#define R_RIIC0_ICSAR1_SVA_Msk R_RIIC_ICSAR1_SVA_Msk +#define R_RIIC0_ICSAR1_SVA_Pos R_RIIC_ICSAR1_SVA_Pos +#define R_RIIC0_ICSARU1_FS_Msk R_RIIC_ICSARU1_FS_Msk +#define R_RIIC0_ICSARU1_FS_Pos R_RIIC_ICSARU1_FS_Pos +#define R_RIIC0_ICSARU1_SVA_Msk R_RIIC_ICSARU1_SVA_Msk +#define R_RIIC0_ICSARU1_SVA_Pos R_RIIC_ICSARU1_SVA_Pos +#define R_RIIC0_ICSAR2_SVA0_Msk R_RIIC_ICSAR2_SVA0_Msk +#define R_RIIC0_ICSAR2_SVA0_Pos R_RIIC_ICSAR2_SVA0_Pos +#define R_RIIC0_ICSAR2_SVA_Msk R_RIIC_ICSAR2_SVA_Msk +#define R_RIIC0_ICSAR2_SVA_Pos R_RIIC_ICSAR2_SVA_Pos +#define R_RIIC0_ICSARU2_FS_Msk R_RIIC_ICSARU2_FS_Msk +#define R_RIIC0_ICSARU2_FS_Pos R_RIIC_ICSARU2_FS_Pos +#define R_RIIC0_ICSARU2_SVA_Msk R_RIIC_ICSARU2_SVA_Msk +#define R_RIIC0_ICSARU2_SVA_Pos R_RIIC_ICSARU2_SVA_Pos +#define R_RIIC0_ICBRL_BRL_Msk R_RIIC_ICBRL_BRL_Msk +#define R_RIIC0_ICBRL_BRL_Pos R_RIIC_ICBRL_BRL_Pos +#define R_RIIC0_ICBRH_BRH_Msk R_RIIC_ICBRH_BRH_Msk +#define R_RIIC0_ICBRH_BRH_Pos R_RIIC_ICBRH_BRH_Pos +#define R_RIIC0_ICDRT_DRT_Msk R_RIIC_ICDRT_DRT_Msk +#define R_RIIC0_ICDRT_DRT_Pos R_RIIC_ICDRT_DRT_Pos +#define R_RIIC0_ICDRR_DRR_Msk R_RIIC_ICDRR_DRR_Msk +#define R_RIIC0_ICDRR_DRR_Pos R_RIIC_ICDRR_DRR_Pos + +#endif /* RIIC_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/rspi_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/rspi_iobitmask.h new file mode 100644 index 00000000..0109d981 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/rspi_iobitmask.h @@ -0,0 +1,149 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : rspi_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for rspi. + *********************************************************************************************************************/ + +#ifndef RSPI_IOBITMASK_H +#define RSPI_IOBITMASK_H + +#define R_RSPI0_SPCR_MODFEN_Msk (0x04UL) +#define R_RSPI0_SPCR_MODFEN_Pos (2UL) +#define R_RSPI0_SPCR_MSTR_Msk (0x08UL) +#define R_RSPI0_SPCR_MSTR_Pos (3UL) +#define R_RSPI0_SPCR_SPEIE_Msk (0x10UL) +#define R_RSPI0_SPCR_SPEIE_Pos (4UL) +#define R_RSPI0_SPCR_SPTIE_Msk (0x20UL) +#define R_RSPI0_SPCR_SPTIE_Pos (5UL) +#define R_RSPI0_SPCR_SPE_Msk (0x40UL) +#define R_RSPI0_SPCR_SPE_Pos (6UL) +#define R_RSPI0_SPCR_SPRIE_Msk (0x80UL) +#define R_RSPI0_SPCR_SPRIE_Pos (7UL) +#define R_RSPI0_SSLP_SSL0P_Msk (0x01UL) +#define R_RSPI0_SSLP_SSL0P_Pos (0UL) +#define R_RSPI0_SPPCR_SPLP_Msk (0x01UL) +#define R_RSPI0_SPPCR_SPLP_Pos (0UL) +#define R_RSPI0_SPPCR_MOIFV_Msk (0x10UL) +#define R_RSPI0_SPPCR_MOIFV_Pos (4UL) +#define R_RSPI0_SPPCR_MOIFE_Msk (0x20UL) +#define R_RSPI0_SPPCR_MOIFE_Pos (5UL) +#define R_RSPI0_SPSR_OVRF_Msk (0x01UL) +#define R_RSPI0_SPSR_OVRF_Pos (0UL) +#define R_RSPI0_SPSR_MODF_Msk (0x04UL) +#define R_RSPI0_SPSR_MODF_Pos (2UL) +#define R_RSPI0_SPSR_SPTEF_Msk (0x20UL) +#define R_RSPI0_SPSR_SPTEF_Pos (5UL) +#define R_RSPI0_SPSR_TEND_Msk (0x40UL) +#define R_RSPI0_SPSR_TEND_Pos (6UL) +#define R_RSPI0_SPSR_SPRF_Msk (0x80UL) +#define R_RSPI0_SPSR_SPRF_Pos (7UL) +#define R_RSPI0_SPDR_SPD_Msk (0xFFFFFFFFUL) +#define R_RSPI0_SPDR_SPD_Pos (0UL) +#define R_RSPI0_SPSCR_SPSLN_Msk (0x03UL) +#define R_RSPI0_SPSCR_SPSLN_Pos (0UL) +#define R_RSPI0_SPSSR_SPCP_Msk (0x03UL) +#define R_RSPI0_SPSSR_SPCP_Pos (0UL) +#define R_RSPI0_SPBR_SPR_Msk (0xFFUL) +#define R_RSPI0_SPBR_SPR_Pos (0UL) +#define R_RSPI0_SPDCR_SPLW_Msk (0x60UL) +#define R_RSPI0_SPDCR_SPLW_Pos (5UL) +#define R_RSPI0_SPDCR_TXDMY_Msk (0x80UL) +#define R_RSPI0_SPDCR_TXDMY_Pos (7UL) +#define R_RSPI0_SPCKD_SCKDL_Msk (0x07UL) +#define R_RSPI0_SPCKD_SCKDL_Pos (0UL) +#define R_RSPI0_SSLND_SLNDL_Msk (0x07UL) +#define R_RSPI0_SSLND_SLNDL_Pos (0UL) +#define R_RSPI0_SPND_SPNDL_Msk (0x07UL) +#define R_RSPI0_SPND_SPNDL_Pos (0UL) +#define R_RSPI0_SPCMD0_CPHA_Msk (0x0001UL) +#define R_RSPI0_SPCMD0_CPHA_Pos (0UL) +#define R_RSPI0_SPCMD0_CPOL_Msk (0x0002UL) +#define R_RSPI0_SPCMD0_CPOL_Pos (1UL) +#define R_RSPI0_SPCMD0_BRDV_Msk (0x000CUL) +#define R_RSPI0_SPCMD0_BRDV_Pos (2UL) +#define R_RSPI0_SPCMD0_SSLKP_Msk (0x0080UL) +#define R_RSPI0_SPCMD0_SSLKP_Pos (7UL) +#define R_RSPI0_SPCMD0_SPB_Msk (0x0F00UL) +#define R_RSPI0_SPCMD0_SPB_Pos (8UL) +#define R_RSPI0_SPCMD0_LSBF_Msk (0x1000UL) +#define R_RSPI0_SPCMD0_LSBF_Pos (12UL) +#define R_RSPI0_SPCMD0_SPNDEN_Msk (0x2000UL) +#define R_RSPI0_SPCMD0_SPNDEN_Pos (13UL) +#define R_RSPI0_SPCMD0_SLNDEN_Msk (0x4000UL) +#define R_RSPI0_SPCMD0_SLNDEN_Pos (14UL) +#define R_RSPI0_SPCMD0_SCKDEN_Msk (0x8000UL) +#define R_RSPI0_SPCMD0_SCKDEN_Pos (15UL) +#define R_RSPI0_SPCMD1_CPHA_Msk (0x0001UL) +#define R_RSPI0_SPCMD1_CPHA_Pos (0UL) +#define R_RSPI0_SPCMD1_CPOL_Msk (0x0002UL) +#define R_RSPI0_SPCMD1_CPOL_Pos (1UL) +#define R_RSPI0_SPCMD1_BRDV_Msk (0x000CUL) +#define R_RSPI0_SPCMD1_BRDV_Pos (2UL) +#define R_RSPI0_SPCMD1_SSLKP_Msk (0x0080UL) +#define R_RSPI0_SPCMD1_SSLKP_Pos (7UL) +#define R_RSPI0_SPCMD1_SPB_Msk (0x0F00UL) +#define R_RSPI0_SPCMD1_SPB_Pos (8UL) +#define R_RSPI0_SPCMD1_LSBF_Msk (0x1000UL) +#define R_RSPI0_SPCMD1_LSBF_Pos (12UL) +#define R_RSPI0_SPCMD1_SPNDEN_Msk (0x2000UL) +#define R_RSPI0_SPCMD1_SPNDEN_Pos (13UL) +#define R_RSPI0_SPCMD1_SLNDEN_Msk (0x4000UL) +#define R_RSPI0_SPCMD1_SLNDEN_Pos (14UL) +#define R_RSPI0_SPCMD1_SCKDEN_Msk (0x8000UL) +#define R_RSPI0_SPCMD1_SCKDEN_Pos (15UL) +#define R_RSPI0_SPCMD2_CPHA_Msk (0x0001UL) +#define R_RSPI0_SPCMD2_CPHA_Pos (0UL) +#define R_RSPI0_SPCMD2_CPOL_Msk (0x0002UL) +#define R_RSPI0_SPCMD2_CPOL_Pos (1UL) +#define R_RSPI0_SPCMD2_BRDV_Msk (0x000CUL) +#define R_RSPI0_SPCMD2_BRDV_Pos (2UL) +#define R_RSPI0_SPCMD2_SSLKP_Msk (0x0080UL) +#define R_RSPI0_SPCMD2_SSLKP_Pos (7UL) +#define R_RSPI0_SPCMD2_SPB_Msk (0x0F00UL) +#define R_RSPI0_SPCMD2_SPB_Pos (8UL) +#define R_RSPI0_SPCMD2_LSBF_Msk (0x1000UL) +#define R_RSPI0_SPCMD2_LSBF_Pos (12UL) +#define R_RSPI0_SPCMD2_SPNDEN_Msk (0x2000UL) +#define R_RSPI0_SPCMD2_SPNDEN_Pos (13UL) +#define R_RSPI0_SPCMD2_SLNDEN_Msk (0x4000UL) +#define R_RSPI0_SPCMD2_SLNDEN_Pos (14UL) +#define R_RSPI0_SPCMD2_SCKDEN_Msk (0x8000UL) +#define R_RSPI0_SPCMD2_SCKDEN_Pos (15UL) +#define R_RSPI0_SPCMD3_CPHA_Msk (0x0001UL) +#define R_RSPI0_SPCMD3_CPHA_Pos (0UL) +#define R_RSPI0_SPCMD3_CPOL_Msk (0x0002UL) +#define R_RSPI0_SPCMD3_CPOL_Pos (1UL) +#define R_RSPI0_SPCMD3_BRDV_Msk (0x000CUL) +#define R_RSPI0_SPCMD3_BRDV_Pos (2UL) +#define R_RSPI0_SPCMD3_SSLKP_Msk (0x0080UL) +#define R_RSPI0_SPCMD3_SSLKP_Pos (7UL) +#define R_RSPI0_SPCMD3_SPB_Msk (0x0F00UL) +#define R_RSPI0_SPCMD3_SPB_Pos (8UL) +#define R_RSPI0_SPCMD3_LSBF_Msk (0x1000UL) +#define R_RSPI0_SPCMD3_LSBF_Pos (12UL) +#define R_RSPI0_SPCMD3_SPNDEN_Msk (0x2000UL) +#define R_RSPI0_SPCMD3_SPNDEN_Pos (13UL) +#define R_RSPI0_SPCMD3_SLNDEN_Msk (0x4000UL) +#define R_RSPI0_SPCMD3_SLNDEN_Pos (14UL) +#define R_RSPI0_SPCMD3_SCKDEN_Msk (0x8000UL) +#define R_RSPI0_SPCMD3_SCKDEN_Pos (15UL) +#define R_RSPI0_SPBFCR_RXTRG_Msk (0x07UL) +#define R_RSPI0_SPBFCR_RXTRG_Pos (0UL) +#define R_RSPI0_SPBFCR_TXTRG_Msk (0x30UL) +#define R_RSPI0_SPBFCR_TXTRG_Pos (4UL) +#define R_RSPI0_SPBFCR_RXRST_Msk (0x40UL) +#define R_RSPI0_SPBFCR_RXRST_Pos (6UL) +#define R_RSPI0_SPBFCR_TXRST_Msk (0x80UL) +#define R_RSPI0_SPBFCR_TXRST_Pos (7UL) +#define R_RSPI0_SPBFDR_R_Msk (0x003FUL) +#define R_RSPI0_SPBFDR_R_Pos (0UL) +#define R_RSPI0_SPBFDR_T_Msk (0x0F00UL) +#define R_RSPI0_SPBFDR_T_Pos (8UL) + +#endif /* RSPI_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/scifa_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/scifa_iobitmask.h new file mode 100644 index 00000000..ed2a8b4b --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/scifa_iobitmask.h @@ -0,0 +1,127 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : scifa_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for scifa. + *********************************************************************************************************************/ + +#ifndef SCIFA_IOBITMASK_H +#define SCIFA_IOBITMASK_H + +#define R_SCIFA0_SMR_CKS_Msk (0x0003UL) +#define R_SCIFA0_SMR_CKS_Pos (0UL) +#define R_SCIFA0_SMR_STOP_Msk (0x0008UL) +#define R_SCIFA0_SMR_STOP_Pos (3UL) +#define R_SCIFA0_SMR_PM_Msk (0x0010UL) +#define R_SCIFA0_SMR_PM_Pos (4UL) +#define R_SCIFA0_SMR_PE_Msk (0x0020UL) +#define R_SCIFA0_SMR_PE_Pos (5UL) +#define R_SCIFA0_SMR_CHR_Msk (0x0040UL) +#define R_SCIFA0_SMR_CHR_Pos (6UL) +#define R_SCIFA0_SMR_CM_Msk (0x0080UL) +#define R_SCIFA0_SMR_CM_Pos (7UL) +#define R_SCIFA0_MDDR_MDDR_Msk (0xFFUL) +#define R_SCIFA0_MDDR_MDDR_Pos (0UL) +#define R_SCIFA0_BRR_BRR_Msk (0xFFUL) +#define R_SCIFA0_BRR_BRR_Pos (0UL) +#define R_SCIFA0_SCR_CKE_Msk (0x0003UL) +#define R_SCIFA0_SCR_CKE_Pos (0UL) +#define R_SCIFA0_SCR_TEIE_Msk (0x0004UL) +#define R_SCIFA0_SCR_TEIE_Pos (2UL) +#define R_SCIFA0_SCR_REIE_Msk (0x0008UL) +#define R_SCIFA0_SCR_REIE_Pos (3UL) +#define R_SCIFA0_SCR_RE_Msk (0x0010UL) +#define R_SCIFA0_SCR_RE_Pos (4UL) +#define R_SCIFA0_SCR_TE_Msk (0x0020UL) +#define R_SCIFA0_SCR_TE_Pos (5UL) +#define R_SCIFA0_SCR_RIE_Msk (0x0040UL) +#define R_SCIFA0_SCR_RIE_Pos (6UL) +#define R_SCIFA0_SCR_TIE_Msk (0x0080UL) +#define R_SCIFA0_SCR_TIE_Pos (7UL) +#define R_SCIFA0_FTDR_FTDR_Msk (0xFFUL) +#define R_SCIFA0_FTDR_FTDR_Pos (0UL) +#define R_SCIFA0_FSR_DR_Msk (0x0001UL) +#define R_SCIFA0_FSR_DR_Pos (0UL) +#define R_SCIFA0_FSR_RDF_Msk (0x0002UL) +#define R_SCIFA0_FSR_RDF_Pos (1UL) +#define R_SCIFA0_FSR_PER_Msk (0x0004UL) +#define R_SCIFA0_FSR_PER_Pos (2UL) +#define R_SCIFA0_FSR_FER_Msk (0x0008UL) +#define R_SCIFA0_FSR_FER_Pos (3UL) +#define R_SCIFA0_FSR_BRK_Msk (0x0010UL) +#define R_SCIFA0_FSR_BRK_Pos (4UL) +#define R_SCIFA0_FSR_TDFE_Msk (0x0020UL) +#define R_SCIFA0_FSR_TDFE_Pos (5UL) +#define R_SCIFA0_FSR_TEND_Msk (0x0040UL) +#define R_SCIFA0_FSR_TEND_Pos (6UL) +#define R_SCIFA0_FSR_ER_Msk (0x0080UL) +#define R_SCIFA0_FSR_ER_Pos (7UL) +#define R_SCIFA0_FRDR_FRDR_Msk (0xFFUL) +#define R_SCIFA0_FRDR_FRDR_Pos (0UL) +#define R_SCIFA0_FCR_LOOP_Msk (0x0001UL) +#define R_SCIFA0_FCR_LOOP_Pos (0UL) +#define R_SCIFA0_FCR_RFRST_Msk (0x0002UL) +#define R_SCIFA0_FCR_RFRST_Pos (1UL) +#define R_SCIFA0_FCR_TFRST_Msk (0x0004UL) +#define R_SCIFA0_FCR_TFRST_Pos (2UL) +#define R_SCIFA0_FCR_MCE_Msk (0x0008UL) +#define R_SCIFA0_FCR_MCE_Pos (3UL) +#define R_SCIFA0_FCR_TTRG_Msk (0x0030UL) +#define R_SCIFA0_FCR_TTRG_Pos (4UL) +#define R_SCIFA0_FCR_RTRG_Msk (0x00C0UL) +#define R_SCIFA0_FCR_RTRG_Pos (6UL) +#define R_SCIFA0_FCR_RSTRG_Msk (0x0700UL) +#define R_SCIFA0_FCR_RSTRG_Pos (8UL) +#define R_SCIFA0_FDR_R_Msk (0x001FUL) +#define R_SCIFA0_FDR_R_Pos (0UL) +#define R_SCIFA0_FDR_T_Msk (0x1F00UL) +#define R_SCIFA0_FDR_T_Pos (8UL) +#define R_SCIFA0_SPTR_SPB2DT_Msk (0x0001UL) +#define R_SCIFA0_SPTR_SPB2DT_Pos (0UL) +#define R_SCIFA0_SPTR_SPB2IO_Msk (0x0002UL) +#define R_SCIFA0_SPTR_SPB2IO_Pos (1UL) +#define R_SCIFA0_SPTR_SCKDT_Msk (0x0004UL) +#define R_SCIFA0_SPTR_SCKDT_Pos (2UL) +#define R_SCIFA0_SPTR_SCKIO_Msk (0x0008UL) +#define R_SCIFA0_SPTR_SCKIO_Pos (3UL) +#define R_SCIFA0_SPTR_CTS2DT_Msk (0x0010UL) +#define R_SCIFA0_SPTR_CTS2DT_Pos (4UL) +#define R_SCIFA0_SPTR_CTS2IO_Msk (0x0020UL) +#define R_SCIFA0_SPTR_CTS2IO_Pos (5UL) +#define R_SCIFA0_SPTR_RTS2DT_Msk (0x0040UL) +#define R_SCIFA0_SPTR_RTS2DT_Pos (6UL) +#define R_SCIFA0_SPTR_RTS2IO_Msk (0x0080UL) +#define R_SCIFA0_SPTR_RTS2IO_Pos (7UL) +#define R_SCIFA0_LSR_ORER_Msk (0x0001UL) +#define R_SCIFA0_LSR_ORER_Pos (0UL) +#define R_SCIFA0_LSR_FER_Msk (0x003CUL) +#define R_SCIFA0_LSR_FER_Pos (2UL) +#define R_SCIFA0_LSR_PER_Msk (0x0F00UL) +#define R_SCIFA0_LSR_PER_Pos (8UL) +#define R_SCIFA0_SEMR_ABCS0_Msk (0x01UL) +#define R_SCIFA0_SEMR_ABCS0_Pos (0UL) +#define R_SCIFA0_SEMR_NFEN_Msk (0x04UL) +#define R_SCIFA0_SEMR_NFEN_Pos (2UL) +#define R_SCIFA0_SEMR_DIR_Msk (0x08UL) +#define R_SCIFA0_SEMR_DIR_Pos (3UL) +#define R_SCIFA0_SEMR_MDDRS_Msk (0x10UL) +#define R_SCIFA0_SEMR_MDDRS_Pos (4UL) +#define R_SCIFA0_SEMR_BRME_Msk (0x20UL) +#define R_SCIFA0_SEMR_BRME_Pos (5UL) +#define R_SCIFA0_SEMR_BGDM_Msk (0x80UL) +#define R_SCIFA0_SEMR_BGDM_Pos (7UL) +#define R_SCIFA0_FTCR_TFTC_Msk (0x001FUL) +#define R_SCIFA0_FTCR_TFTC_Pos (0UL) +#define R_SCIFA0_FTCR_TTRGS_Msk (0x0080UL) +#define R_SCIFA0_FTCR_TTRGS_Pos (7UL) +#define R_SCIFA0_FTCR_RFTC_Msk (0x1F00UL) +#define R_SCIFA0_FTCR_RFTC_Pos (8UL) +#define R_SCIFA0_FTCR_RTRGS_Msk (0x8000UL) +#define R_SCIFA0_FTCR_RTRGS_Pos (15UL) + +#endif /* SCIFA_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/ssi_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/ssi_iobitmask.h new file mode 100644 index 00000000..8d1cc4d2 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/ssi_iobitmask.h @@ -0,0 +1,109 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : ssi_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for ssi. + *********************************************************************************************************************/ + +#ifndef SSI_IOBITMASK_H +#define SSI_IOBITMASK_H + +#define R_SSI_SSICR_REN_Msk (0x00000001UL) +#define R_SSI_SSICR_REN_Pos (0UL) +#define R_SSI_SSICR_TEN_Msk (0x00000002UL) +#define R_SSI_SSICR_TEN_Pos (1UL) +#define R_SSI_SSICR_MUEN_Msk (0x00000008UL) +#define R_SSI_SSICR_MUEN_Pos (3UL) +#define R_SSI_SSICR_CKDV_Msk (0x000000F0UL) +#define R_SSI_SSICR_CKDV_Pos (4UL) +#define R_SSI_SSICR_DEL_Msk (0x00000100UL) +#define R_SSI_SSICR_DEL_Pos (8UL) +#define R_SSI_SSICR_PDTA_Msk (0x00000200UL) +#define R_SSI_SSICR_PDTA_Pos (9UL) +#define R_SSI_SSICR_SDTA_Msk (0x00000400UL) +#define R_SSI_SSICR_SDTA_Pos (10UL) +#define R_SSI_SSICR_SPDP_Msk (0x00000800UL) +#define R_SSI_SSICR_SPDP_Pos (11UL) +#define R_SSI_SSICR_LRCKP_Msk (0x00001000UL) +#define R_SSI_SSICR_LRCKP_Pos (12UL) +#define R_SSI_SSICR_BCKP_Msk (0x00002000UL) +#define R_SSI_SSICR_BCKP_Pos (13UL) +#define R_SSI_SSICR_MST_Msk (0x00004000UL) +#define R_SSI_SSICR_MST_Pos (14UL) +#define R_SSI_SSICR_SWL_Msk (0x00070000UL) +#define R_SSI_SSICR_SWL_Pos (16UL) +#define R_SSI_SSICR_DWL_Msk (0x00380000UL) +#define R_SSI_SSICR_DWL_Pos (19UL) +#define R_SSI_SSICR_FRM_Msk (0x00C00000UL) +#define R_SSI_SSICR_FRM_Pos (22UL) +#define R_SSI_SSICR_IIEN_Msk (0x02000000UL) +#define R_SSI_SSICR_IIEN_Pos (25UL) +#define R_SSI_SSICR_ROIEN_Msk (0x04000000UL) +#define R_SSI_SSICR_ROIEN_Pos (26UL) +#define R_SSI_SSICR_RUIEN_Msk (0x08000000UL) +#define R_SSI_SSICR_RUIEN_Pos (27UL) +#define R_SSI_SSICR_TOIEN_Msk (0x10000000UL) +#define R_SSI_SSICR_TOIEN_Pos (28UL) +#define R_SSI_SSICR_TUIEN_Msk (0x20000000UL) +#define R_SSI_SSICR_TUIEN_Pos (29UL) +#define R_SSI_SSICR_CKS_Msk (0x40000000UL) +#define R_SSI_SSICR_CKS_Pos (30UL) +#define R_SSI_SSISR_IIRQ_Msk (0x02000000UL) +#define R_SSI_SSISR_IIRQ_Pos (25UL) +#define R_SSI_SSISR_ROIRQ_Msk (0x04000000UL) +#define R_SSI_SSISR_ROIRQ_Pos (26UL) +#define R_SSI_SSISR_RUIRQ_Msk (0x08000000UL) +#define R_SSI_SSISR_RUIRQ_Pos (27UL) +#define R_SSI_SSISR_TOIRQ_Msk (0x10000000UL) +#define R_SSI_SSISR_TOIRQ_Pos (28UL) +#define R_SSI_SSISR_TUIRQ_Msk (0x20000000UL) +#define R_SSI_SSISR_TUIRQ_Pos (29UL) +#define R_SSI_SSIFCR_RFRST_Msk (0x00000001UL) +#define R_SSI_SSIFCR_RFRST_Pos (0UL) +#define R_SSI_SSIFCR_TFRST_Msk (0x00000002UL) +#define R_SSI_SSIFCR_TFRST_Pos (1UL) +#define R_SSI_SSIFCR_RIE_Msk (0x00000004UL) +#define R_SSI_SSIFCR_RIE_Pos (2UL) +#define R_SSI_SSIFCR_TIE_Msk (0x00000008UL) +#define R_SSI_SSIFCR_TIE_Pos (3UL) +#define R_SSI_SSIFCR_RXDNCE_Msk (0x00000100UL) +#define R_SSI_SSIFCR_RXDNCE_Pos (8UL) +#define R_SSI_SSIFCR_LRCKNCE_Msk (0x00000200UL) +#define R_SSI_SSIFCR_LRCKNCE_Pos (9UL) +#define R_SSI_SSIFCR_BCKNCE_Msk (0x00000400UL) +#define R_SSI_SSIFCR_BCKNCE_Pos (10UL) +#define R_SSI_SSIFCR_BSW_Msk (0x00000800UL) +#define R_SSI_SSIFCR_BSW_Pos (11UL) +#define R_SSI_SSIFCR_SSIRST_Msk (0x00010000UL) +#define R_SSI_SSIFCR_SSIRST_Pos (16UL) +#define R_SSI_SSIFCR_AUCKE_Msk (0x80000000UL) +#define R_SSI_SSIFCR_AUCKE_Pos (31UL) +#define R_SSI_SSIFSR_RDF_Msk (0x00000001UL) +#define R_SSI_SSIFSR_RDF_Pos (0UL) +#define R_SSI_SSIFSR_RDC_Msk (0x00003F00UL) +#define R_SSI_SSIFSR_RDC_Pos (8UL) +#define R_SSI_SSIFSR_TDE_Msk (0x00010000UL) +#define R_SSI_SSIFSR_TDE_Pos (16UL) +#define R_SSI_SSIFSR_TDC_Msk (0x3F000000UL) +#define R_SSI_SSIFSR_TDC_Pos (24UL) +#define R_SSI_SSIFTDR_SSIFTDR_Msk (0xFFFFFFFFUL) +#define R_SSI_SSIFTDR_SSIFTDR_Pos (0UL) +#define R_SSI_SSIFRDR_SSIFRDR_Msk (0xFFFFFFFFUL) +#define R_SSI_SSIFRDR_SSIFRDR_Pos (0UL) +#define R_SSI_SSIOFR_OMOD_Msk (0x00000003UL) +#define R_SSI_SSIOFR_OMOD_Pos (0UL) +#define R_SSI_SSIOFR_LRCONT_Msk (0x00000100UL) +#define R_SSI_SSIOFR_LRCONT_Pos (8UL) +#define R_SSI_SSIOFR_BCKSTP_Msk (0x00000200UL) +#define R_SSI_SSIOFR_BCKSTP_Pos (9UL) +#define R_SSI_SSISCR_RDFS_Msk (0x0000001FUL) +#define R_SSI_SSISCR_RDFS_Pos (0UL) +#define R_SSI_SSISCR_TDES_Msk (0x00001F00UL) +#define R_SSI_SSISCR_TDES_Pos (8UL) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/sysc_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/sysc_iobitmask.h new file mode 100644 index 00000000..c083048e --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/sysc_iobitmask.h @@ -0,0 +1,656 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : sysc_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for sysc. + *********************************************************************************************************************/ +#ifndef SYSC_IOBITMASK_H +#define SYSC_IOBITMASK_H + +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWPU_Msk (0x00000001UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWPU_Pos (0UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWNS_Msk (0x00000002UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWNS_Pos (1UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWSEL_Msk (0x00000008UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWSEL_Pos (3UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARPU_Msk (0x00000010UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARPU_Pos (4UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARNS_Msk (0x00000020UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARNS_Pos (5UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARSEL_Msk (0x00000080UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARSEL_Pos (7UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWPU_Msk (0x00000100UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWPU_Pos (8UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWNS_Msk (0x00000200UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWNS_Pos (9UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWSEL_Msk (0x00000800UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWSEL_Pos (11UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARPU_Msk (0x00001000UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARPU_Pos (12UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARNS_Msk (0x00002000UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARNS_Pos (13UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARSEL_Msk (0x00008000UL) +#define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARSEL_Pos (15UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWPU_Msk (0x00000001UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWPU_Pos (0UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWNS_Msk (0x00000002UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWNS_Pos (1UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWSEL_Msk (0x00000008UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWSEL_Pos (3UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARPU_Msk (0x00000010UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARPU_Pos (4UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARNS_Msk (0x00000020UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARNS_Pos (5UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARSEL_Msk (0x00000080UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARSEL_Pos (7UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWPU_Msk (0x00000100UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWPU_Pos (8UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWNS_Msk (0x00000200UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWNS_Pos (9UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWSEL_Msk (0x00000800UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWSEL_Pos (11UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARPU_Msk (0x00001000UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARPU_Pos (12UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARNS_Msk (0x00002000UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARNS_Pos (13UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARSEL_Msk (0x00008000UL) +#define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARSEL_Pos (15UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWPU_Msk (0x00010000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWPU_Pos (16UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWNS_Msk (0x00020000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWNS_Pos (17UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWSEL_Msk (0x00080000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_AWSEL_Pos (19UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARPU_Msk (0x00100000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARPU_Pos (20UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARNS_Msk (0x00200000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARNS_Pos (21UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARSEL_Msk (0x00800000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther0_ARSEL_Pos (23UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWPU_Msk (0x01000000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWPU_Pos (24UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWNS_Msk (0x02000000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWNS_Pos (25UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWSEL_Msk (0x08000000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_AWSEL_Pos (27UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARPU_Msk (0x10000000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARPU_Pos (28UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARNS_Msk (0x20000000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARNS_Pos (29UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARSEL_Msk (0x80000000UL) +#define R_SYSC_SYS_MSTACCCTL1_GEther1_ARSEL_Pos (31UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWPU_Msk (0x00000001UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWPU_Pos (0UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWNS_Msk (0x00000002UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWNS_Pos (1UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWSEL_Msk (0x00000008UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_AWSEL_Pos (3UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARPU_Msk (0x00000010UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARPU_Pos (4UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARNS_Msk (0x00000020UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARNS_Pos (5UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARSEL_Msk (0x00000080UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20H_ARSEL_Pos (7UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWPU_Msk (0x00000100UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWPU_Pos (8UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWNS_Msk (0x00000200UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWNS_Pos (9UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWSEL_Msk (0x00000800UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_AWSEL_Pos (11UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARPU_Msk (0x00001000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARPU_Pos (12UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARNS_Msk (0x00002000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARNS_Pos (13UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARSEL_Msk (0x00008000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB20D_ARSEL_Pos (15UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWPU_Msk (0x00010000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWPU_Pos (16UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWNS_Msk (0x00020000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWNS_Pos (17UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWSEL_Msk (0x00080000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_AWSEL_Pos (19UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARPU_Msk (0x00100000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARPU_Pos (20UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARNS_Msk (0x00200000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARNS_Pos (21UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARSEL_Msk (0x00800000UL) +#define R_SYSC_SYS_MSTACCCTL2_USB21H_ARSEL_Pos (23UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWPU_Msk (0x00000001UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWPU_Pos (0UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWNS_Msk (0x00000002UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWNS_Pos (1UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWSEL_Msk (0x00000008UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWSEL_Pos (3UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARPU_Msk (0x00000010UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARPU_Pos (4UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARNS_Msk (0x00000020UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARNS_Pos (5UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARSEL_Msk (0x00000080UL) +#define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARSEL_Pos (7UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWPU_Msk (0x00000100UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWPU_Pos (8UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWNS_Msk (0x00000200UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWNS_Pos (9UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWSEL_Msk (0x00000800UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_AWSEL_Pos (11UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARPU_Msk (0x00001000UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARPU_Pos (12UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARNS_Msk (0x00002000UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARNS_Pos (13UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARSEL_Msk (0x00008000UL) +#define R_SYSC_SYS_MSTACCCTL6_PCIE_ARSEL_Pos (15UL) +#define R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL0_SRAM2_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL0_SRAM2_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL0_SRAM3_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL0_SRAM3_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC0_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC0_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC1_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL2_TZC1_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC2_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC2_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC3_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC3_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC5_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC5_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC6_SL_Msk (0x00003000UL) +#define R_SYSC_SYS_SLVACCCTL2_TZC6_SL_Pos (12UL) +#define R_SYSC_SYS_SLVACCCTL3_CST_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL3_CST_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL3_CPG_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL3_CPG_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL3_SYSC_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL3_SYSC_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL3_SYC_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL3_SYC_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL3_GIC_SL_Msk (0x00000300UL) +#define R_SYSC_SYS_SLVACCCTL3_GIC_SL_Pos (8UL) +#define R_SYSC_SYS_SLVACCCTL3_IA55IM33_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL3_IA55IM33_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL3_GPIO_SL_Msk (0x00003000UL) +#define R_SYSC_SYS_SLVACCCTL3_GPIO_SL_Pos (12UL) +#define R_SYSC_SYS_SLVACCCTL3_MHU_SL_Msk (0x0000C000UL) +#define R_SYSC_SYS_SLVACCCTL3_MHU_SL_Pos (14UL) +#define R_SYSC_SYS_SLVACCCTL4_DMAC0_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL4_DMAC0_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL4_DMAC1_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL4_DMAC1_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM0_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM0_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM1_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM1_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM2_SL_Msk (0x00000300UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM2_SL_Pos (8UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM3_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM3_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM4_SL_Msk (0x00003000UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM4_SL_Pos (12UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM5_SL_Msk (0x0000C000UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM5_SL_Pos (14UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM6_SL_Msk (0x00030000UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM6_SL_Pos (16UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM7_SL_Msk (0x000C0000UL) +#define R_SYSC_SYS_SLVACCCTL4_OSTM7_SL_Pos (18UL) +#define R_SYSC_SYS_SLVACCCTL4_WDT0_SL_Msk (0x00300000UL) +#define R_SYSC_SYS_SLVACCCTL4_WDT0_SL_Pos (20UL) +#define R_SYSC_SYS_SLVACCCTL4_WDT1_SL_Msk (0x00C00000UL) +#define R_SYSC_SYS_SLVACCCTL4_WDT1_SL_Pos (22UL) +#define R_SYSC_SYS_SLVACCCTL4_WDT2_SL_Msk (0x03000000UL) +#define R_SYSC_SYS_SLVACCCTL4_WDT2_SL_Pos (24UL) +#define R_SYSC_SYS_SLVACCCTL4_RTC_SL_Msk (0x30000000UL) +#define R_SYSC_SYS_SLVACCCTL4_RTC_SL_Pos (28UL) +#define R_SYSC_SYS_SLVACCCTL5_MTU3A_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL5_MTU3A_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL5_POE3_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL5_POE3_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL5_GPT_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL5_GPT_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL5_POEG_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL5_POEG_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL5_DDR_SL_Msk (0x00000300UL) +#define R_SYSC_SYS_SLVACCCTL5_DDR_SL_Pos (8UL) +#define R_SYSC_SYS_SLVACCCTL5_XSPI_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL5_XSPI_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL5_OCTA_SL_Msk (0x00003000UL) +#define R_SYSC_SYS_SLVACCCTL5_OCTA_SL_Pos (12UL) +#define R_SYSC_SYS_SLVACCCTL6_USBT_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL6_USBT_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL6_USBT20_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL6_USBT20_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL6_USBT21_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL6_USBT21_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL6_SDHI0_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL6_SDHI0_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL6_SDHI1_SL_Msk (0x00000300UL) +#define R_SYSC_SYS_SLVACCCTL6_SDHI1_SL_Pos (8UL) +#define R_SYSC_SYS_SLVACCCTL6_SDHI2_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL6_SDHI2_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL6_ETH0_SL_Msk (0x00003000UL) +#define R_SYSC_SYS_SLVACCCTL6_ETH0_SL_Pos (12UL) +#define R_SYSC_SYS_SLVACCCTL6_ETH1_SL_Msk (0x0000C000UL) +#define R_SYSC_SYS_SLVACCCTL6_ETH1_SL_Pos (14UL) +#define R_SYSC_SYS_SLVACCCTL6_PCIE_SL_Msk (0x00030000UL) +#define R_SYSC_SYS_SLVACCCTL6_PCIE_SL_Pos (16UL) +#define R_SYSC_SYS_SLVACCCTL7_I2C0_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL7_I2C0_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL7_I2C1_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL7_I2C1_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL7_I2C2_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL7_I2C2_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL7_I2C3_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL7_I2C3_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL7_I3C_SL_Msk (0x00000300UL) +#define R_SYSC_SYS_SLVACCCTL7_I3C_SL_Pos (8UL) +#define R_SYSC_SYS_SLVACCCTL7_CANFD_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL7_CANFD_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI0_SL_Msk (0x00003000UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI0_SL_Pos (12UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI1_SL_Msk (0x0000C000UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI1_SL_Pos (14UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI2_SL_Msk (0x00030000UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI2_SL_Pos (16UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI3_SL_Msk (0x000C0000UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI3_SL_Pos (18UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI4_SL_Msk (0x00300000UL) +#define R_SYSC_SYS_SLVACCCTL7_RSPI4_SL_Pos (20UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF0_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF0_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF1_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF1_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF2_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF2_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF3_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF3_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF4_SL_Msk (0x00000300UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF4_SL_Pos (8UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF5_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL8_SCIF5_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL8_SCI0_SL_Msk (0x00003000UL) +#define R_SYSC_SYS_SLVACCCTL8_SCI0_SL_Pos (12UL) +#define R_SYSC_SYS_SLVACCCTL8_SCI1_SL_Msk (0x0000C000UL) +#define R_SYSC_SYS_SLVACCCTL8_SCI1_SL_Pos (14UL) +#define R_SYSC_SYS_SLVACCCTL8_IRDA_SL_Msk (0x00030000UL) +#define R_SYSC_SYS_SLVACCCTL8_IRDA_SL_Pos (16UL) +#define R_SYSC_SYS_SLVACCCTL9_SSIF0_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL9_SSIF0_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL9_SSIF1_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL9_SSIF1_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL9_SSIF2_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL9_SSIF2_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL9_SSIF3_SL_Msk (0x000000C0UL) +#define R_SYSC_SYS_SLVACCCTL9_SSIF3_SL_Pos (6UL) +#define R_SYSC_SYS_SLVACCCTL9_SRC_SL_Msk (0x00000300UL) +#define R_SYSC_SYS_SLVACCCTL9_SRC_SL_Pos (8UL) +#define R_SYSC_SYS_SLVACCCTL9_SPDIF_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL9_SPDIF_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL9_PDM_SL_Msk (0x00003000UL) +#define R_SYSC_SYS_SLVACCCTL9_PDM_SL_Pos (12UL) +#define R_SYSC_SYS_SLVACCCTL10_ADC_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL10_ADC_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL10_TSU_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL10_TSU_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL11_OTP_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL11_OTP_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL11_VBATT_SL_Msk (0x00000C00UL) +#define R_SYSC_SYS_SLVACCCTL11_VBATT_SL_Pos (10UL) +#define R_SYSC_SYS_SLVACCCTL12_CA55_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL12_CA55_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL12_CM33_SL_Msk (0x0000000CUL) +#define R_SYSC_SYS_SLVACCCTL12_CM33_SL_Pos (2UL) +#define R_SYSC_SYS_SLVACCCTL12_CM33FPU_SL_Msk (0x00000030UL) +#define R_SYSC_SYS_SLVACCCTL12_CM33FPU_SL_Pos (4UL) +#define R_SYSC_SYS_SLVACCCTL14_LSI_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL14_LSI_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL16_AOF_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL16_AOF_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL17_LP_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL17_LP_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL18_GPREG_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL18_GPREG_SL_Pos (0UL) +#define R_SYSC_SYS_SLVACCCTL20_IPCONT_SL_Msk (0x00000003UL) +#define R_SYSC_SYS_SLVACCCTL20_IPCONT_SL_Pos (0UL) +#define R_SYSC_SYS_RAM0_ECC_VECCEN_Msk (0x00000001UL) +#define R_SYSC_SYS_RAM0_ECC_VECCEN_Pos (0UL) +#define R_SYSC_SYS_RAM0_EN_VCEN_Msk (0x00000001UL) +#define R_SYSC_SYS_RAM0_EN_VCEN_Pos (0UL) +#define R_SYSC_SYS_RAM0_EN_VLWEN_Msk (0x00000002UL) +#define R_SYSC_SYS_RAM0_EN_VLWEN_Pos (1UL) +#define R_SYSC_SYS_RAM1_ECC_VECCEN_Msk (0x00000001UL) +#define R_SYSC_SYS_RAM1_ECC_VECCEN_Pos (0UL) +#define R_SYSC_SYS_RAM1_EN_VCEN_Msk (0x00000001UL) +#define R_SYSC_SYS_RAM1_EN_VCEN_Pos (0UL) +#define R_SYSC_SYS_RAM1_EN_VLWEN_Msk (0x00000002UL) +#define R_SYSC_SYS_RAM1_EN_VLWEN_Pos (1UL) +#define R_SYSC_SYS_RAM2_ECC_VECCEN_Msk (0x00000001UL) +#define R_SYSC_SYS_RAM2_ECC_VECCEN_Pos (0UL) +#define R_SYSC_SYS_RAM2_EN_VCEN_Msk (0x00000001UL) +#define R_SYSC_SYS_RAM2_EN_VCEN_Pos (0UL) +#define R_SYSC_SYS_RAM2_EN_VLWEN_Msk (0x00000002UL) +#define R_SYSC_SYS_RAM2_EN_VLWEN_Pos (1UL) +#define R_SYSC_SYS_RAM3_ECC_VECCEN_Msk (0x00000001UL) +#define R_SYSC_SYS_RAM3_ECC_VECCEN_Pos (0UL) +#define R_SYSC_SYS_RAM3_EN_VCEN_Msk (0x00000001UL) +#define R_SYSC_SYS_RAM3_EN_VCEN_Pos (0UL) +#define R_SYSC_SYS_RAM3_EN_VLWEN_Msk (0x00000002UL) +#define R_SYSC_SYS_RAM3_EN_VLWEN_Pos (1UL) +#define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Msk (0x00000001UL) +#define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Pos (0UL) +#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Msk (0x00010000UL) +#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Pos (16UL) +#define R_SYSC_SYS_WDT1_CTRL_WDTSTOP_Msk (0x00000001UL) +#define R_SYSC_SYS_WDT1_CTRL_WDTSTOP_Pos (0UL) +#define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Msk (0x00010000UL) +#define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Pos (16UL) +#define R_SYSC_SYS_WDT2_CTRL_WDTSTOP_Msk (0x00000001UL) +#define R_SYSC_SYS_WDT2_CTRL_WDTSTOP_Pos (0UL) +#define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Msk (0x00010000UL) +#define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Pos (16UL) +#define R_SYSC_SYS_DDR_MCAR_CTRL_MCAR_CTRL_Msk (0x00010000UL) +#define R_SYSC_SYS_DDR_MCAR_CTRL_MCAR_CTRL_Pos (16UL) +#define R_SYSC_SYS_XSPI_MAP_STAADD_CS0_MAP_STAADD_CS0_Msk (0xFFFFFFFFUL) +#define R_SYSC_SYS_XSPI_MAP_STAADD_CS0_MAP_STAADD_CS0_Pos (0UL) +#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS0_MAP_ENDADD_CS0_Msk (0xFFFFFFFFUL) +#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS0_MAP_ENDADD_CS0_Pos (0UL) +#define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS0_Msk (0x00000001UL) +#define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS0_Pos (0UL) +#define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS1_Msk (0xFFFFFFFEUL) +#define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS1_Pos (1UL) +#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS0_Msk (0x00000001UL) +#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS0_Pos (0UL) +#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS1_Msk (0xFFFFFFFEUL) +#define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS1_Pos (1UL) +#define R_SYSC_SYS_GETH0_CFG_FEC_GIGA_ENABLE_Msk (0x01000000UL) +#define R_SYSC_SYS_GETH0_CFG_FEC_GIGA_ENABLE_Pos (24UL) +#define R_SYSC_SYS_GETH1_CFG_FEC_GIGA_ENABLE_Msk (0x01000000UL) +#define R_SYSC_SYS_GETH1_CFG_FEC_GIGA_ENABLE_Pos (24UL) +#define R_SYSC_SYS_PCIE_CFG_ALLOW_ENTER_L1_Msk (0x00000100UL) +#define R_SYSC_SYS_PCIE_CFG_ALLOW_ENTER_L1_Pos (8UL) +#define R_SYSC_SYS_PCIE_MON_PMU_POWEROFF_Msk (0x00000001UL) +#define R_SYSC_SYS_PCIE_MON_PMU_POWEROFF_Pos (0UL) +#define R_SYSC_SYS_PCIE_MON_CLKL1PM_REQ_Msk (0x00000002UL) +#define R_SYSC_SYS_PCIE_MON_CLKL1PM_REQ_Pos (1UL) +#define R_SYSC_SYS_PCIE_MON_D_STATE_OUT_F0_Msk (0x00000030UL) +#define R_SYSC_SYS_PCIE_MON_D_STATE_OUT_F0_Pos (4UL) +#define R_SYSC_SYS_PCIE_ERR_MON_ERR_COR_DETECTED_F0_Msk (0x00000001UL) +#define R_SYSC_SYS_PCIE_ERR_MON_ERR_COR_DETECTED_F0_Pos (0UL) +#define R_SYSC_SYS_PCIE_ERR_MON_ERR_NONFATAL_DETECTED_F0_Msk (0x00000002UL) +#define R_SYSC_SYS_PCIE_ERR_MON_ERR_NONFATAL_DETECTED_F0_Pos (1UL) +#define R_SYSC_SYS_PCIE_ERR_MON_ERR_FATAL_DETECTED_F0_Msk (0x00000004UL) +#define R_SYSC_SYS_PCIE_ERR_MON_ERR_FATAL_DETECTED_F0_Pos (2UL) +#define R_SYSC_SYS_PCIE_PHY_MODE_RXTERMINATION_Msk (0x00000001UL) +#define R_SYSC_SYS_PCIE_PHY_MODE_RXTERMINATION_Pos (0UL) +#define R_SYSC_SYS_I2C0_CFG_af_bypass_Msk (0x00000001UL) +#define R_SYSC_SYS_I2C0_CFG_af_bypass_Pos (0UL) +#define R_SYSC_SYS_I2C1_CFG_af_bypass_Msk (0x00000001UL) +#define R_SYSC_SYS_I2C1_CFG_af_bypass_Pos (0UL) +#define R_SYSC_SYS_I2C2_CFG_af_bypass_Msk (0x00000001UL) +#define R_SYSC_SYS_I2C2_CFG_af_bypass_Pos (0UL) +#define R_SYSC_SYS_I2C3_CFG_af_bypass_Msk (0x00000001UL) +#define R_SYSC_SYS_I2C3_CFG_af_bypass_Pos (0UL) +#define R_SYSC_SYS_I3C_CFG_af_bypass_Msk (0x00000001UL) +#define R_SYSC_SYS_I3C_CFG_af_bypass_Pos (0UL) +#define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Msk (0xFFFFFFFCUL) +#define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Pos (2UL) +#define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Msk (0x000000FFUL) +#define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Pos (0UL) +#define R_SYSC_SYS_CM33_CFG0_CONFIGSSYSTICK_Msk (0x03FFFFFFUL) +#define R_SYSC_SYS_CM33_CFG0_CONFIGSSYSTICK_Pos (0UL) +#define R_SYSC_SYS_CM33_CFG1_CONFIGNSSYSTICK_Msk (0x03FFFFFFUL) +#define R_SYSC_SYS_CM33_CFG1_CONFIGNSSYSTICK_Pos (0UL) +#define R_SYSC_SYS_CM33_CFG2_INITSVTOR_Msk (0xFFFFFF80UL) +#define R_SYSC_SYS_CM33_CFG2_INITSVTOR_Pos (7UL) +#define R_SYSC_SYS_CM33_CFG3_INITNSVTOR_Msk (0xFFFFFF80UL) +#define R_SYSC_SYS_CM33_CFG3_INITNSVTOR_Pos (7UL) +#define R_SYSC_SYS_CM33_LOCK_LOCKSVTAIRCR_Msk (0x00000001UL) +#define R_SYSC_SYS_CM33_LOCK_LOCKSVTAIRCR_Pos (0UL) +#define R_SYSC_SYS_CM33_LOCK_LOCKNSVTOR_Msk (0x00000002UL) +#define R_SYSC_SYS_CM33_LOCK_LOCKNSVTOR_Pos (1UL) +#define R_SYSC_SYS_CM33FPU_CFG0_CONFIGSSYSTICK_Msk (0x03FFFFFFUL) +#define R_SYSC_SYS_CM33FPU_CFG0_CONFIGSSYSTICK_Pos (0UL) +#define R_SYSC_SYS_CM33FPU_CFG1_CONFIGNSSYSTICK_Msk (0x03FFFFFFUL) +#define R_SYSC_SYS_CM33FPU_CFG1_CONFIGNSSYSTICK_Pos (0UL) +#define R_SYSC_SYS_CM33FPU_CFG2_INITSVTOR_Msk (0xFFFFFFC0UL) +#define R_SYSC_SYS_CM33FPU_CFG2_INITSVTOR_Pos (6UL) +#define R_SYSC_SYS_CM33FPU_CFG3_INITNSVTOR_Msk (0xFFFFFFC0UL) +#define R_SYSC_SYS_CM33FPU_CFG3_INITNSVTOR_Pos (6UL) +#define R_SYSC_SYS_CM33FPU_LOCK_LOCKSVTAIRCR_Msk (0x00000001UL) +#define R_SYSC_SYS_CM33FPU_LOCK_LOCKSVTAIRCR_Pos (0UL) +#define R_SYSC_SYS_CM33FPU_LOCK_LOCKNSVTOR_Msk (0x00000002UL) +#define R_SYSC_SYS_CM33FPU_LOCK_LOCKNSVTOR_Pos (1UL) +#define R_SYSC_SYS_LSI_MODE_STAT_BOOTCPUSEL_Msk (0x00000001UL) +#define R_SYSC_SYS_LSI_MODE_STAT_BOOTCPUSEL_Pos (0UL) +#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Msk (0x00000070UL) +#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Pos (4UL) +#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Msk (0x00000200UL) +#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Pos (9UL) +#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Msk (0x00001000UL) +#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Pos (12UL) +#define R_SYSC_SYS_LSI_MODE_STAT_MD_BYPASS_Msk (0x00002000UL) +#define R_SYSC_SYS_LSI_MODE_STAT_MD_BYPASS_Pos (13UL) +#define R_SYSC_SYS_LSI_MODE_STAT_SEC_EN_Msk (0x00010000UL) +#define R_SYSC_SYS_LSI_MODE_STAT_SEC_EN_Pos (16UL) +#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_0_Msk (0x0000000FUL) +#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_0_Pos (0UL) +#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_0_Msk (0x000000F0UL) +#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_0_Pos (4UL) +#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_0_Msk (0x00000F00UL) +#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_0_Pos (8UL) +#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_0_Msk (0x0000F000UL) +#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_0_Pos (12UL) +#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_1_Msk (0x000F0000UL) +#define R_SYSC_SYS_AOF0_OFS00_SXSDHI_1_Pos (16UL) +#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_1_Msk (0x00F00000UL) +#define R_SYSC_SYS_AOF0_OFS01_SXSDHI_1_Pos (20UL) +#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_1_Msk (0x0F000000UL) +#define R_SYSC_SYS_AOF0_OFS10_SXSDHI_1_Pos (24UL) +#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_1_Msk (0xF0000000UL) +#define R_SYSC_SYS_AOF0_OFS11_SXSDHI_1_Pos (28UL) +#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_0_Msk (0x0000000FUL) +#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_0_Pos (0UL) +#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_0_Msk (0x000000F0UL) +#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_0_Pos (4UL) +#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_0_Msk (0x00000F00UL) +#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_0_Pos (8UL) +#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_0_Msk (0x0000F000UL) +#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_0_Pos (12UL) +#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_1_Msk (0x000F0000UL) +#define R_SYSC_SYS_AOF1_OFS00_SXGIGE_1_Pos (16UL) +#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_1_Msk (0x00F00000UL) +#define R_SYSC_SYS_AOF1_OFS01_SXGIGE_1_Pos (20UL) +#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_1_Msk (0x0F000000UL) +#define R_SYSC_SYS_AOF1_OFS10_SXGIGE_1_Pos (24UL) +#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_1_Msk (0xF0000000UL) +#define R_SYSC_SYS_AOF1_OFS11_SXGIGE_1_Pos (28UL) +#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_0_H_Msk (0x0000000FUL) +#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_0_H_Pos (0UL) +#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_0_H_Msk (0x000000F0UL) +#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_0_H_Pos (4UL) +#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_0_H_Msk (0x00000F00UL) +#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_0_H_Pos (8UL) +#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_0_H_Msk (0x0000F000UL) +#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_0_H_Pos (12UL) +#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_1_Msk (0x000F0000UL) +#define R_SYSC_SYS_AOF2_OFS00_SXUSB2_1_Pos (16UL) +#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_1_Msk (0x00F00000UL) +#define R_SYSC_SYS_AOF2_OFS01_SXUSB2_1_Pos (20UL) +#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_1_Msk (0x0F000000UL) +#define R_SYSC_SYS_AOF2_OFS10_SXUSB2_1_Pos (24UL) +#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_1_Msk (0xF0000000UL) +#define R_SYSC_SYS_AOF2_OFS11_SXUSB2_1_Pos (28UL) +#define R_SYSC_SYS_AOF3_OFS00_SXUSB2_0_F_Msk (0x0000000FUL) +#define R_SYSC_SYS_AOF3_OFS00_SXUSB2_0_F_Pos (0UL) +#define R_SYSC_SYS_AOF3_OFS01_SXUSB2_0_F_Msk (0x000000F0UL) +#define R_SYSC_SYS_AOF3_OFS01_SXUSB2_0_F_Pos (4UL) +#define R_SYSC_SYS_AOF3_OFS10_SXUSB2_0_F_Msk (0x00000F00UL) +#define R_SYSC_SYS_AOF3_OFS10_SXUSB2_0_F_Pos (8UL) +#define R_SYSC_SYS_AOF3_OFS11_SXUSB2_0_F_Msk (0x0000F000UL) +#define R_SYSC_SYS_AOF3_OFS11_SXUSB2_0_F_Pos (12UL) +#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_S_Msk (0x0000000FUL) +#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_S_Pos (0UL) +#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_S_Msk (0x000000F0UL) +#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_S_Pos (4UL) +#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_S_Msk (0x00000F00UL) +#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_S_Pos (8UL) +#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_S_Msk (0x0000F000UL) +#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_S_Pos (12UL) +#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_NS_Msk (0x000F0000UL) +#define R_SYSC_SYS_AOF6_OFS00_SXDMAC_NS_Pos (16UL) +#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_NS_Msk (0x00F00000UL) +#define R_SYSC_SYS_AOF6_OFS01_SXDMAC_NS_Pos (20UL) +#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_NS_Msk (0x0F000000UL) +#define R_SYSC_SYS_AOF6_OFS10_SXDMAC_NS_Pos (24UL) +#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_NS_Msk (0xF0000000UL) +#define R_SYSC_SYS_AOF6_OFS11_SXDMAC_NS_Pos (28UL) +#define R_SYSC_SYS_AOF9_OFS00_SXSDHI_2_Msk (0x0000000FUL) +#define R_SYSC_SYS_AOF9_OFS00_SXSDHI_2_Pos (0UL) +#define R_SYSC_SYS_AOF9_OFS01_SXDMAC_S_Msk (0x000000F0UL) +#define R_SYSC_SYS_AOF9_OFS01_SXDMAC_S_Pos (4UL) +#define R_SYSC_SYS_AOF9_OFS10_SXDMAC_S_Msk (0x00000F00UL) +#define R_SYSC_SYS_AOF9_OFS10_SXDMAC_S_Pos (8UL) +#define R_SYSC_SYS_AOF9_OFS11_SXDMAC_S_Msk (0x0000F000UL) +#define R_SYSC_SYS_AOF9_OFS11_SXDMAC_S_Pos (12UL) +#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_REQ_Msk (0x00000100UL) +#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_REQ_Pos (8UL) +#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_REQ_Msk (0x00001000UL) +#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_REQ_Pos (12UL) +#define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_REQ_Msk (0x00002000UL) +#define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_REQ_Pos (13UL) +#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_ACK_Msk (0x01000000UL) +#define R_SYSC_SYS_LP_CTL1_CA55SLEEP_ACK_Pos (24UL) +#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_ACK_Msk (0x10000000UL) +#define R_SYSC_SYS_LP_CTL1_CM33SLEEP_ACK_Pos (28UL) +#define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_ACK_Msk (0x20000000UL) +#define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_ACK_Pos (29UL) +#define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Msk (0x00000001UL) +#define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Pos (0UL) +#define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Msk (0x00000002UL) +#define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Pos (1UL) +#define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Msk (0x00000004UL) +#define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Pos (2UL) +#define R_SYSC_SYS_LP_CTL5_CA55SLEEP0_F_Msk (0x00000100UL) +#define R_SYSC_SYS_LP_CTL5_CA55SLEEP0_F_Pos (8UL) +#define R_SYSC_SYS_LP_CTL5_CM33SLEEP_F_Msk (0x00000400UL) +#define R_SYSC_SYS_LP_CTL5_CM33SLEEP_F_Pos (10UL) +#define R_SYSC_SYS_LP_CTL5_CM33FPUSLEEP_F_Msk (0x00000800UL) +#define R_SYSC_SYS_LP_CTL5_CM33FPUSLEEP_F_Pos (11UL) +#define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Msk (0x00000002UL) +#define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Pos (1UL) +#define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Msk (0x00000004UL) +#define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Pos (2UL) +#define R_SYSC_SYS_LP_CTL6_CA55SLEEP0_E_Msk (0x00000100UL) +#define R_SYSC_SYS_LP_CTL6_CA55SLEEP0_E_Pos (8UL) +#define R_SYSC_SYS_LP_CTL6_CM33SLEEP_E_Msk (0x00000400UL) +#define R_SYSC_SYS_LP_CTL6_CM33SLEEP_E_Pos (10UL) +#define R_SYSC_SYS_LP_CTL6_CM33FPUSLEEP_E_Msk (0x00000800UL) +#define R_SYSC_SYS_LP_CTL6_CM33FPUSLEEP_E_Pos (11UL) +#define R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk (0x00000001UL) +#define R_SYSC_SYS_LP_CTL7_IM33_MASK_Pos (0UL) +#define R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Msk (0x00000002UL) +#define R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Pos (1UL) +#define R_SYSC_SYS_LP_CM33CTL0_SLEEPMODE_Msk (0x00000001UL) +#define R_SYSC_SYS_LP_CM33CTL0_SLEEPMODE_Pos (0UL) +#define R_SYSC_SYS_LP_CM33CTL0_SLEEPDEEP_Msk (0x00000010UL) +#define R_SYSC_SYS_LP_CM33CTL0_SLEEPDEEP_Pos (4UL) +#define R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Msk (0x00000200UL) +#define R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Pos (9UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Msk (0x00000002UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Pos (1UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Msk (0x00000004UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Pos (2UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Msk (0x00000100UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Pos (8UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Msk (0x00000200UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Pos (9UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Msk (0x00000400UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Pos (10UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Msk (0x00000800UL) +#define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Pos (11UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Msk (0x00000002UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Pos (1UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Msk (0x00000004UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Pos (2UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Msk (0x00000100UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Pos (8UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Msk (0x00000200UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Pos (9UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQAREQn_Msk (0x00000400UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQAREQn_Pos (10UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Msk (0x00000800UL) +#define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Pos (11UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Msk (0x00000001UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Pos (0UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Msk (0x00000002UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Pos (1UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Msk (0x00000004UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Pos (2UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Msk (0x00000100UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Pos (8UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Msk (0x00000200UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Pos (9UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Msk (0x00000400UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Pos (10UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Msk (0x00000800UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Pos (11UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Msk (0x00020000UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Pos (17UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Msk (0x00040000UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Pos (18UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Msk (0x01000000UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Pos (24UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Msk (0x02000000UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Pos (25UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Msk (0x04000000UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Pos (26UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Msk (0x08000000UL) +#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Pos (27UL) +#define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPMODE_Msk (0x00000001UL) +#define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPMODE_Pos (0UL) +#define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPDEEP_Msk (0x00000010UL) +#define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPDEEP_Pos (4UL) +#define R_SYSC_SYS_LP_CM33FPUCTL0_SYSRESETREQ_Msk (0x00000200UL) +#define R_SYSC_SYS_LP_CM33FPUCTL0_SYSRESETREQ_Pos (9UL) +#define R_SYSC_SYS_PD_ISO_CTRL_PD_ISOVCC_ISOEN_Msk (0x00000001UL) +#define R_SYSC_SYS_PD_ISO_CTRL_PD_ISOVCC_ISOEN_Pos (0UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_EN_Msk (0x00000001UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_EN_Pos (0UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_Msk (0x00000002UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_Pos (1UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_EN_Msk (0x00000010UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_EN_Pos (4UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_Msk (0x00000020UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_Pos (5UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_EN_Msk (0x00000100UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_EN_Pos (8UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_Msk (0x00000200UL) +#define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_Pos (9UL) +#define R_SYSC_ISO_IOBUF_SE18_CTRL_ISO_IOBUF_SE18_Msk (0x00000001UL) +#define R_SYSC_ISO_IOBUF_SE18_CTRL_ISO_IOBUF_SE18_Pos (0UL) +#define R_SYSC_SYS_USB_PWRRDY_PWRRDY_N_Msk (0x00000001UL) +#define R_SYSC_SYS_USB_PWRRDY_PWRRDY_N_Pos (0UL) +#define R_SYSC_SYS_PCIE_RST_RSM_B_PCIE_RST_RSM_B_Msk (0x00000001UL) +#define R_SYSC_SYS_PCIE_RST_RSM_B_PCIE_RST_RSM_B_Pos (0UL) +#define R_SYSC_SYS_GPREG_0_GPREG0_Msk (0xFFFFFFFFUL) +#define R_SYSC_SYS_GPREG_0_GPREG0_Pos (0UL) +#define R_SYSC_SYS_GPREG_1_GPREG1_Msk (0xFFFFFFFFUL) +#define R_SYSC_SYS_GPREG_1_GPREG1_Pos (0UL) +#define R_SYSC_SYS_GPREG_2_GPREG2_Msk (0xFFFFFFFFUL) +#define R_SYSC_SYS_GPREG_2_GPREG2_Pos (0UL) +#define R_SYSC_SYS_GPREG_3_GPREG3_Msk (0xFFFFFFFFUL) +#define R_SYSC_SYS_GPREG_3_GPREG3_Pos (0UL) +#define R_SYSC_SYS_IPCONT_SEL_SPI_OCTA_SEL_SPI_OCTA_Msk (0x00000001UL) +#define R_SYSC_SYS_IPCONT_SEL_SPI_OCTA_SEL_SPI_OCTA_Pos (0UL) +#define R_SYSC_SYS_IPCONT_IDAUZERONS_IDAUZERONS_Msk (0x00000001UL) +#define R_SYSC_SYS_IPCONT_IDAUZERONS_IDAUZERONS_Pos (0UL) +#define R_SYSC_SYS_IPCONT_IDAUZERONS_FPU_IDAUZERONS_FPU_Msk (0x00000001UL) +#define R_SYSC_SYS_IPCONT_IDAUZERONS_FPU_IDAUZERONS_FPU_Pos (0UL) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/tsu_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/tsu_iobitmask.h new file mode 100644 index 00000000..0a943fc0 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/tsu_iobitmask.h @@ -0,0 +1,25 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : tsu_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for tsu. + *********************************************************************************************************************/ + +#ifndef TSU_IOBITMASK_H +#define TSU_IOBITMASK_H + +#define R_TSU_TSU_SM_EN_Msk (0x00000001UL) +#define R_TSU_TSU_SM_EN_Pos (0UL) +#define R_TSU_TSU_SM_OE_Msk (0x00000002UL) +#define R_TSU_TSU_SM_OE_Pos (1UL) +#define R_TSU_OTPTSUTRIM0_REG_OTPTSUTRIM0_Msk (0x00000FFFUL) +#define R_TSU_OTPTSUTRIM0_REG_OTPTSUTRIM0_Pos (0UL) +#define R_TSU_OTPTSUTRIM1_REG_OTPTSUTRIM1_Msk (0x00000FFFUL) +#define R_TSU_OTPTSUTRIM1_REG_OTPTSUTRIM1_Pos (0UL) + +#endif /* TSU_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/tzc_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/tzc_iobitmask.h new file mode 100644 index 00000000..901d9b76 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/tzc_iobitmask.h @@ -0,0 +1,299 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : tzc_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for tzc. + *********************************************************************************************************************/ + +#ifndef TZC400_IOBITMASK_H +#define TZC400_IOBITMASK_H + +#define R_TZC_BUILD_CONFIG_NOR_Msk (0x0000001FUL) +#define R_TZC_BUILD_CONFIG_NOR_Pos (0UL) +#define R_TZC_BUILD_CONFIG_ADDRW_Msk (0x00003F00UL) +#define R_TZC_BUILD_CONFIG_ADDRW_Pos (8UL) +#define R_TZC_BUILD_CONFIG_NOF_Msk (0x03000000UL) +#define R_TZC_BUILD_CONFIG_NOF_Pos (24UL) +#define R_TZC_ACTION_RV_Msk (0x00000003UL) +#define R_TZC_ACTION_RV_Pos (0UL) +#define R_TZC_GATE_KEEPER_OR_Msk (0x0000000FUL) +#define R_TZC_GATE_KEEPER_OR_Pos (0UL) +#define R_TZC_GATE_KEEPER_OS_Msk (0x000F0000UL) +#define R_TZC_GATE_KEEPER_OS_Pos (16UL) +#define R_TZC_SPECULATION_CTRL_RSD_Msk (0x00000001UL) +#define R_TZC_SPECULATION_CTRL_RSD_Pos (0UL) +#define R_TZC_SPECULATION_CTRL_WSD_Msk (0x00000002UL) +#define R_TZC_SPECULATION_CTRL_WSD_Pos (1UL) +#define R_TZC_INT_STATUS_STS_Msk (0x0000000FUL) +#define R_TZC_INT_STATUS_STS_Pos (0UL) +#define R_TZC_INT_STATUS_OVERRUN_Msk (0x00000F00UL) +#define R_TZC_INT_STATUS_OVERRUN_Pos (8UL) +#define R_TZC_INT_STATUS_OVERLAP_Msk (0x000F0000UL) +#define R_TZC_INT_STATUS_OVERLAP_Pos (16UL) +#define R_TZC_INT_CLEAR_CLEAR_Msk (0x0000000FUL) +#define R_TZC_INT_CLEAR_CLEAR_Pos (0UL) +#define R_TZC_FAIL_ADDRESS_LOW_0_ASL_Msk (0xFFFFFFFFUL) +#define R_TZC_FAIL_ADDRESS_LOW_0_ASL_Pos (0UL) +#define R_TZC_FAIL_ADDRESS_HIGH_0_ASH_Msk (0x00000001UL) +#define R_TZC_FAIL_ADDRESS_HIGH_0_ASH_Pos (0UL) +#define R_TZC_FAIL_CONTROL_0_PL_Msk (0x00100000UL) +#define R_TZC_FAIL_CONTROL_0_PL_Pos (20UL) +#define R_TZC_FAIL_CONTROL_0_NS_Msk (0x00200000UL) +#define R_TZC_FAIL_CONTROL_0_NS_Pos (21UL) +#define R_TZC_FAIL_CONTROL_0_DC_Msk (0x01000000UL) +#define R_TZC_FAIL_CONTROL_0_DC_Pos (24UL) +#define R_TZC_FAIL_ID_0_ID_Msk (0x00000001UL) +#define R_TZC_FAIL_ID_0_ID_Pos (0UL) +#define R_TZC_FAIL_ID_0_VNET_Msk (0x0F000000UL) +#define R_TZC_FAIL_ID_0_VNET_Pos (24UL) +#define R_TZC_FAIL_ADDRESS_LOW_1_ASL_Msk (0xFFFFFFFFUL) +#define R_TZC_FAIL_ADDRESS_LOW_1_ASL_Pos (0UL) +#define R_TZC_FAIL_ADDRESS_HIGH_1_ASH_Msk (0x00000001UL) +#define R_TZC_FAIL_ADDRESS_HIGH_1_ASH_Pos (0UL) +#define R_TZC_FAIL_CONTROL_1_PL_Msk (0x00100000UL) +#define R_TZC_FAIL_CONTROL_1_PL_Pos (20UL) +#define R_TZC_FAIL_CONTROL_1_NS_Msk (0x00200000UL) +#define R_TZC_FAIL_CONTROL_1_NS_Pos (21UL) +#define R_TZC_FAIL_CONTROL_1_DC_Msk (0x01000000UL) +#define R_TZC_FAIL_CONTROL_1_DC_Pos (24UL) +#define R_TZC_FAIL_ID_1_ID_Msk (0x00000001UL) +#define R_TZC_FAIL_ID_1_ID_Pos (0UL) +#define R_TZC_FAIL_ID_1_VNET_Msk (0x0F000000UL) +#define R_TZC_FAIL_ID_1_VNET_Pos (24UL) +#define R_TZC_FAIL_ADDRESS_LOW_2_ASL_Msk (0xFFFFFFFFUL) +#define R_TZC_FAIL_ADDRESS_LOW_2_ASL_Pos (0UL) +#define R_TZC_FAIL_ADDRESS_HIGH_2_ASH_Msk (0x00000001UL) +#define R_TZC_FAIL_ADDRESS_HIGH_2_ASH_Pos (0UL) +#define R_TZC_FAIL_CONTROL_2_PL_Msk (0x00100000UL) +#define R_TZC_FAIL_CONTROL_2_PL_Pos (20UL) +#define R_TZC_FAIL_CONTROL_2_NS_Msk (0x00200000UL) +#define R_TZC_FAIL_CONTROL_2_NS_Pos (21UL) +#define R_TZC_FAIL_CONTROL_2_DC_Msk (0x01000000UL) +#define R_TZC_FAIL_CONTROL_2_DC_Pos (24UL) +#define R_TZC_FAIL_ID_2_ID_Msk (0x00000001UL) +#define R_TZC_FAIL_ID_2_ID_Pos (0UL) +#define R_TZC_FAIL_ID_2_VNET_Msk (0x0F000000UL) +#define R_TZC_FAIL_ID_2_VNET_Pos (24UL) +#define R_TZC_FAIL_ADDRESS_LOW_3_ASL_Msk (0xFFFFFFFFUL) +#define R_TZC_FAIL_ADDRESS_LOW_3_ASL_Pos (0UL) +#define R_TZC_FAIL_ADDRESS_HIGH_3_ASH_Msk (0x00000001UL) +#define R_TZC_FAIL_ADDRESS_HIGH_3_ASH_Pos (0UL) +#define R_TZC_FAIL_CONTROL_3_PL_Msk (0x00100000UL) +#define R_TZC_FAIL_CONTROL_3_PL_Pos (20UL) +#define R_TZC_FAIL_CONTROL_3_NS_Msk (0x00200000UL) +#define R_TZC_FAIL_CONTROL_3_NS_Pos (21UL) +#define R_TZC_FAIL_CONTROL_3_DC_Msk (0x01000000UL) +#define R_TZC_FAIL_CONTROL_3_DC_Pos (24UL) +#define R_TZC_FAIL_ID_3_ID_Msk (0x00000001UL) +#define R_TZC_FAIL_ID_3_ID_Pos (0UL) +#define R_TZC_FAIL_ID_3_VNET_Msk (0x0F000000UL) +#define R_TZC_FAIL_ID_3_VNET_Pos (24UL) +#define R_TZC_REGION_BASE_LOW_0_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_0_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_0_BAH_Msk (0x00000001UL) +#define R_TZC_REGION_BASE_HIGH_0_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_0_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_0_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_0_TAH_Msk (0x00000001UL) +#define R_TZC_REGION_TOP_HIGH_0_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_0_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_0_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_0_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_0_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_0_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_0_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_0_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_0_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_0_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_0_NWE_Pos (16UL) +#define R_TZC_REGION_BASE_LOW_1_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_1_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_1_BAH_Msk (0x00000003UL) +#define R_TZC_REGION_BASE_HIGH_1_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_1_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_1_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_1_TAH_Msk (0x00000003UL) +#define R_TZC_REGION_TOP_HIGH_1_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_1_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_1_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_1_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_1_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_1_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_1_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_1_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_1_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_1_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_1_NWE_Pos (16UL) +#define R_TZC_REGION_BASE_LOW_2_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_2_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_2_BAH_Msk (0x00000007UL) +#define R_TZC_REGION_BASE_HIGH_2_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_2_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_2_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_2_TAH_Msk (0x00000007UL) +#define R_TZC_REGION_TOP_HIGH_2_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_2_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_2_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_2_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_2_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_2_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_2_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_2_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_2_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_2_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_2_NWE_Pos (16UL) +#define R_TZC_REGION_BASE_LOW_3_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_3_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_3_BAH_Msk (0x0000000FUL) +#define R_TZC_REGION_BASE_HIGH_3_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_3_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_3_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_3_TAH_Msk (0x0000000FUL) +#define R_TZC_REGION_TOP_HIGH_3_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_3_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_3_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_3_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_3_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_3_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_3_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_3_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_3_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_3_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_3_NWE_Pos (16UL) +#define R_TZC_REGION_BASE_LOW_4_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_4_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_4_BAH_Msk (0x0000001FUL) +#define R_TZC_REGION_BASE_HIGH_4_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_4_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_4_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_4_TAH_Msk (0x0000001FUL) +#define R_TZC_REGION_TOP_HIGH_4_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_4_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_4_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_4_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_4_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_4_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_4_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_4_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_4_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_4_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_4_NWE_Pos (16UL) +#define R_TZC_REGION_BASE_LOW_5_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_5_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_5_BAH_Msk (0x0000003FUL) +#define R_TZC_REGION_BASE_HIGH_5_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_5_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_5_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_5_TAH_Msk (0x0000003FUL) +#define R_TZC_REGION_TOP_HIGH_5_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_5_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_5_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_5_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_5_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_5_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_5_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_5_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_5_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_5_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_5_NWE_Pos (16UL) +#define R_TZC_REGION_BASE_LOW_6_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_6_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_6_BAH_Msk (0x0000007FUL) +#define R_TZC_REGION_BASE_HIGH_6_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_6_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_6_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_6_TAH_Msk (0x0000007FUL) +#define R_TZC_REGION_TOP_HIGH_6_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_6_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_6_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_6_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_6_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_6_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_6_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_6_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_6_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_6_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_6_NWE_Pos (16UL) +#define R_TZC_REGION_BASE_LOW_7_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_7_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_7_BAH_Msk (0x000000FFUL) +#define R_TZC_REGION_BASE_HIGH_7_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_7_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_7_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_7_TAH_Msk (0x000000FFUL) +#define R_TZC_REGION_TOP_HIGH_7_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_7_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_7_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_7_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_7_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_7_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_7_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_7_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_7_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_7_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_7_NWE_Pos (16UL) +#define R_TZC_REGION_BASE_LOW_8_BAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_BASE_LOW_8_BAL_Pos (12UL) +#define R_TZC_REGION_BASE_HIGH_8_BAH_Msk (0x000001FFUL) +#define R_TZC_REGION_BASE_HIGH_8_BAH_Pos (0UL) +#define R_TZC_REGION_TOP_LOW_8_TAL_Msk (0xFFFFF000UL) +#define R_TZC_REGION_TOP_LOW_8_TAL_Pos (12UL) +#define R_TZC_REGION_TOP_HIGH_8_TAH_Msk (0x000001FFUL) +#define R_TZC_REGION_TOP_HIGH_8_TAH_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_8_FE_Msk (0x0000000FUL) +#define R_TZC_REGION_ATTRIBUTES_8_FE_Pos (0UL) +#define R_TZC_REGION_ATTRIBUTES_8_SRE_Msk (0x40000000UL) +#define R_TZC_REGION_ATTRIBUTES_8_SRE_Pos (30UL) +#define R_TZC_REGION_ATTRIBUTES_8_SWE_Msk (0x80000000UL) +#define R_TZC_REGION_ATTRIBUTES_8_SWE_Pos (31UL) +#define R_TZC_REGION_ID_ACCESS_8_NRE_Msk (0x0000FFFFUL) +#define R_TZC_REGION_ID_ACCESS_8_NRE_Pos (0UL) +#define R_TZC_REGION_ID_ACCESS_8_NWE_Msk (0xFFFF0000UL) +#define R_TZC_REGION_ID_ACCESS_8_NWE_Pos (16UL) +#define R_TZC_PID4_JEP106_Msk (0x0000000FUL) +#define R_TZC_PID4_JEP106_Pos (0UL) +#define R_TZC_PID4_CNT4KB_Msk (0x000000F0UL) +#define R_TZC_PID4_CNT4KB_Pos (4UL) +#define R_TZC_PID5_JEP106_Msk (0x0000000FUL) +#define R_TZC_PID5_JEP106_Pos (0UL) +#define R_TZC_PID5_CNT4KB_Msk (0x000000F0UL) +#define R_TZC_PID5_CNT4KB_Pos (4UL) +#define R_TZC_PID6_JEP106_Msk (0x0000000FUL) +#define R_TZC_PID6_JEP106_Pos (0UL) +#define R_TZC_PID6_CNT4KB_Msk (0x000000F0UL) +#define R_TZC_PID6_CNT4KB_Pos (4UL) +#define R_TZC_PID7_JEP106_Msk (0x0000000FUL) +#define R_TZC_PID7_JEP106_Pos (0UL) +#define R_TZC_PID7_CNT4KB_Msk (0x000000F0UL) +#define R_TZC_PID7_CNT4KB_Pos (4UL) +#define R_TZC_PID0_JEP106_Msk (0x0000000FUL) +#define R_TZC_PID0_JEP106_Pos (0UL) +#define R_TZC_PID0_CNT4KB_Msk (0x000000F0UL) +#define R_TZC_PID0_CNT4KB_Pos (4UL) +#define R_TZC_PID1_JEP106_Msk (0x0000000FUL) +#define R_TZC_PID1_JEP106_Pos (0UL) +#define R_TZC_PID1_CNT4KB_Msk (0x000000F0UL) +#define R_TZC_PID1_CNT4KB_Pos (4UL) +#define R_TZC_PID2_JEP106_Msk (0x0000000FUL) +#define R_TZC_PID2_JEP106_Pos (0UL) +#define R_TZC_PID2_CNT4KB_Msk (0x000000F0UL) +#define R_TZC_PID2_CNT4KB_Pos (4UL) +#define R_TZC_PID3_JEP106_Msk (0x0000000FUL) +#define R_TZC_PID3_JEP106_Pos (0UL) +#define R_TZC_PID3_CNT4KB_Msk (0x000000F0UL) +#define R_TZC_PID3_CNT4KB_Pos (4UL) +#define R_TZC_CID0_CPI0_Msk (0x000000FFUL) +#define R_TZC_CID0_CPI0_Pos (0UL) +#define R_TZC_CID1_CPI1_Msk (0x000000FFUL) +#define R_TZC_CID1_CPI1_Pos (0UL) +#define R_TZC_CID2_CPI2_Msk (0x000000FFUL) +#define R_TZC_CID2_CPI2_Pos (0UL) +#define R_TZC_CID3_CPI3_Msk (0x000000FFUL) +#define R_TZC_CID3_CPI3_Pos (0UL) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/wdt_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/wdt_iobitmask.h new file mode 100644 index 00000000..31b01e89 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/wdt_iobitmask.h @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : wdt_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for wdt. + *********************************************************************************************************************/ + +#ifndef WDT_IOBITMASK_H +#define WDT_IOBITMASK_H + +#define R_WDT0_WDTCNT_WDTEN_Msk (0x00000001UL) +#define R_WDT0_WDTCNT_WDTEN_Pos (0UL) +#define R_WDT0_WDTSET_WDTTIME_Msk (0xFFF00000UL) +#define R_WDT0_WDTSET_WDTTIME_Pos (20UL) +#define R_WDT0_WDTTIM_CRTTIME_Msk (0xFFFFFFFFUL) +#define R_WDT0_WDTTIM_CRTTIME_Pos (0UL) +#define R_WDT0_WDTINT_INTDISP_Msk (0x00000001UL) +#define R_WDT0_WDTINT_INTDISP_Pos (0UL) +#define R_WDT0_PECR_PECR_Msk (0xFFFFFFFFUL) +#define R_WDT0_PECR_PECR_Pos (0UL) +#define R_WDT0_PEEN_PEEN_Msk (0x00000001UL) +#define R_WDT0_PEEN_PEEN_Pos (0UL) +#define R_WDT0_PESR_PESR_Msk (0xFFFFFFFFUL) +#define R_WDT0_PESR_PESR_Pos (0UL) +#define R_WDT0_PEER_PEER_Msk (0xFFFFFFFFUL) +#define R_WDT0_PEER_PEER_Pos (0UL) +#define R_WDT0_PEPO_PEPO_Msk (0xFFFFFFFFUL) +#define R_WDT0_PEPO_PEPO_Pos (0UL) + +#endif /* WDT_IOBITMASK_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/xspi_iobitmask.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/xspi_iobitmask.h new file mode 100644 index 00000000..d837e021 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/xspi_iobitmask.h @@ -0,0 +1,269 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : xspi_iobitmask.h + * Version : 1.00 + * Description : IO bit mask file for xspi. + *********************************************************************************************************************/ + +#ifndef XSPI_IOBITMASK_H +#define XSPI_IOBITMASK_H + +#define R_XSPI0_WRAPCFG_CKSFTCS0_Msk (0x0000001FUL) +#define R_XSPI0_WRAPCFG_CKSFTCS0_Pos (0UL) +#define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x00001F00UL) +#define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) +#define R_XSPI0_WRAPCFG_CKSFTCS1_Msk (0x001F0000UL) +#define R_XSPI0_WRAPCFG_CKSFTCS1_Pos (16UL) +#define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1F000000UL) +#define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) +#define R_XSPI0_COMCFG_OEASTEX_Msk (0x00010000UL) +#define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) +#define R_XSPI0_COMCFG_OENEGEX_Msk (0x00020000UL) +#define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) +#define R_XSPI0_BMCFG_WRMD_Msk (0x00000001UL) +#define R_XSPI0_BMCFG_WRMD_Pos (0UL) +#define R_XSPI0_BMCFG_MWRCOMB_Msk (0x00000080UL) +#define R_XSPI0_BMCFG_MWRCOMB_Pos (7UL) +#define R_XSPI0_BMCFG_MWRSIZE_Msk (0x0000FF00UL) +#define R_XSPI0_BMCFG_MWRSIZE_Pos (8UL) +#define R_XSPI0_BMCFG_PREEN_Msk (0x00010000UL) +#define R_XSPI0_BMCFG_PREEN_Pos (16UL) +#define R_XSPI0_BMCFG_CMBTIM_Msk (0xFF000000UL) +#define R_XSPI0_BMCFG_CMBTIM_Pos (24UL) +#define R_XSPI0_CSa_CMCFG0_FFMT_Msk (0x00000003UL) +#define R_XSPI0_CSa_CMCFG0_FFMT_Pos (0UL) +#define R_XSPI0_CSa_CMCFG0_ADDSIZE_Msk (0x0000000CUL) +#define R_XSPI0_CSa_CMCFG0_ADDSIZE_Pos (2UL) +#define R_XSPI0_CSa_CMCFG0_WPBSTMD_Msk (0x00000010UL) +#define R_XSPI0_CSa_CMCFG0_WPBSTMD_Pos (4UL) +#define R_XSPI0_CSa_CMCFG0_ARYAMD_Msk (0x00000020UL) +#define R_XSPI0_CSa_CMCFG0_ARYAMD_Pos (5UL) +#define R_XSPI0_CSa_CMCFG0_ADDRPEN_Msk (0x00FF0000UL) +#define R_XSPI0_CSa_CMCFG0_ADDRPEN_Pos (16UL) +#define R_XSPI0_CSa_CMCFG0_ADDRPCD_Msk (0xFF000000UL) +#define R_XSPI0_CSa_CMCFG0_ADDRPCD_Pos (24UL) +#define R_XSPI0_CSa_CMCFG1_RDCMD_Msk (0x0000FFFFUL) +#define R_XSPI0_CSa_CMCFG1_RDCMD_Pos (0UL) +#define R_XSPI0_CSa_CMCFG1_RDLATE_Msk (0x001F0000UL) +#define R_XSPI0_CSa_CMCFG1_RDLATE_Pos (16UL) +#define R_XSPI0_CSa_CMCFG2_WRCMD_Msk (0x0000FFFFUL) +#define R_XSPI0_CSa_CMCFG2_WRCMD_Pos (0UL) +#define R_XSPI0_CSa_CMCFG2_WRLATE_Msk (0x001F0000UL) +#define R_XSPI0_CSa_CMCFG2_WRLATE_Pos (16UL) +#define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x000003FFUL) +#define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) +#define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x00000400UL) +#define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) +#define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x00000800UL) +#define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) +#define R_XSPI0_LIOCFGCS_CSMIN_Msk (0x000F0000UL) +#define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) +#define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x00100000UL) +#define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) +#define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x00200000UL) +#define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) +#define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x00400000UL) +#define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) +#define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x00800000UL) +#define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) +#define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0x0F000000UL) +#define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) +#define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xF0000000UL) +#define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) +#define R_XSPI0_BMCTL0_CS0ACC_Msk (0x00000003UL) +#define R_XSPI0_BMCTL0_CS0ACC_Pos (0UL) +#define R_XSPI0_BMCTL0_CS1ACC_Msk (0x0000000CUL) +#define R_XSPI0_BMCTL0_CS1ACC_Pos (2UL) +#define R_XSPI0_BMCTL1_MWRPUSH_Msk (0x00000100UL) +#define R_XSPI0_BMCTL1_MWRPUSH_Pos (8UL) +#define R_XSPI0_BMCTL1_PBUFCLR_Msk (0x00000400UL) +#define R_XSPI0_BMCTL1_PBUFCLR_Pos (10UL) +#define R_XSPI0_CMCTL_XIPENCODE_Msk (0x000000FFUL) +#define R_XSPI0_CMCTL_XIPENCODE_Pos (0UL) +#define R_XSPI0_CMCTL_XIPEXCODE_Msk (0x0000FF00UL) +#define R_XSPI0_CMCTL_XIPEXCODE_Pos (8UL) +#define R_XSPI0_CMCTL_XIPEN_Msk (0x00010000UL) +#define R_XSPI0_CMCTL_XIPEN_Pos (16UL) +#define R_XSPI0_CDCTL0_TRREQ_Msk (0x00000001UL) +#define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) +#define R_XSPI0_CDCTL0_PERMD_Msk (0x00000002UL) +#define R_XSPI0_CDCTL0_PERMD_Pos (1UL) +#define R_XSPI0_CDCTL0_CSSEL_Msk (0x00000008UL) +#define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) +#define R_XSPI0_CDCTL0_TRNUM_Msk (0x00000030UL) +#define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) +#define R_XSPI0_CDCTL0_PERITV_Msk (0x001F0000UL) +#define R_XSPI0_CDCTL0_PERITV_Pos (16UL) +#define R_XSPI0_CDCTL0_PERREP_Msk (0x0F000000UL) +#define R_XSPI0_CDCTL0_PERREP_Pos (24UL) +#define R_XSPI0_CDCTL1_PEREXP_Msk (0xFFFFFFFFUL) +#define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) +#define R_XSPI0_CDCTL2_PERMSK_Msk (0xFFFFFFFFUL) +#define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) +#define R_XSPI0_BUF_CDT_CMDSIZE_Msk (0x00000003UL) +#define R_XSPI0_BUF_CDT_CMDSIZE_Pos (0UL) +#define R_XSPI0_BUF_CDT_ADDSIZE_Msk (0x0000001CUL) +#define R_XSPI0_BUF_CDT_ADDSIZE_Pos (2UL) +#define R_XSPI0_BUF_CDT_DATASIZE_Msk (0x000001E0UL) +#define R_XSPI0_BUF_CDT_DATASIZE_Pos (5UL) +#define R_XSPI0_BUF_CDT_LATE_Msk (0x00003E00UL) +#define R_XSPI0_BUF_CDT_LATE_Pos (9UL) +#define R_XSPI0_BUF_CDT_TRTYPE_Msk (0x00008000UL) +#define R_XSPI0_BUF_CDT_TRTYPE_Pos (15UL) +#define R_XSPI0_BUF_CDT_CMD_Msk (0xFFFF0000UL) +#define R_XSPI0_BUF_CDT_CMD_Pos (16UL) +#define R_XSPI0_BUF_CDA_ADD_Msk (0xFFFFFFFFUL) +#define R_XSPI0_BUF_CDA_ADD_Pos (0UL) +#define R_XSPI0_BUF_CDD0_DATA_Msk (0xFFFFFFFFUL) +#define R_XSPI0_BUF_CDD0_DATA_Pos (0UL) +#define R_XSPI0_BUF_CDD1_DATA_Msk (0xFFFFFFFFUL) +#define R_XSPI0_BUF_CDD1_DATA_Pos (0UL) +#define R_XSPI0_LPCTL0_PATREQ_Msk (0x00000001UL) +#define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) +#define R_XSPI0_LPCTL0_CSSEL_Msk (0x00000008UL) +#define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) +#define R_XSPI0_LPCTL0_XDPIN_Msk (0x00000030UL) +#define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) +#define R_XSPI0_LPCTL0_XD1LEN_Msk (0x001F0000UL) +#define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) +#define R_XSPI0_LPCTL0_XD1VAL_Msk (0x00800000UL) +#define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) +#define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1F000000UL) +#define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) +#define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) +#define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) +#define R_XSPI0_LPCTL1_PATREQ_Msk (0x00000003UL) +#define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) +#define R_XSPI0_LPCTL1_CSSEL_Msk (0x00000008UL) +#define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) +#define R_XSPI0_LPCTL1_RSTREP_Msk (0x00000030UL) +#define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) +#define R_XSPI0_LPCTL1_RSTWID_Msk (0x00000700UL) +#define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) +#define R_XSPI0_LPCTL1_RSTSU_Msk (0x00007000UL) +#define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) +#define R_XSPI0_LIOCTL_WPCS0_Msk (0x00000001UL) +#define R_XSPI0_LIOCTL_WPCS0_Pos (0UL) +#define R_XSPI0_LIOCTL_WPCS1_Msk (0x00000002UL) +#define R_XSPI0_LIOCTL_WPCS1_Pos (1UL) +#define R_XSPI0_LIOCTL_RSTCS0_Msk (0x00010000UL) +#define R_XSPI0_LIOCTL_RSTCS0_Pos (16UL) +#define R_XSPI0_LIOCTL_RSTCS1_Msk (0x00020000UL) +#define R_XSPI0_LIOCTL_RSTCS1_Pos (17UL) +#define R_XSPI0_CSb_CCCTL0_CAEN_Msk (0x00000001UL) +#define R_XSPI0_CSb_CCCTL0_CAEN_Pos (0UL) +#define R_XSPI0_CSb_CCCTL0_CANOWR_Msk (0x00000002UL) +#define R_XSPI0_CSb_CCCTL0_CANOWR_Pos (1UL) +#define R_XSPI0_CSb_CCCTL0_CAITV_Msk (0x00001F00UL) +#define R_XSPI0_CSb_CCCTL0_CAITV_Pos (8UL) +#define R_XSPI0_CSb_CCCTL0_CASFTSTA_Msk (0x001F0000UL) +#define R_XSPI0_CSb_CCCTL0_CASFTSTA_Pos (16UL) +#define R_XSPI0_CSb_CCCTL0_CASFTEND_Msk (0x1F000000UL) +#define R_XSPI0_CSb_CCCTL0_CASFTEND_Pos (24UL) +#define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Msk (0x00000003UL) +#define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Pos (0UL) +#define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Msk (0x0000001CUL) +#define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Pos (2UL) +#define R_XSPI0_CSb_CCCTL1_CADATASIZE_Msk (0x000001E0UL) +#define R_XSPI0_CSb_CCCTL1_CADATASIZE_Pos (5UL) +#define R_XSPI0_CSb_CCCTL1_CAWRLATE_Msk (0x001F0000UL) +#define R_XSPI0_CSb_CCCTL1_CAWRLATE_Pos (16UL) +#define R_XSPI0_CSb_CCCTL1_CARDLATE_Msk (0x1F000000UL) +#define R_XSPI0_CSb_CCCTL1_CARDLATE_Pos (24UL) +#define R_XSPI0_CSb_CCCTL2_CAWRCMD_Msk (0x0000FFFFUL) +#define R_XSPI0_CSb_CCCTL2_CAWRCMD_Pos (0UL) +#define R_XSPI0_CSb_CCCTL2_CARDCMD_Msk (0xFFFF0000UL) +#define R_XSPI0_CSb_CCCTL2_CARDCMD_Pos (16UL) +#define R_XSPI0_CSb_CCCTL3_CAADD_Msk (0xFFFFFFFFUL) +#define R_XSPI0_CSb_CCCTL3_CAADD_Pos (0UL) +#define R_XSPI0_CSb_CCCTL4_CADATA_Msk (0xFFFFFFFFUL) +#define R_XSPI0_CSb_CCCTL4_CADATA_Pos (0UL) +#define R_XSPI0_CSb_CCCTL5_CADATA_Msk (0xFFFFFFFFUL) +#define R_XSPI0_CSb_CCCTL5_CADATA_Pos (0UL) +#define R_XSPI0_CSb_CCCTL6_CADATA_Msk (0xFFFFFFFFUL) +#define R_XSPI0_CSb_CCCTL6_CADATA_Pos (0UL) +#define R_XSPI0_CSb_CCCTL7_CADATA_Msk (0xFFFFFFFFUL) +#define R_XSPI0_CSb_CCCTL7_CADATA_Pos (0UL) +#define R_XSPI0_VERSTT_VER_Msk (0xFFFFFFFFUL) +#define R_XSPI0_VERSTT_VER_Pos (0UL) +#define R_XSPI0_COMSTT_MEMACC_Msk (0x00000001UL) +#define R_XSPI0_COMSTT_MEMACC_Pos (0UL) +#define R_XSPI0_COMSTT_PBUFNE_Msk (0x00000010UL) +#define R_XSPI0_COMSTT_PBUFNE_Pos (4UL) +#define R_XSPI0_COMSTT_WRBUFNE_Msk (0x00000040UL) +#define R_XSPI0_COMSTT_WRBUFNE_Pos (6UL) +#define R_XSPI0_CASTTCS_CASUC_Msk (0xFFFFFFFFUL) +#define R_XSPI0_CASTTCS_CASUC_Pos (0UL) +#define R_XSPI0_INTS_CMDCMP_Msk (0x00000001UL) +#define R_XSPI0_INTS_CMDCMP_Pos (0UL) +#define R_XSPI0_INTS_PATCMP_Msk (0x00000002UL) +#define R_XSPI0_INTS_PATCMP_Pos (1UL) +#define R_XSPI0_INTS_INICMP_Msk (0x00000004UL) +#define R_XSPI0_INTS_INICMP_Pos (2UL) +#define R_XSPI0_INTS_PERTO_Msk (0x00000008UL) +#define R_XSPI0_INTS_PERTO_Pos (3UL) +#define R_XSPI0_INTS_DSTOCS0_Msk (0x00000010UL) +#define R_XSPI0_INTS_DSTOCS0_Pos (4UL) +#define R_XSPI0_INTS_DSTOCS1_Msk (0x00000020UL) +#define R_XSPI0_INTS_DSTOCS1_Pos (5UL) +#define R_XSPI0_INTS_BUSERR_Msk (0x00100000UL) +#define R_XSPI0_INTS_BUSERR_Pos (20UL) +#define R_XSPI0_INTS_CAFAILCS0_Msk (0x10000000UL) +#define R_XSPI0_INTS_CAFAILCS0_Pos (28UL) +#define R_XSPI0_INTS_CAFAILCS1_Msk (0x20000000UL) +#define R_XSPI0_INTS_CAFAILCS1_Pos (29UL) +#define R_XSPI0_INTS_CASUCCS0_Msk (0x40000000UL) +#define R_XSPI0_INTS_CASUCCS0_Pos (30UL) +#define R_XSPI0_INTS_CASUCCS1_Msk (0x80000000UL) +#define R_XSPI0_INTS_CASUCCS1_Pos (31UL) +#define R_XSPI0_INTC_CMDCMPC_Msk (0x00000001UL) +#define R_XSPI0_INTC_CMDCMPC_Pos (0UL) +#define R_XSPI0_INTC_PATCMPC_Msk (0x00000002UL) +#define R_XSPI0_INTC_PATCMPC_Pos (1UL) +#define R_XSPI0_INTC_INICMPC_Msk (0x00000004UL) +#define R_XSPI0_INTC_INICMPC_Pos (2UL) +#define R_XSPI0_INTC_PERTOC_Msk (0x00000008UL) +#define R_XSPI0_INTC_PERTOC_Pos (3UL) +#define R_XSPI0_INTC_DSTOCS0C_Msk (0x00000010UL) +#define R_XSPI0_INTC_DSTOCS0C_Pos (4UL) +#define R_XSPI0_INTC_DSTOCS1C_Msk (0x00000020UL) +#define R_XSPI0_INTC_DSTOCS1C_Pos (5UL) +#define R_XSPI0_INTC_BUSERRC_Msk (0x00100000UL) +#define R_XSPI0_INTC_BUSERRC_Pos (20UL) +#define R_XSPI0_INTC_CAFAILCS0C_Msk (0x10000000UL) +#define R_XSPI0_INTC_CAFAILCS0C_Pos (28UL) +#define R_XSPI0_INTC_CAFAILCS1C_Msk (0x20000000UL) +#define R_XSPI0_INTC_CAFAILCS1C_Pos (29UL) +#define R_XSPI0_INTC_CASUCCS0C_Msk (0x40000000UL) +#define R_XSPI0_INTC_CASUCCS0C_Pos (30UL) +#define R_XSPI0_INTC_CASUCCS1C_Msk (0x80000000UL) +#define R_XSPI0_INTC_CASUCCS1C_Pos (31UL) +#define R_XSPI0_INTE_CMDCMPE_Msk (0x00000001UL) +#define R_XSPI0_INTE_CMDCMPE_Pos (0UL) +#define R_XSPI0_INTE_PATCMPE_Msk (0x00000002UL) +#define R_XSPI0_INTE_PATCMPE_Pos (1UL) +#define R_XSPI0_INTE_INICMPE_Msk (0x00000004UL) +#define R_XSPI0_INTE_INICMPE_Pos (2UL) +#define R_XSPI0_INTE_PERTOE_Msk (0x00000008UL) +#define R_XSPI0_INTE_PERTOE_Pos (3UL) +#define R_XSPI0_INTE_DSTOCS0E_Msk (0x00000010UL) +#define R_XSPI0_INTE_DSTOCS0E_Pos (4UL) +#define R_XSPI0_INTE_DSTOCS1E_Msk (0x00000020UL) +#define R_XSPI0_INTE_DSTOCS1E_Pos (5UL) +#define R_XSPI0_INTE_BUSERRE_Msk (0x00100000UL) +#define R_XSPI0_INTE_BUSERRE_Pos (20UL) +#define R_XSPI0_INTE_CAFAILCS0E_Msk (0x10000000UL) +#define R_XSPI0_INTE_CAFAILCS0E_Pos (28UL) +#define R_XSPI0_INTE_CAFAILCS1E_Msk (0x20000000UL) +#define R_XSPI0_INTE_CAFAILCS1E_Pos (29UL) +#define R_XSPI0_INTE_CASUCCS0E_Msk (0x40000000UL) +#define R_XSPI0_INTE_CASUCCS0E_Pos (30UL) +#define R_XSPI0_INTE_CASUCCS1E_Msk (0x80000000UL) +#define R_XSPI0_INTE_CASUCCS1E_Pos (31UL) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefine.h new file mode 100644 index 00000000..ef14d0ee --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefine.h @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : iodefine.h + * Version : 1.00 + * Description : iodefine header + *********************************************************************************************************************/ + +#ifndef __IODEFINE_HEADER__ +#define __IODEFINE_HEADER__ + +#include "iodefines/adc_c_iodefine.h" +#include "iodefines/canfd_iodefine.h" +#include "iodefines/cpg_iodefine.h" +#include "iodefines/dmac_b_iodefine.h" +#include "iodefines/gpio_iodefine.h" +#include "iodefines/gpt_iodefine.h" +#include "iodefines/gtm_iodefine.h" +#include "iodefines/intc_im33_iodefine.h" +#include "iodefines/mhu_iodefine.h" +#include "iodefines/poeg_iodefine.h" +#include "iodefines/riic_iodefine.h" +#include "iodefines/rspi_iodefine.h" +#include "iodefines/scifa_iodefine.h" +#include "iodefines/ssi_iodefine.h" +#include "iodefines/sysc_iodefine.h" +#include "iodefines/tsu_iodefine.h" +#include "iodefines/tzc_iodefine.h" +#include "iodefines/wdt_iodefine.h" +#include "iodefines/xspi_iodefine.h" + +#ifdef BSP_OVERRIDE_REG_HEADER_IOPORT + #include BSP_OVERRIDE_REG_HEADER_IOPORT +#endif + +#endif /* __IODEFINE_HEADER__ */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/adc_c_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/adc_c_iodefine.h new file mode 100644 index 00000000..dd067f8f --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/adc_c_iodefine.h @@ -0,0 +1,377 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : adc_c_iodefine.h + * Version : 1.00 + * Description : IO define file for adc_c. + *********************************************************************************************************************/ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef ADC_C_IODEFINE_H +#define ADC_C_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t ADM0; + struct + { + __IOM uint32_t ADCE : 1; + __IM uint32_t ADBSY : 1; + __IOM uint32_t PWDWNB : 1; + uint32_t : 12; + __IOM uint32_t SRESB : 1; + uint32_t : 16; + } ADM0_b; + }; + union + { + __IOM uint32_t ADM1; + struct + { + __IOM uint32_t TRG : 1; + __IOM uint32_t TRGIN : 1; + __IOM uint32_t MS : 1; + __IOM uint32_t RPS : 1; + __IOM uint32_t BS : 1; + uint32_t : 7; + __IOM uint32_t EGA : 2; + uint32_t : 2; + __IM uint32_t TRGEN : 6; + uint32_t : 10; + } ADM1_b; + }; + union + { + __IOM uint32_t ADM2; + struct + { + __IOM uint32_t CHSEL : 9; + uint32_t : 23; + } ADM2_b; + }; + union + { + __IOM uint32_t ADM3; + struct + { + __IOM uint32_t ADSMP : 8; + uint32_t : 8; + __IOM uint32_t ADCMP : 8; + __IOM uint32_t ADIL : 8; + } ADM3_b; + }; + union + { + __IOM uint32_t TSUMODE; + struct + { + uint32_t : 1; + __IOM uint32_t TSUEN : 1; + uint32_t : 30; + } TSUMODE_b; + }; + __IM uint8_t RESERVED[12]; + union + { + __IOM uint32_t ADINT; + struct + { + __IOM uint32_t INTEN : 12; + uint32_t : 4; + __IOM uint32_t CSEEN : 1; + uint32_t : 14; + __IM uint32_t INTS : 1; + } ADINT_b; + }; + union + { + __IOM uint32_t ADSTS; + struct + { + __IOM uint32_t INTST : 9; + uint32_t : 7; + __IOM uint32_t CSEST : 1; + uint32_t : 14; + __IOM uint32_t TRGS : 1; + } ADSTS_b; + }; + __IM uint8_t RESERVED1[4]; + union + { + __IOM uint32_t ADFIL; + struct + { + __IOM uint32_t FILONOFF : 1; + uint32_t : 3; + __IOM uint32_t FILNUM : 2; + uint32_t : 26; + } ADFIL_b; + }; + union + { + __IM uint32_t ADCR0; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR0_b; + }; + union + { + __IM uint32_t ADCR1; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR1_b; + }; + union + { + __IM uint32_t ADCR2; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR2_b; + }; + union + { + __IM uint32_t ADCR3; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR3_b; + }; + union + { + __IM uint32_t ADCR4; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR4_b; + }; + union + { + __IM uint32_t ADCR5; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR5_b; + }; + union + { + __IM uint32_t ADCR6; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR6_b; + }; + union + { + __IM uint32_t ADCR7; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR7_b; + }; + union + { + __IM uint32_t ADCR8; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR8_b; + }; + union + { + __IM uint32_t ADCR9; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR9_b; + }; + union + { + __IM uint32_t ADCR10; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR10_b; + }; + union + { + __IM uint32_t ADCR11; + struct + { + __IM uint32_t AD0 : 1; + __IM uint32_t AD1 : 1; + __IM uint32_t AD2 : 1; + __IM uint32_t AD3 : 1; + __IM uint32_t AD4 : 1; + __IM uint32_t AD5 : 1; + __IM uint32_t AD6 : 1; + __IM uint32_t AD7 : 1; + __IM uint32_t AD8 : 1; + __IM uint32_t AD9 : 1; + __IM uint32_t AD10 : 1; + __IM uint32_t AD11 : 1; + uint32_t : 20; + } ADCR11_b; + }; +} R_ADC_C_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_ADC_C_BASE 0x40058000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_ADC_C ((R_ADC_C_Type *) R_ADC_C_BASE) + +#endif /* ADC_C_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/canfd_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/canfd_iodefine.h new file mode 100644 index 00000000..7838d54e --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/canfd_iodefine.h @@ -0,0 +1,1699 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : canfd_iodefine.h + * Version : 1.00 + * Description : IO define file for canfd. + *********************************************************************************************************************/ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef CANFD_IODEFINE_H +#define CANFD_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ + __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ + __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ + uint32_t : 2; + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + uint32_t : 2; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint8_t RESERVED[4]; + + union + { + __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ + + struct + { + __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ + uint32_t : 7; + __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ + uint32_t : 23; + } BLCT_b; + }; + + union + { + __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ + } BLSTS_b; + }; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00001800) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00001804) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00001808) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination + * 0 */ + __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination + * 1 */ + __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination + * 2 */ + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 7; /*!< [14..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000180C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 18; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00008000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 5; + __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00008004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint8_t RESERVED[52]; +} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint8_t RESERVED[52]; +} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry Enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint8_t RESERVED[52]; +} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + uint32_t : 28; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint8_t RESERVED[52]; +} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) + */ + +typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ + + __IM uint8_t RESERVED[96]; + + union + { + __IM uint32_t CFDGIPV; /*!< (@ 0x00000080) Global IP Version Register */ + + struct + { + __IOM uint32_t IPV : 8; /*!< [7..0] IP Version */ + __IOM uint32_t IPT : 2; /*!< [9..8] IP Type */ + uint32_t : 6; + __IOM uint32_t PSI : 14; /*!< [29..16] Parameter Status Information */ + uint32_t : 2; + } CFDGIPV_b; + }; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + __IOM uint32_t QOWEIE : 1; /*!< [12..12] TXQ Message Overwrite Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ + uint32_t : 1; + __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ + __IM uint32_t MOWES : 1; /*!< [7..7] Message Overwrite Error Status */ + uint32_t : 8; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ + uint32_t : 14; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 7; /*!< [6..0] Acceptance Filter List Page Number */ + uint32_t : 1; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + __IM uint8_t RESERVED1[12]; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNS : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + __IM uint8_t RESERVED2[12]; + + union + { + __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ + uint32_t : 15; + } CFDRFCC_b[8]; + }; + + union + { + __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ + uint32_t : 15; + } CFDRFSTS_b[8]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[8]; + }; + + union + { + __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[6]; + }; + __IM uint8_t RESERVED3[72]; + + union + { + __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement + * Registers */ + + struct + { + __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ + __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ + __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ + uint32_t : 7; + __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ + uint32_t : 15; + } CFDCFCCE_b[6]; + }; + __IM uint8_t RESERVED4[72]; + + union + { + __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ + __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ + __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ + uint32_t : 5; + __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ + uint32_t : 7; + } CFDCFSTS_b[6]; + }; + __IM uint8_t RESERVED5[72]; + + union + { + __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[6]; + }; + __IM uint8_t RESERVED6[72]; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ + __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ + uint32_t : 18; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ + __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ + uint32_t : 18; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ + __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ + uint32_t : 18; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 8; + __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ + uint32_t : 8; + } CFDRFISTS_b; + }; + + union + { + __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFRISTS_b; + }; + + union + { + __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ + + struct + { + __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ + uint32_t : 26; + } CFDCFMOWSTS_b; + }; + + union + { + __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ + + struct + { + __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ + __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ + uint32_t : 18; + } CFDFFFSTS_b; + }; + __IM uint8_t RESERVED7[8]; + + union + { + __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[128]; + }; + __IM uint8_t RESERVED8[1152]; + + union + { + __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[128]; + }; + __IM uint8_t RESERVED9[1152]; + + union + { + __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t TMTRSTS : 16; /*!< [15..0] TX Message Buffer Transmission Request Status */ + uint32_t : 16; + } CFDTMTRSTS_b[4]; + }; + __IM uint8_t RESERVED10[144]; + + union + { + __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t TMTARSTS : 16; /*!< [15..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 16; + } CFDTMTARSTS_b[4]; + }; + __IM uint8_t RESERVED11[144]; + + union + { + __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t TMTCSTS : 16; /*!< [15..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 16; + } CFDTMTCSTS_b[4]; + }; + __IM uint8_t RESERVED12[144]; + + union + { + __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t TMTASTS : 16; /*!< [15..0] TX Message Buffer Transmission abort Status */ + uint32_t : 16; + } CFDTMTASTS_b[4]; + }; + __IM uint8_t RESERVED13[144]; + + union + { + __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIE : 16; /*!< [15..0] TX Message Buffer Interrupt Enable */ + uint32_t : 16; + } CFDTMIEC_b[4]; + }; + __IM uint8_t RESERVED14[160]; + + union + { + __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC0_b[2]; + }; + __IM uint8_t RESERVED15[24]; + + union + { + __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS0_b[2]; + }; + __IM uint8_t RESERVED16[24]; + + union + { + __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[2]; + }; + __IM uint8_t RESERVED17[24]; + + union + { + __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC1_b[2]; + }; + __IM uint8_t RESERVED18[24]; + + union + { + __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS1_b[2]; + }; + __IM uint8_t RESERVED19[24]; + + union + { + __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR1_b[2]; + }; + __IM uint8_t RESERVED20[24]; + + union + { + __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC2_b[2]; + }; + __IM uint8_t RESERVED21[24]; + + union + { + __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS2_b[2]; + }; + __IM uint8_t RESERVED22[24]; + + union + { + __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR2_b[2]; + }; + __IM uint8_t RESERVED23[24]; + + union + { + __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 1; + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 5; + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC3_b[2]; + }; + __IM uint8_t RESERVED24[24]; + + union + { + __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 4; + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + uint32_t : 1; + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS3_b[2]; + }; + __IM uint8_t RESERVED25[24]; + + union + { + __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR3_b[2]; + }; + __IM uint8_t RESERVED26[24]; + + union + { + __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ + + struct + { + __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ + uint32_t : 24; + } CFDTXQESTS_b; + }; + + union + { + __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ + uint32_t : 25; + } CFDTXQFISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ + + struct + { + __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ + uint32_t : 25; + } CFDTXQMSTS_b; + }; + + union + { + __IOM uint32_t CFDTXQOWSTS; /*!< (@ 0x0000118C) TX Queue Message Overwrite Status Register */ + + struct + { + __IM uint32_t TXQ0OW : 4; /*!< [3..0] TXQ message Overwrite Status for channel 0 */ + __IM uint32_t TXQ1OW : 4; /*!< [7..4] TXQ message Overwrite Status for channel 1 */ + uint32_t : 24; + } CFDTXQOWSTS_b; + }; + + union + { + __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQOFTISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 25; + } CFDTXQOFRISTS_b; + }; + + union + { + __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ + + struct + { + __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ + __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQFSTS_b; + }; + __IM uint8_t RESERVED27[96]; + + union + { + __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ + uint32_t : 20; + } CFDTHLCC_b[2]; + }; + __IM uint8_t RESERVED28[24]; + + union + { + __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[2]; + }; + __IM uint8_t RESERVED29[24]; + + union + { + __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[2]; + }; + __IM uint8_t RESERVED30[184]; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel + * 0 */ + __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel + * 0 */ + uint32_t : 1; + __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ + __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ + __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ + __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ + __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ + __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel + * 1 */ + __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel + * 1 */ + uint32_t : 17; + } CFDGTINTSTS0_b; + }; + + __IM uint8_t RESERVED31[4]; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ + + struct + { + __IOM uint32_t C0ICBCE : 1; /*!< [0..0] Channel 0 Internal CAN Bus Communication Test Mode Enable */ + __IOM uint32_t C1ICBCE : 1; /*!< [1..1] Channel 1 Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 14; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ + + struct + { + __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 1; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + __IM uint8_t RESERVED32[4]; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint8_t RESERVED33[4]; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint8_t RESERVED34[16]; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ + __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ + __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ + __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ + __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ + __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ + uint32_t : 22; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ + __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ + __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ + __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ + __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ + __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel + * 1 */ + uint32_t : 22; + } CFDCDTSTS_b; + }; + __IM uint8_t RESERVED35[8]; + + union + { + __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ + + struct + { + __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ + __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ + uint32_t : 6; + __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ + __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel + * 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTCT_b; + }; + + union + { + __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ + + struct + { + __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ + __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ + uint32_t : 6; + __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ + __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTSTS_b; + }; + __IM uint8_t RESERVED36[8]; + + union + { + __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ + + struct + { + __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ + uint32_t : 1; + __IM uint32_t BQFIF : 2; /*!< [5..4] Borrowed TXQ Full Interrupt Flag Channel n */ + uint32_t : 2; + __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ + uint32_t : 1; + __IM uint32_t BQOFRIF : 2; /*!< [13..12] Borrowed TXQ One Frame RX Interrupt Flag Channel n */ + uint32_t : 2; + __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ + uint32_t : 1; + __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ + uint32_t : 1; + } CFDGRINTSTS_b[2]; + }; + __IM uint8_t RESERVED37[40]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + + union + { + __IOM uint32_t CFDGFCMC; /*!< (@ 0x00001384) Global Flexible CAN Mode Configuration Register */ + + struct + { + __IOM uint32_t FLXC0 : 1; /*!< [0..0] Flexible CAN Mode between Channel 0 and Channel 1 */ + uint32_t : 31; + } CFDGFCMC_b; + }; + __IM uint8_t RESERVED38[4]; + + union + { + __IOM uint32_t CFDGFTBAC; /*!< (@ 0x0000138C) Global Flexible Transmission Buffer Assignment Configuration Register */ + + struct + { + __IOM uint32_t FLXMB0 : 4; /*!< [3..0] Flexible Transmission Buffer Assignment between Channel 0 and Channel 1 */ + uint32_t : 28; + } CFDGFTBAC_b; + }; + __IM uint8_t RESERVED39[112]; + + __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ + __IM uint8_t RESERVED40[960]; + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ + __IM uint8_t RESERVED41[1792]; + __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ + __IM uint8_t RESERVED42[12288]; + __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ + __IM uint8_t RESERVED43[6400]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ + __IM uint8_t RESERVED44[1008]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint8_t RESERVED45[31488]; + __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ +} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_CANFD_BASE 0x400C0000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/cpg_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/cpg_iodefine.h new file mode 100644 index 00000000..39e5cdb2 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/cpg_iodefine.h @@ -0,0 +1,3815 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : cpg_iodefine.h + * Version : 1.00 + * Description : IO define file for cpg. + *********************************************************************************************************************/ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef CPG_IODEFINE_H +#define CPG_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t CPG_PLL1_STBY; + struct + { + __IOM uint32_t RESETB : 1; + uint32_t : 1; + __IOM uint32_t SSCG_EN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_MODE : 1; + uint32_t : 11; + __IOM uint32_t RESETB_WEN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_EN_WEN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_MODE_WEN : 1; + uint32_t : 11; + } CPG_PLL1_STBY_b; + }; + union + { + __IOM uint32_t CPG_PLL1_CLK1; + struct + { + __IOM uint32_t RANGESEL : 1; + __IOM uint32_t DIV_NF : 12; + __IOM uint32_t DIV_NI : 9; + __IOM uint32_t DIV_M : 4; + __IOM uint32_t DIV_P : 3; + uint32_t : 3; + } CPG_PLL1_CLK1_b; + }; + union + { + __IOM uint32_t CPG_PLL1_CLK2; + struct + { + __IOM uint32_t SELMPERCENT : 3; + __IOM uint32_t SELMFREQ : 5; + uint32_t : 24; + } CPG_PLL1_CLK2_b; + }; + union + { + __IM uint32_t CPG_PLL1_MON; + struct + { + __IM uint32_t PLL1_RESETB : 1; + uint32_t : 3; + __IM uint32_t PLL1_LOCK : 1; + uint32_t : 27; + } CPG_PLL1_MON_b; + }; + __IM uint8_t RESERVED[12]; + union + { + __IM uint32_t CPG_PLL2_MON; + struct + { + __IM uint32_t PLL2_RESETB : 1; + uint32_t : 3; + __IM uint32_t PLL2_LOCK : 1; + uint32_t : 27; + } CPG_PLL2_MON_b; + }; + __IM uint8_t RESERVED1[12]; + union + { + __IM uint32_t CPG_PLL3_MON; + struct + { + __IM uint32_t PLL3_RESETB : 1; + uint32_t : 3; + __IM uint32_t PLL3_LOCK : 1; + uint32_t : 27; + } CPG_PLL3_MON_b; + }; + union + { + __IOM uint32_t CPG_PLL4_STBY; + struct + { + __IOM uint32_t RESETB : 1; + uint32_t : 1; + __IOM uint32_t SSCG_EN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_MODE : 1; + uint32_t : 11; + __IOM uint32_t RESETB_WEN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_EN_WEN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_MODE_WEN : 1; + uint32_t : 11; + } CPG_PLL4_STBY_b; + }; + union + { + __IOM uint32_t CPG_PLL4_CLK1; + struct + { + __IOM uint32_t RANGESEL : 1; + __IOM uint32_t DIV_NF : 12; + __IOM uint32_t DIV_NI : 9; + __IOM uint32_t DIV_M : 4; + __IOM uint32_t DIV_P : 3; + uint32_t : 3; + } CPG_PLL4_CLK1_b; + }; + union + { + __IOM uint32_t CPG_PLL4_CLK2; + struct + { + __IOM uint32_t SELMPERCENT : 3; + __IOM uint32_t SELMFREQ : 5; + uint32_t : 24; + } CPG_PLL4_CLK2_b; + }; + union + { + __IM uint32_t CPG_PLL4_MON; + struct + { + __IM uint32_t PLL4_RESETB : 1; + uint32_t : 3; + __IM uint32_t PLL4_LOCK : 1; + uint32_t : 27; + } CPG_PLL4_MON_b; + }; + __IM uint8_t RESERVED2[16]; + union + { + __IOM uint32_t CPG_PLL6_STBY; + struct + { + __IOM uint32_t RESETB : 1; + uint32_t : 1; + __IOM uint32_t SSCG_EN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_MODE : 1; + uint32_t : 11; + __IOM uint32_t RESETB_WEN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_EN_WEN : 1; + uint32_t : 1; + __IOM uint32_t SSCG_MODE_WEN : 1; + uint32_t : 11; + } CPG_PLL6_STBY_b; + }; + union + { + __IOM uint32_t CPG_PLL6_CLK1; + struct + { + __IOM uint32_t RANGESEL : 1; + __IOM uint32_t DIV_NF : 12; + __IOM uint32_t DIV_NI : 9; + __IOM uint32_t DIV_M : 4; + __IOM uint32_t DIV_P : 3; + uint32_t : 3; + } CPG_PLL6_CLK1_b; + }; + union + { + __IOM uint32_t CPG_PLL6_CLK2; + struct + { + __IOM uint32_t SELMPERCENT : 3; + __IOM uint32_t SELMFREQ : 5; + uint32_t : 24; + } CPG_PLL6_CLK2_b; + }; + union + { + __IM uint32_t CPG_PLL6_MON; + struct + { + __IM uint32_t PLL6_RESETB : 1; + uint32_t : 3; + __IM uint32_t PLL6_LOCK : 1; + uint32_t : 27; + } CPG_PLL6_MON_b; + }; + __IM uint8_t RESERVED3[160]; + union + { + __IOM uint32_t CPG_PLL1_SETTING; + struct + { + __IOM uint32_t SEL_PLL1 : 1; + uint32_t : 15; + __IOM uint32_t SEL_PLL1_WEN : 1; + uint32_t : 15; + } CPG_PLL1_SETTING_b; + }; + union + { + __IM uint32_t CPG_OTPPLL0_MON; + struct + { + __IM uint32_t OTP0_MON : 1; + __IM uint32_t OTP1_MON : 1; + __IM uint32_t OTP2_MON : 1; + __IM uint32_t OTP3_MON : 1; + __IM uint32_t OTP4_MON : 1; + __IM uint32_t OTP5_MON : 1; + __IM uint32_t OTP6_MON : 1; + __IM uint32_t OTP7_MON : 1; + __IM uint32_t OTP8_MON : 1; + __IM uint32_t OTP9_MON : 1; + __IM uint32_t OTP10_MON : 1; + __IM uint32_t OTP11_MON : 1; + __IM uint32_t OTP12_MON : 1; + __IM uint32_t OTP13_MON : 1; + __IM uint32_t OTP14_MON : 1; + __IM uint32_t OTP15_MON : 1; + __IM uint32_t OTP16_MON : 1; + __IM uint32_t OTP17_MON : 1; + __IM uint32_t OTP18_MON : 1; + __IM uint32_t OTP19_MON : 1; + __IM uint32_t OTP20_MON : 1; + __IM uint32_t OTP21_MON : 1; + __IM uint32_t OTP22_MON : 1; + __IM uint32_t OTP23_MON : 1; + __IM uint32_t OTP24_MON : 1; + __IM uint32_t OTP25_MON : 1; + __IM uint32_t OTP26_MON : 1; + __IM uint32_t OTP27_MON : 1; + __IM uint32_t OTP28_MON : 1; + __IM uint32_t OTP29_MON : 1; + __IM uint32_t OTP30_MON : 1; + __IM uint32_t OTP31_MON : 1; + } CPG_OTPPLL0_MON_b; + }; + union + { + __IM uint32_t CPG_OTPPLL1_MON; + struct + { + __IM uint32_t OTP0_MON : 1; + __IM uint32_t OTP1_MON : 1; + __IM uint32_t OTP2_MON : 1; + __IM uint32_t OTP3_MON : 1; + __IM uint32_t OTP4_MON : 1; + __IM uint32_t OTP5_MON : 1; + __IM uint32_t OTP6_MON : 1; + __IM uint32_t OTP7_MON : 1; + __IM uint32_t OTP8_MON : 1; + __IM uint32_t OTP9_MON : 1; + __IM uint32_t OTP10_MON : 1; + __IM uint32_t OTP11_MON : 1; + __IM uint32_t OTP12_MON : 1; + __IM uint32_t OTP13_MON : 1; + __IM uint32_t OTP14_MON : 1; + __IM uint32_t OTP15_MON : 1; + __IM uint32_t OTP16_MON : 1; + __IM uint32_t OTP17_MON : 1; + __IM uint32_t OTP18_MON : 1; + __IM uint32_t OTP19_MON : 1; + __IM uint32_t OTP20_MON : 1; + __IM uint32_t OTP21_MON : 1; + __IM uint32_t OTP22_MON : 1; + __IM uint32_t OTP23_MON : 1; + __IM uint32_t OTP24_MON : 1; + __IM uint32_t OTP25_MON : 1; + __IM uint32_t OTP26_MON : 1; + __IM uint32_t OTP27_MON : 1; + __IM uint32_t OTP28_MON : 1; + __IM uint32_t OTP29_MON : 1; + __IM uint32_t OTP30_MON : 1; + __IM uint32_t OTP31_MON : 1; + } CPG_OTPPLL1_MON_b; + }; + union + { + __IM uint32_t CPG_OTPPLL2_MON; + struct + { + __IM uint32_t OTP0_MON : 1; + __IM uint32_t OTP1_MON : 1; + __IM uint32_t OTP2_MON : 1; + __IM uint32_t OTP3_MON : 1; + __IM uint32_t OTP4_MON : 1; + __IM uint32_t OTP5_MON : 1; + __IM uint32_t OTP6_MON : 1; + __IM uint32_t OTP7_MON : 1; + __IM uint32_t OTP8_MON : 1; + __IM uint32_t OTP9_MON : 1; + __IM uint32_t OTP10_MON : 1; + __IM uint32_t OTP11_MON : 1; + __IM uint32_t OTP12_MON : 1; + __IM uint32_t OTP13_MON : 1; + __IM uint32_t OTP14_MON : 1; + __IM uint32_t OTP15_MON : 1; + __IM uint32_t OTP16_MON : 1; + __IM uint32_t OTP17_MON : 1; + __IM uint32_t OTP18_MON : 1; + __IM uint32_t OTP19_MON : 1; + __IM uint32_t OTP20_MON : 1; + __IM uint32_t OTP21_MON : 1; + __IM uint32_t OTP22_MON : 1; + __IM uint32_t OTP23_MON : 1; + __IM uint32_t OTP24_MON : 1; + __IM uint32_t OTP25_MON : 1; + __IM uint32_t OTP26_MON : 1; + __IM uint32_t OTP27_MON : 1; + __IM uint32_t OTP28_MON : 1; + __IM uint32_t OTP29_MON : 1; + __IM uint32_t OTP30_MON : 1; + __IM uint32_t OTP31_MON : 1; + } CPG_OTPPLL2_MON_b; + }; + __IM uint8_t RESERVED4[240]; + union + { + __IOM uint32_t CPG_PL1_DDIV; + struct + { + __IOM uint32_t DIVPL1_SET : 2; + uint32_t : 14; + __IOM uint32_t DIV_PLL1SET_WEN : 1; + uint32_t : 15; + } CPG_PL1_DDIV_b; + }; + union + { + __IOM uint32_t CPG_PL2_DDIV; + struct + { + uint32_t : 4; + __IOM uint32_t DIVPL2B_SET : 3; + uint32_t : 13; + __IOM uint32_t DIV_PLL2_B_WEN : 1; + uint32_t : 11; + } CPG_PL2_DDIV_b; + }; + union + { + __IOM uint32_t CPG_PL3_DDIV; + struct + { + __IOM uint32_t DIVPL3A_SET : 3; + uint32_t : 1; + __IOM uint32_t DIVPL3B_SET : 3; + uint32_t : 1; + __IOM uint32_t DIVPL3C_SET : 3; + uint32_t : 5; + __IOM uint32_t DIV_PLL3_A_WEN : 1; + uint32_t : 3; + __IOM uint32_t DIV_PLL3_B_WEN : 1; + uint32_t : 3; + __IOM uint32_t DIV_PLL3_C_WEN : 1; + uint32_t : 7; + } CPG_PL3_DDIV_b; + }; + __IM uint8_t RESERVED5[8]; + union + { + __IOM uint32_t CPG_PL6_DDIV; + struct + { + __IOM uint32_t DIVPL6A_SET : 3; + uint32_t : 1; + __IOM uint32_t DIVPL6B_SET : 3; + uint32_t : 9; + __IOM uint32_t DIV_PLL6_A_WEN : 1; + uint32_t : 3; + __IOM uint32_t DIV_PLL6_B_WEN : 1; + uint32_t : 11; + } CPG_PL6_DDIV_b; + }; + union + { + __IOM uint32_t CPG_SDHI_DDIV; + struct + { + __IOM uint32_t DIVSDHI0_SET : 1; + uint32_t : 3; + __IOM uint32_t DIVSDHI1_SET : 1; + uint32_t : 3; + __IOM uint32_t DIVSDHI2_SET : 1; + uint32_t : 7; + __IOM uint32_t DIVSDHI0_WEN : 1; + uint32_t : 3; + __IOM uint32_t DIVSDHI1_WEN : 1; + uint32_t : 3; + __IOM uint32_t DIVSDHI2_WEN : 1; + uint32_t : 7; + } CPG_SDHI_DDIV_b; + }; + union + { + __IOM uint32_t CPG_OCTA_DDIV; + struct + { + __IOM uint32_t DIVOCTA_SET : 3; + uint32_t : 13; + __IOM uint32_t DIVOCTA_WEN : 1; + uint32_t : 15; + } CPG_OCTA_DDIV_b; + }; + union + { + __IOM uint32_t CPG_SPI_DDIV; + struct + { + __IOM uint32_t DIVSPI_SET : 3; + uint32_t : 13; + __IOM uint32_t DIVSPI_WEN : 1; + uint32_t : 15; + } CPG_SPI_DDIV_b; + }; + __IM uint8_t RESERVED6[28]; + union + { + __IOM uint32_t CPG_PLL_DSEL; + struct + { + uint32_t : 6; + __IOM uint32_t SELPL4_SET : 1; + uint32_t : 15; + __IOM uint32_t SELPL4_WEN : 1; + uint32_t : 9; + } CPG_PLL_DSEL_b; + }; + union + { + __IOM uint32_t CPG_SDHI_DSEL; + struct + { + __IOM uint32_t SEL_SDHI0_SET : 2; + uint32_t : 2; + __IOM uint32_t SEL_SDHI1_SET : 2; + uint32_t : 2; + __IOM uint32_t SEL_SDHI2_SET : 2; + uint32_t : 6; + __IOM uint32_t SEL_SDHI0_WEN : 1; + uint32_t : 3; + __IOM uint32_t SEL_SDHI1_WEN : 1; + uint32_t : 3; + __IOM uint32_t SEL_SDHI2_WEN : 1; + uint32_t : 7; + } CPG_SDHI_DSEL_b; + }; + __IM uint8_t RESERVED7[56]; + union + { + __IM uint32_t CPG_CLKDIVSTATUS; + struct + { + __IM uint32_t DIVPL1_STS : 1; + uint32_t : 4; + __IM uint32_t DIVPL2B_STS : 1; + uint32_t : 2; + __IM uint32_t DIVPL3A_STS : 1; + __IM uint32_t DIVPL3B_STS : 1; + __IM uint32_t DIVPL3C_STS : 1; + uint32_t : 9; + __IM uint32_t DIVPL6A_STS : 1; + __IM uint32_t DIVPL6B_STS : 1; + uint32_t : 2; + __IM uint32_t DIVSDHI0_STS : 1; + __IM uint32_t DIVSDHI1_STS : 1; + __IM uint32_t DIVSDHI2_STS : 1; + uint32_t : 1; + __IM uint32_t DIVOCTA_STS : 1; + __IM uint32_t DIVSPI_STS : 1; + uint32_t : 2; + } CPG_CLKDIVSTATUS_b; + }; + union + { + __IM uint32_t CPG_CLKSELSTATUS; + struct + { + __IM uint32_t SELPL1_STS : 1; + uint32_t : 1; + __IM uint32_t SELPL2_STS : 1; + uint32_t : 1; + __IM uint32_t SELPL3_STS : 1; + uint32_t : 1; + __IM uint32_t SELPL4_STS : 1; + uint32_t : 3; + __IM uint32_t SELPL6_STS : 1; + uint32_t : 5; + __IM uint32_t SELSDHI0_STS : 1; + __IM uint32_t SELSDHI1_STS : 1; + __IM uint32_t SELSDHI2_STS : 1; + uint32_t : 13; + } CPG_CLKSELSTATUS_b; + }; + __IM uint8_t RESERVED8[376]; + union + { + __IOM uint32_t CPG_OCTA_SSEL; + struct + { + __IOM uint32_t SELOCTA_SET : 2; + uint32_t : 14; + __IOM uint32_t SELOCTA_WEN : 1; + uint32_t : 15; + } CPG_OCTA_SSEL_b; + }; + union + { + __IOM uint32_t CPG_SPI_SSEL; + struct + { + __IOM uint32_t SELSPI_SET : 2; + uint32_t : 14; + __IOM uint32_t SELSPI_WEN : 1; + uint32_t : 15; + } CPG_SPI_SSEL_b; + }; + __IM uint8_t RESERVED9[248]; + union + { + __IOM uint32_t CPG_CLKON_CA55; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + uint32_t : 10; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + uint32_t : 10; + } CPG_CLKON_CA55_b; + }; + union + { + __IOM uint32_t CPG_CLKON_CM33; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ON : 1; + __IOM uint32_t CLK9_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ONWEN : 1; + __IOM uint32_t CLK9_ONWEN : 1; + uint32_t : 6; + } CPG_CLKON_CM33_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SRAM_ACPU; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + uint32_t : 13; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + uint32_t : 13; + } CPG_CLKON_SRAM_ACPU_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SRAM_MCPU; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_SRAM_MCPU_b; + }; + __IM uint8_t RESERVED10[4]; + union + { + __IOM uint32_t CPG_CLKON_GIC600; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_GIC600_b; + }; + union + { + __IOM uint32_t CPG_CLKON_IA55; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_IA55_b; + }; + union + { + __IOM uint32_t CPG_CLKON_IM33; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ON : 1; + __IOM uint32_t CLK9_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ONWEN : 1; + __IOM uint32_t CLK9_ONWEN : 1; + uint32_t : 6; + } CPG_CLKON_IM33_b; + }; + union + { + __IOM uint32_t CPG_CLKON_MHU; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_MHU_b; + }; + union + { + __IOM uint32_t CPG_CLKON_CST; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + __IOM uint32_t CLK6_ON : 1; + __IOM uint32_t CLK7_ON : 1; + __IOM uint32_t CLK8_ON : 1; + __IOM uint32_t CLK9_ON : 1; + __IOM uint32_t CLK10_ON : 1; + __IOM uint32_t CLK11_ON : 1; + __IOM uint32_t CLK12_ON : 1; + __IOM uint32_t CLK13_ON : 1; + uint32_t : 2; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + __IOM uint32_t CLK6_ONWEN : 1; + __IOM uint32_t CLK7_ONWEN : 1; + __IOM uint32_t CLK8_ONWEN : 1; + __IOM uint32_t CLK9_ONWEN : 1; + __IOM uint32_t CLK10_ONWEN : 1; + __IOM uint32_t CLK11_ONWEN : 1; + __IOM uint32_t CLK12_ONWEN : 1; + __IOM uint32_t CLK13_ONWEN : 1; + uint32_t : 2; + } CPG_CLKON_CST_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SYC; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_SYC_b; + }; + union + { + __IOM uint32_t CPG_CLKON_DMAC_REG; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_DMAC_REG_b; + }; + __IM uint8_t RESERVED11[4]; + union + { + __IOM uint32_t CPG_CLKON_GTM; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + __IOM uint32_t CLK6_ON : 1; + __IOM uint32_t CLK7_ON : 1; + uint32_t : 8; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + __IOM uint32_t CLK6_ONWEN : 1; + __IOM uint32_t CLK7_ONWEN : 1; + uint32_t : 8; + } CPG_CLKON_GTM_b; + }; + union + { + __IOM uint32_t CPG_CLKON_MTU; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_MTU_b; + }; + union + { + __IOM uint32_t CPG_CLKON_POE3; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_POE3_b; + }; + union + { + __IOM uint32_t CPG_CLKON_GPT; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_GPT_b; + }; + union + { + __IOM uint32_t CPG_CLKON_POEG; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + uint32_t : 12; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + uint32_t : 12; + } CPG_CLKON_POEG_b; + }; + union + { + __IOM uint32_t CPG_CLKON_WDT; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + uint32_t : 10; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + uint32_t : 10; + } CPG_CLKON_WDT_b; + }; + union + { + __IOM uint32_t CPG_CLKON_DDR; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + uint32_t : 12; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + uint32_t : 12; + } CPG_CLKON_DDR_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SPI; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + uint32_t : 12; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + uint32_t : 12; + } CPG_CLKON_SPI_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SDHI; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + __IOM uint32_t CLK6_ON : 1; + __IOM uint32_t CLK7_ON : 1; + __IOM uint32_t CLK8_ON : 1; + __IOM uint32_t CLK9_ON : 1; + __IOM uint32_t CLK10_ON : 1; + __IOM uint32_t CLK11_ON : 1; + uint32_t : 4; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + __IOM uint32_t CLK6_ONWEN : 1; + __IOM uint32_t CLK7_ONWEN : 1; + __IOM uint32_t CLK8_ONWEN : 1; + __IOM uint32_t CLK9_ONWEN : 1; + __IOM uint32_t CLK10_ONWEN : 1; + __IOM uint32_t CLK11_ONWEN : 1; + uint32_t : 4; + } CPG_CLKON_SDHI_b; + }; + __IM uint8_t RESERVED12[24]; + union + { + __IOM uint32_t CPG_CLKON_SSI; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + __IOM uint32_t CLK6_ON : 1; + __IOM uint32_t CLK7_ON : 1; + uint32_t : 8; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + __IOM uint32_t CLK6_ONWEN : 1; + __IOM uint32_t CLK7_ONWEN : 1; + uint32_t : 8; + } CPG_CLKON_SSI_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SRC; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_SRC_b; + }; + union + { + __IOM uint32_t CPG_CLKON_USB; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + uint32_t : 12; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + uint32_t : 12; + } CPG_CLKON_USB_b; + }; + union + { + __IOM uint32_t CPG_CLKON_ETH; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ON : 1; + __IOM uint32_t CLK9_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ONWEN : 1; + __IOM uint32_t CLK9_ONWEN : 1; + uint32_t : 6; + } CPG_CLKON_ETH_b; + }; + union + { + __IOM uint32_t CPG_CLKON_I2C; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + uint32_t : 12; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + uint32_t : 12; + } CPG_CLKON_I2C_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SCIF; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IM uint32_t CLK5_ON : 1; + uint32_t : 10; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IM uint32_t CLK5_ONWEN : 1; + uint32_t : 10; + } CPG_CLKON_SCIF_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SCI; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_SCI_b; + }; + union + { + __IOM uint32_t CPG_CLKON_IRDA; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_IRDA_b; + }; + union + { + __IOM uint32_t CPG_CLKON_RSPI; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + uint32_t : 11; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + uint32_t : 11; + } CPG_CLKON_RSPI_b; + }; + union + { + __IOM uint32_t CPG_CLKON_CANFD; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_CANFD_b; + }; + union + { + __IOM uint32_t CPG_CLKON_GPIO; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_GPIO_b; + }; + __IM uint8_t RESERVED13[12]; + union + { + __IOM uint32_t CPG_CLKON_ADC; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_ADC_b; + }; + union + { + __IOM uint32_t CPG_CLKON_TSU; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_TSU_b; + }; + __IM uint8_t RESERVED14[4]; + union + { + __IOM uint32_t CPG_CLKON_AXI_ACPU_BUS; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + __IOM uint32_t CLK6_ON : 1; + uint32_t : 9; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + __IOM uint32_t CLK6_ONWEN : 1; + uint32_t : 9; + } CPG_CLKON_AXI_ACPU_BUS_b; + }; + union + { + __IOM uint32_t CPG_CLKON_AXI_MCPU_BUS; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + __IOM uint32_t CLK6_ON : 1; + __IOM uint32_t CLK7_ON : 1; + __IOM uint32_t CLK8_ON : 1; + uint32_t : 1; + __IOM uint32_t CLK10_ON : 1; + __IOM uint32_t CLK11_ON : 1; + __IOM uint32_t CLK12_ON : 1; + uint32_t : 1; + __IOM uint32_t CLK14_ON : 1; + __IOM uint32_t CLK15_ON : 1; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + __IOM uint32_t CLK6_ONWEN : 1; + __IOM uint32_t CLK7_ONWEN : 1; + __IOM uint32_t CLK8_ONWEN : 1; + uint32_t : 1; + __IOM uint32_t CLK10_ONWEN : 1; + __IOM uint32_t CLK11_ONWEN : 1; + __IOM uint32_t CLK12_ONWEN : 1; + uint32_t : 1; + __IOM uint32_t CLK14_ONWEN : 1; + __IOM uint32_t CLK15_ONWEN : 1; + } CPG_CLKON_AXI_MCPU_BUS_b; + }; + union + { + __IOM uint32_t CPG_CLKON_AXI_COM_BUS; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ON : 1; + __IOM uint32_t CLK9_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ONWEN : 1; + __IOM uint32_t CLK9_ONWEN : 1; + uint32_t : 6; + } CPG_CLKON_AXI_COM_BUS_b; + }; + __IM uint8_t RESERVED15[4]; + union + { + __IOM uint32_t CPG_CLKON_PERI_COM; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ON : 1; + __IOM uint32_t CLK9_ON : 1; + uint32_t : 6; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 6; + __IOM uint32_t CLK8_ONWEN : 1; + __IOM uint32_t CLK9_ONWEN : 1; + uint32_t : 6; + } CPG_CLKON_PERI_COM_b; + }; + union + { + __IOM uint32_t CPG_CLKON_REG1_BUS; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_REG1_BUS_b; + }; + union + { + __IOM uint32_t CPG_CLKON_REG0_BUS; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + uint32_t : 12; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + uint32_t : 12; + } CPG_CLKON_REG0_BUS_b; + }; + union + { + __IOM uint32_t CPG_CLKON_PERI_CPU; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + __IOM uint32_t CLK2_ON : 1; + __IOM uint32_t CLK3_ON : 1; + __IOM uint32_t CLK4_ON : 1; + __IOM uint32_t CLK5_ON : 1; + __IOM uint32_t CLK6_ON : 1; + __IOM uint32_t CLK7_ON : 1; + uint32_t : 8; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + __IOM uint32_t CLK2_ONWEN : 1; + __IOM uint32_t CLK3_ONWEN : 1; + __IOM uint32_t CLK4_ONWEN : 1; + __IOM uint32_t CLK5_ONWEN : 1; + __IOM uint32_t CLK6_ONWEN : 1; + __IOM uint32_t CLK7_ONWEN : 1; + uint32_t : 8; + } CPG_CLKON_PERI_CPU_b; + }; + __IM uint8_t RESERVED16[4]; + union + { + __IOM uint32_t CPG_CLKON_PERI_DDR; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_PERI_DDR_b; + }; + union + { + __IOM uint32_t CPG_CLKON_AXI_TZCDDR; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_AXI_TZCDDR_b; + }; + __IM uint8_t RESERVED17[20]; + union + { + __IOM uint32_t CPG_CLKON_OCTA; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_OCTA_b; + }; + union + { + __IOM uint32_t CPG_CLKON_OTFDE_DDR; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_OTFDE_DDR_b; + }; + __IM uint8_t RESERVED18[4]; + union + { + __IOM uint32_t CPG_CLKON_OTFDE_SPI; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_OTFDE_SPI_b; + }; + union + { + __IOM uint32_t CPG_CLKON_PDM; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_PDM_b; + }; + union + { + __IOM uint32_t CPG_CLKON_PCI; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_PCI_b; + }; + union + { + __IOM uint32_t CPG_CLKON_SPDIF; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_SPDIF_b; + }; + union + { + __IOM uint32_t CPG_CLKON_I3C; + struct + { + __IOM uint32_t CLK0_ON : 1; + __IOM uint32_t CLK1_ON : 1; + uint32_t : 14; + __IOM uint32_t CLK0_ONWEN : 1; + __IOM uint32_t CLK1_ONWEN : 1; + uint32_t : 14; + } CPG_CLKON_I3C_b; + }; + union + { + __IOM uint32_t CPG_CLKON_VBAT; + struct + { + __IOM uint32_t CLK0_ON : 1; + uint32_t : 15; + __IOM uint32_t CLK0_ONWEN : 1; + uint32_t : 15; + } CPG_CLKON_VBAT_b; + }; + __IM uint8_t RESERVED19[104]; + union + { + __IM uint32_t CPG_CLKMON_CA55; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + uint32_t : 26; + } CPG_CLKMON_CA55_b; + }; + union + { + __IM uint32_t CPG_CLKMON_CM33; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 6; + __IM uint32_t CLK8_MON : 1; + __IM uint32_t CLK9_MON : 1; + uint32_t : 22; + } CPG_CLKMON_CM33_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SRAM_ACPU; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + uint32_t : 29; + } CPG_CLKMON_SRAM_ACPU_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SRAM_MCPU; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_SRAM_MCPU_b; + }; + __IM uint8_t RESERVED20[4]; + union + { + __IM uint32_t CPG_CLKMON_GIC600; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_GIC600_b; + }; + union + { + __IM uint32_t CPG_CLKMON_IA55; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_IA55_b; + }; + union + { + __IM uint32_t CPG_CLKMON_IM33; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 6; + __IM uint32_t CLK8_MON : 1; + __IM uint32_t CLK9_MON : 1; + uint32_t : 22; + } CPG_CLKMON_IM33_b; + }; + union + { + __IM uint32_t CPG_CLKMON_MHU; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_MHU_b; + }; + union + { + __IM uint32_t CPG_CLKMON_CST; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + __IM uint32_t CLK6_MON : 1; + __IM uint32_t CLK7_MON : 1; + __IM uint32_t CLK8_MON : 1; + __IM uint32_t CLK9_MON : 1; + __IM uint32_t CLK10_MON : 1; + __IM uint32_t CLK11_MON : 1; + __IM uint32_t CLK12_MON : 1; + __IM uint32_t CLK13_MON : 1; + uint32_t : 18; + } CPG_CLKMON_CST_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SYC; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_SYC_b; + }; + union + { + __IM uint32_t CPG_CLKMON_DMAC_REG; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_DMAC_REG_b; + }; + __IM uint8_t RESERVED21[4]; + union + { + __IM uint32_t CPG_CLKMON_GTM; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + __IM uint32_t CLK6_MON : 1; + __IM uint32_t CLK7_MON : 1; + uint32_t : 24; + } CPG_CLKMON_GTM_b; + }; + union + { + __IM uint32_t CPG_CLKMON_MTU; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_MTU_b; + }; + union + { + __IM uint32_t CPG_CLKMON_POE3; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_POE3_b; + }; + union + { + __IM uint32_t CPG_CLKMON_GPT; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_GPT_b; + }; + union + { + __IM uint32_t CPG_CLKMON_POEG; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + uint32_t : 28; + } CPG_CLKMON_POEG_b; + }; + union + { + __IM uint32_t CPG_CLKMON_WDT; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + uint32_t : 26; + } CPG_CLKMON_WDT_b; + }; + union + { + __IM uint32_t CPG_CLKMON_DDR; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + uint32_t : 28; + } CPG_CLKMON_DDR_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SPI; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + uint32_t : 28; + } CPG_CLKMON_SPI_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SDHI; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + __IM uint32_t CLK6_MON : 1; + __IM uint32_t CLK7_MON : 1; + __IM uint32_t CLK8_MON : 1; + __IM uint32_t CLK9_MON : 1; + __IM uint32_t CLK10_MON : 1; + __IM uint32_t CLK11_MON : 1; + uint32_t : 20; + } CPG_CLKMON_SDHI_b; + }; + __IM uint8_t RESERVED22[24]; + union + { + __IM uint32_t CPG_CLKMON_SSI; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + __IM uint32_t CLK6_MON : 1; + __IM uint32_t CLK7_MON : 1; + uint32_t : 24; + } CPG_CLKMON_SSI_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SRC; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_SRC_b; + }; + union + { + __IM uint32_t CPG_CLKMON_USB; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + uint32_t : 28; + } CPG_CLKMON_USB_b; + }; + union + { + __IM uint32_t CPG_CLKMON_ETH; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 6; + __IM uint32_t CLK8_MON : 1; + __IM uint32_t CLK9_MON : 1; + uint32_t : 22; + } CPG_CLKMON_ETH_b; + }; + union + { + __IM uint32_t CPG_CLKMON_I2C; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + uint32_t : 28; + } CPG_CLKMON_I2C_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SCIF; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + uint32_t : 26; + } CPG_CLKMON_SCIF_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SCI; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_SCI_b; + }; + union + { + __IM uint32_t CPG_CLKMON_IRDA; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_IRDA_b; + }; + union + { + __IM uint32_t CPG_CLKMON_RSPI; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + uint32_t : 27; + } CPG_CLKMON_RSPI_b; + }; + union + { + __IM uint32_t CPG_CLKMON_CANFD; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_CANFD_b; + }; + union + { + __IM uint32_t CPG_CLKMON_GPIO; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_GPIO_b; + }; + __IM uint8_t RESERVED23[12]; + union + { + __IM uint32_t CPG_CLKMON_ADC; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_ADC_b; + }; + union + { + __IM uint32_t CPG_CLKMON_TSU; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_TSU_b; + }; + __IM uint8_t RESERVED24[4]; + union + { + __IM uint32_t CPG_CLKMON_AXI_ACPU_BUS; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + __IM uint32_t CLK6_MON : 1; + uint32_t : 25; + } CPG_CLKMON_AXI_ACPU_BUS_b; + }; + union + { + __IM uint32_t CPG_CLKMON_AXI_MCPU_BUS; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + __IM uint32_t CLK6_MON : 1; + __IM uint32_t CLK7_MON : 1; + __IM uint32_t CLK8_MON : 1; + uint32_t : 1; + __IM uint32_t CLK10_MON : 1; + __IM uint32_t CLK11_MON : 1; + __IM uint32_t CLK12_MON : 1; + uint32_t : 1; + __IM uint32_t CLK14_MON : 1; + __IM uint32_t CLK15_MON : 1; + uint32_t : 16; + } CPG_CLKMON_AXI_MCPU_BUS_b; + }; + union + { + __IM uint32_t CPG_CLKMON_AXI_COM_BUS; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 6; + __IM uint32_t CLK8_MON : 1; + __IM uint32_t CLK9_MON : 1; + uint32_t : 22; + } CPG_CLKMON_AXI_COM_BUS_b; + }; + __IM uint8_t RESERVED25[4]; + union + { + __IM uint32_t CPG_CLKMON_PERI_COM; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 6; + __IM uint32_t CLK8_MON : 1; + __IM uint32_t CLK9_MON : 1; + uint32_t : 22; + } CPG_CLKMON_PERI_COM_b; + }; + union + { + __IM uint32_t CPG_CLKMON_REG1_BUS; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_REG1_BUS_b; + }; + union + { + __IM uint32_t CPG_CLKMON_REG0_BUS; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + uint32_t : 28; + } CPG_CLKMON_REG0_BUS_b; + }; + union + { + __IM uint32_t CPG_CLKMON_PERI_CPU; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + __IM uint32_t CLK2_MON : 1; + __IM uint32_t CLK3_MON : 1; + __IM uint32_t CLK4_MON : 1; + __IM uint32_t CLK5_MON : 1; + __IM uint32_t CLK6_MON : 1; + __IM uint32_t CLK7_MON : 1; + uint32_t : 24; + } CPG_CLKMON_PERI_CPU_b; + }; + __IM uint8_t RESERVED26[4]; + union + { + __IM uint32_t CPG_CLKMON_PERI_DDR; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_PERI_DDR_b; + }; + union + { + __IM uint32_t CPG_CLKMON_AXI_TZCDDR; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_AXI_TZCDDR_b; + }; + __IM uint8_t RESERVED27[20]; + union + { + __IM uint32_t CPG_CLKMON_OCTA; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_OCTA_b; + }; + union + { + __IM uint32_t CPG_CLKMON_OTFDE_DDR; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_OTFDE_DDR_b; + }; + __IM uint8_t RESERVED28[4]; + union + { + __IM uint32_t CPG_CLKMON_OTFDE_SPI; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_OTFDE_SPI_b; + }; + union + { + __IM uint32_t CPG_CLKMON_PDM; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_PDM_b; + }; + union + { + __IM uint32_t CPG_CLKMON_PCI; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_PCI_b; + }; + union + { + __IM uint32_t CPG_CLKMON_SPDIF; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_SPDIF_b; + }; + union + { + __IM uint32_t CPG_CLKMON_I3C; + struct + { + __IM uint32_t CLK0_MON : 1; + __IM uint32_t CLK1_MON : 1; + uint32_t : 30; + } CPG_CLKMON_I3C_b; + }; + union + { + __IM uint32_t CPG_CLKMON_VBAT; + struct + { + __IM uint32_t CLK0_MON : 1; + uint32_t : 31; + } CPG_CLKMON_VBAT_b; + }; + __IM uint8_t RESERVED29[104]; + union + { + __IOM uint32_t CPG_RST_CA55; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 1; + __IOM uint32_t UNIT2_RSTB : 1; + uint32_t : 1; + __IOM uint32_t UNIT4_RSTB : 1; + __IOM uint32_t UNIT5_RSTB : 1; + __IOM uint32_t UNIT6_RSTB : 1; + __IOM uint32_t UNIT7_RSTB : 1; + __IOM uint32_t UNIT8_RSTB : 1; + __IOM uint32_t UNIT9_RSTB : 1; + __IOM uint32_t UNIT10_RSTB : 1; + __IOM uint32_t UNIT11_RSTB : 1; + __IOM uint32_t UNIT12_RSTB : 1; + uint32_t : 3; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + uint32_t : 1; + __IOM uint32_t UNIT4_RSTWEN : 1; + __IOM uint32_t UNIT5_RSTWEN : 1; + __IOM uint32_t UNIT6_RSTWEN : 1; + __IOM uint32_t UNIT7_RSTWEN : 1; + __IOM uint32_t UNIT8_RSTWEN : 1; + __IOM uint32_t UNIT9_RSTWEN : 1; + __IOM uint32_t UNIT10_RSTWEN : 1; + __IOM uint32_t UNIT11_RSTWEN : 1; + __IOM uint32_t UNIT12_RSTWEN : 1; + uint32_t : 3; + } CPG_RST_CA55_b; + }; + union + { + __IOM uint32_t CPG_RST_CM33; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + uint32_t : 5; + __IOM uint32_t UNIT8_RSTB : 1; + __IOM uint32_t UNIT9_RSTB : 1; + __IOM uint32_t UNIT10_RSTB : 1; + uint32_t : 5; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + uint32_t : 5; + __IOM uint32_t UNIT8_RSTWEN : 1; + __IOM uint32_t UNIT9_RSTWEN : 1; + __IOM uint32_t UNIT10_RSTWEN : 1; + uint32_t : 5; + } CPG_RST_CM33_b; + }; + union + { + __IOM uint32_t CPG_RST_SRAM_ACPU; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + uint32_t : 13; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + uint32_t : 13; + } CPG_RST_SRAM_ACPU_b; + }; + union + { + __IOM uint32_t CPG_RST_SRAM_MCPU; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_SRAM_MCPU_b; + }; + __IM uint8_t RESERVED30[4]; + union + { + __IOM uint32_t CPG_RST_GIC600; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_GIC600_b; + }; + union + { + __IOM uint32_t CPG_RST_IA55; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_IA55_b; + }; + union + { + __IOM uint32_t CPG_RST_IM33; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 7; + __IOM uint32_t UNIT8_RSTB : 1; + uint32_t : 7; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 7; + __IOM uint32_t UNIT8_RSTWEN : 1; + uint32_t : 7; + } CPG_RST_IM33_b; + }; + union + { + __IOM uint32_t CPG_RST_MHU; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_MHU_b; + }; + __IM uint8_t RESERVED31[4]; + union + { + __IOM uint32_t CPG_RST_SYC; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_SYC_b; + }; + union + { + __IOM uint32_t CPG_RST_DMAC; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_DMAC_b; + }; + __IM uint8_t RESERVED32[4]; + union + { + __IOM uint32_t CPG_RST_GTM; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + __IOM uint32_t UNIT4_RSTB : 1; + __IOM uint32_t UNIT5_RSTB : 1; + __IOM uint32_t UNIT6_RSTB : 1; + __IOM uint32_t UNIT7_RSTB : 1; + uint32_t : 8; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + __IOM uint32_t UNIT4_RSTWEN : 1; + __IOM uint32_t UNIT5_RSTWEN : 1; + __IOM uint32_t UNIT6_RSTWEN : 1; + __IOM uint32_t UNIT7_RSTWEN : 1; + uint32_t : 8; + } CPG_RST_GTM_b; + }; + union + { + __IOM uint32_t CPG_RST_MTU; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_MTU_b; + }; + union + { + __IOM uint32_t CPG_RST_POE3; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_POE3_b; + }; + union + { + __IOM uint32_t CPG_RST_GPT; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_GPT_b; + }; + union + { + __IOM uint32_t CPG_RST_POEG; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + uint32_t : 12; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + uint32_t : 12; + } CPG_RST_POEG_b; + }; + union + { + __IOM uint32_t CPG_RST_WDT; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + uint32_t : 13; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + uint32_t : 13; + } CPG_RST_WDT_b; + }; + union + { + __IOM uint32_t CPG_RST_DDR; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + uint32_t : 2; + __IOM uint32_t UNIT6_RSTB : 1; + __IOM uint32_t UNIT7_RSTB : 1; + __IOM uint32_t UNIT8_RSTB : 1; + uint32_t : 7; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + uint32_t : 2; + __IOM uint32_t UNIT6_RSTWEN : 1; + __IOM uint32_t UNIT7_RSTWEN : 1; + __IOM uint32_t UNIT8_RSTWEN : 1; + uint32_t : 7; + } CPG_RST_DDR_b; + }; + union + { + __IOM uint32_t CPG_RST_SPI; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_SPI_b; + }; + union + { + __IOM uint32_t CPG_RST_SDHI; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + uint32_t : 13; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + uint32_t : 13; + } CPG_RST_SDHI_b; + }; + __IM uint8_t RESERVED33[24]; + union + { + __IOM uint32_t CPG_RST_SSIF; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + uint32_t : 12; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + uint32_t : 12; + } CPG_RST_SSIF_b; + }; + union + { + __IOM uint32_t CPG_RST_SRC; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_SRC_b; + }; + union + { + __IOM uint32_t CPG_RST_USB; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + uint32_t : 12; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + uint32_t : 12; + } CPG_RST_USB_b; + }; + union + { + __IOM uint32_t CPG_RST_ETH; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_ETH_b; + }; + union + { + __IOM uint32_t CPG_RST_I2C; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + uint32_t : 12; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + uint32_t : 12; + } CPG_RST_I2C_b; + }; + union + { + __IOM uint32_t CPG_RST_SCIF; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + __IOM uint32_t UNIT4_RSTB : 1; + __IOM uint32_t UNIT5_RSTB : 1; + uint32_t : 10; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + __IOM uint32_t UNIT4_RSTWEN : 1; + __IOM uint32_t UNIT5_RSTWEN : 1; + uint32_t : 10; + } CPG_RST_SCIF_b; + }; + union + { + __IOM uint32_t CPG_RST_SCI; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_SCI_b; + }; + union + { + __IOM uint32_t CPG_RST_IRDA; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_IRDA_b; + }; + union + { + __IOM uint32_t CPG_RST_RSPI; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + __IOM uint32_t UNIT4_RSTB : 1; + uint32_t : 11; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + __IOM uint32_t UNIT4_RSTWEN : 1; + uint32_t : 11; + } CPG_RST_RSPI_b; + }; + union + { + __IOM uint32_t CPG_RST_CANFD; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_CANFD_b; + }; + union + { + __IOM uint32_t CPG_RST_GPIO; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + uint32_t : 13; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + uint32_t : 13; + } CPG_RST_GPIO_b; + }; + __IM uint8_t RESERVED34[12]; + union + { + __IOM uint32_t CPG_RST_ADC; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_ADC_b; + }; + union + { + __IOM uint32_t CPG_RST_TSU; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_TSU_b; + }; + __IM uint8_t RESERVED35[4]; + union + { + __IOM uint32_t CPG_RST_AXI_ACPU_BUS; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_AXI_ACPU_BUS_b; + }; + union + { + __IOM uint32_t CPG_RST_AXI_MCPU_BUS; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_AXI_MCPU_BUS_b; + }; + union + { + __IOM uint32_t CPG_RST_AXI_COM_BUS; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_AXI_COM_BUS_b; + }; + __IM uint8_t RESERVED36[4]; + union + { + __IOM uint32_t CPG_RST_PERI_COM; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_PERI_COM_b; + }; + union + { + __IOM uint32_t CPG_RST_REG1_BUS; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_REG1_BUS_b; + }; + union + { + __IOM uint32_t CPG_RST_REG0_BUS; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_REG0_BUS_b; + }; + union + { + __IOM uint32_t CPG_RST_PERI_CPU; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_PERI_CPU_b; + }; + __IM uint8_t RESERVED37[4]; + union + { + __IOM uint32_t CPG_RST_PERI_DDR; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_PERI_DDR_b; + }; + union + { + __IOM uint32_t CPG_RST_AXI_TZCDDR; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + uint32_t : 12; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + uint32_t : 12; + } CPG_RST_AXI_TZCDDR_b; + }; + __IM uint8_t RESERVED38[20]; + union + { + __IOM uint32_t CPG_RST_OCTA; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_OCTA_b; + }; + union + { + __IOM uint32_t CPG_RST_OTFDE_DDR; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_OTFDE_DDR_b; + }; + __IM uint8_t RESERVED39[4]; + union + { + __IOM uint32_t CPG_RST_OTFDE_SPI; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_OTFDE_SPI_b; + }; + union + { + __IOM uint32_t CPG_RST_PDM; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_PDM_b; + }; + union + { + __IOM uint32_t CPG_RST_PCI; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + __IOM uint32_t UNIT2_RSTB : 1; + __IOM uint32_t UNIT3_RSTB : 1; + __IOM uint32_t UNIT4_RSTB : 1; + __IOM uint32_t UNIT5_RSTB : 1; + __IOM uint32_t UNIT6_RSTB : 1; + uint32_t : 9; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + __IOM uint32_t UNIT2_RSTWEN : 1; + __IOM uint32_t UNIT3_RSTWEN : 1; + __IOM uint32_t UNIT4_RSTWEN : 1; + __IOM uint32_t UNIT5_RSTWEN : 1; + __IOM uint32_t UNIT6_RSTWEN : 1; + uint32_t : 9; + } CPG_RST_PCI_b; + }; + union + { + __IOM uint32_t CPG_RST_SPDIF; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_SPDIF_b; + }; + union + { + __IOM uint32_t CPG_RST_I3C; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + __IOM uint32_t UNIT1_RSTB : 1; + uint32_t : 14; + __IOM uint32_t UNIT0_RSTWEN : 1; + __IOM uint32_t UNIT1_RSTWEN : 1; + uint32_t : 14; + } CPG_RST_I3C_b; + }; + union + { + __IOM uint32_t CPG_RST_VBAT; + struct + { + __IOM uint32_t UNIT0_RSTB : 1; + uint32_t : 15; + __IOM uint32_t UNIT0_RSTWEN : 1; + uint32_t : 15; + } CPG_RST_VBAT_b; + }; + __IM uint8_t RESERVED40[104]; + union + { + __IM uint32_t CPG_RSTMON_CA55; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 1; + __IM uint32_t RST2_MON : 1; + uint32_t : 1; + __IM uint32_t RST4_MON : 1; + __IM uint32_t RST5_MON : 1; + __IM uint32_t RST6_MON : 1; + __IM uint32_t RST7_MON : 1; + __IM uint32_t RST8_MON : 1; + __IM uint32_t RST9_MON : 1; + __IM uint32_t RST10_MON : 1; + __IM uint32_t RST11_MON : 1; + __IM uint32_t RST12_MON : 1; + uint32_t : 19; + } CPG_RSTMON_CA55_b; + }; + union + { + __IM uint32_t CPG_RSTMON_CM33; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + uint32_t : 5; + __IM uint32_t RST8_MON : 1; + __IM uint32_t RST9_MON : 1; + __IM uint32_t RST10_MON : 1; + uint32_t : 21; + } CPG_RSTMON_CM33_b; + }; + union + { + __IM uint32_t CPG_RSTMON_SRAM_ACPU; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_SRAM_ACPU_b; + }; + union + { + __IM uint32_t CPG_RSTMON_SRAM_MCPU; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_SRAM_MCPU_b; + }; + __IM uint8_t RESERVED41[4]; + union + { + __IM uint32_t CPG_RSTMON_GIC600; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_GIC600_b; + }; + union + { + __IM uint32_t CPG_RSTMON_IA55; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_IA55_b; + }; + union + { + __IM uint32_t CPG_RSTMON_IM33; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_IM33_b; + }; + union + { + __IM uint32_t CPG_RSTMON_MHU; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_MHU_b; + }; + __IM uint8_t RESERVED42[4]; + union + { + __IM uint32_t CPG_RSTMON_SYC; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_SYC_b; + }; + union + { + __IM uint32_t CPG_RSTMON_DMAC; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_DMAC_b; + }; + __IM uint8_t RESERVED43[4]; + union + { + __IM uint32_t CPG_RSTMON_GTM; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + __IM uint32_t RST4_MON : 1; + __IM uint32_t RST5_MON : 1; + __IM uint32_t RST6_MON : 1; + __IM uint32_t RST7_MON : 1; + uint32_t : 24; + } CPG_RSTMON_GTM_b; + }; + union + { + __IM uint32_t CPG_RSTMON_MTU; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_MTU_b; + }; + union + { + __IM uint32_t CPG_RSTMON_POE3; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_POE3_b; + }; + union + { + __IM uint32_t CPG_RSTMON_GPT; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_GPT_b; + }; + union + { + __IM uint32_t CPG_RSTMON_POEG; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + uint32_t : 28; + } CPG_RSTMON_POEG_b; + }; + union + { + __IM uint32_t CPG_RSTMON_WDT; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + uint32_t : 29; + } CPG_RSTMON_WDT_b; + }; + union + { + __IM uint32_t CPG_RSTMON_DDR; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + uint32_t : 2; + __IM uint32_t RST6_MON : 1; + __IM uint32_t RST7_MON : 1; + __IM uint32_t RST8_MON : 1; + uint32_t : 23; + } CPG_RSTMON_DDR_b; + }; + union + { + __IM uint32_t CPG_RSTMON_SPI; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_SPI_b; + }; + union + { + __IM uint32_t CPG_RSTMON_SDHI; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + uint32_t : 29; + } CPG_RSTMON_SDHI_b; + }; + __IM uint8_t RESERVED44[24]; + union + { + __IM uint32_t CPG_RSTMON_SSIF; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + uint32_t : 28; + } CPG_RSTMON_SSIF_b; + }; + union + { + __IM uint32_t CPG_RSTMON_SRC; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_SRC_b; + }; + union + { + __IM uint32_t CPG_RSTMON_USB; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + uint32_t : 28; + } CPG_RSTMON_USB_b; + }; + union + { + __IM uint32_t CPG_RSTMON_ETH; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_ETH_b; + }; + union + { + __IM uint32_t CPG_RSTMON_I2C; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + uint32_t : 28; + } CPG_RSTMON_I2C_b; + }; + union + { + __IM uint32_t CPG_RSTMON_SCIF; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + __IM uint32_t RST4_MON : 1; + __IM uint32_t RST5_MON : 1; + uint32_t : 26; + } CPG_RSTMON_SCIF_b; + }; + union + { + __IM uint32_t CPG_RSTMON_SCI; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_SCI_b; + }; + union + { + __IM uint32_t CPG_RSTMON_IRDA; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_IRDA_b; + }; + union + { + __IM uint32_t CPG_RSTMON_RSPI; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + __IM uint32_t RST4_MON : 1; + uint32_t : 27; + } CPG_RSTMON_RSPI_b; + }; + union + { + __IM uint32_t CPG_RSTMON_CANFD; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_CANFD_b; + }; + union + { + __IM uint32_t CPG_RSTMON_GPIO; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + uint32_t : 29; + } CPG_RSTMON_GPIO_b; + }; + __IM uint8_t RESERVED45[12]; + union + { + __IM uint32_t CPG_RSTMON_ADC; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_ADC_b; + }; + union + { + __IM uint32_t CPG_RSTMON_TSU; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_TSU_b; + }; + __IM uint8_t RESERVED46[4]; + union + { + __IM uint32_t CPG_RSTMON_AXI_ACPU_BUS; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_AXI_ACPU_BUS_b; + }; + union + { + __IM uint32_t CPG_RSTMON_AXI_MCPU_BUS; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_AXI_MCPU_BUS_b; + }; + union + { + __IM uint32_t CPG_RSTMON_AXI_COM_BUS; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_AXI_COM_BUS_b; + }; + __IM uint8_t RESERVED47[4]; + union + { + __IM uint32_t CPG_RSTMON_PERI_COM; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_PERI_COM_b; + }; + union + { + __IM uint32_t CPG_RSTMON_REG1_BUS; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_REG1_BUS_b; + }; + union + { + __IM uint32_t CPG_RSTMON_REG0_BUS; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_REG0_BUS_b; + }; + union + { + __IM uint32_t CPG_RSTMON_PERI_CPU; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_PERI_CPU_b; + }; + __IM uint8_t RESERVED48[4]; + union + { + __IM uint32_t CPG_RSTMON_PERI_DDR; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_PERI_DDR_b; + }; + union + { + __IM uint32_t CPG_RSTMON_AXI_TZCDDR; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + uint32_t : 28; + } CPG_RSTMON_AXI_TZCDDR_b; + }; + __IM uint8_t RESERVED49[20]; + union + { + __IM uint32_t CPG_RSTMON_OCTA; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_OCTA_b; + }; + union + { + __IM uint32_t CPG_RSTMON_OTFDE_DDR; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_OTFDE_DDR_b; + }; + __IM uint8_t RESERVED50[4]; + union + { + __IM uint32_t CPG_RSTMON_OTFDE_SPI; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_OTFDE_SPI_b; + }; + union + { + __IM uint32_t CPG_RSTMON_PDM; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_PDM_b; + }; + union + { + __IM uint32_t CPG_RSTMON_PCI; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + __IM uint32_t RST2_MON : 1; + __IM uint32_t RST3_MON : 1; + __IM uint32_t RST4_MON : 1; + __IM uint32_t RST5_MON : 1; + __IM uint32_t RST6_MON : 1; + uint32_t : 25; + } CPG_RSTMON_PCI_b; + }; + union + { + __IM uint32_t CPG_RSTMON_SPDIF; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_SPDIF_b; + }; + union + { + __IM uint32_t CPG_RSTMON_I3C; + struct + { + __IM uint32_t RST0_MON : 1; + __IM uint32_t RST1_MON : 1; + uint32_t : 30; + } CPG_RSTMON_I3C_b; + }; + union + { + __IM uint32_t CPG_RSTMON_VBAT; + struct + { + __IM uint32_t RST0_MON : 1; + uint32_t : 31; + } CPG_RSTMON_VBAT_b; + }; + __IM uint8_t RESERVED51[120]; + union + { + __IOM uint32_t CPG_WDTOVF_RST; + struct + { + __IOM uint32_t WDTOVF0 : 1; + __IOM uint32_t WDTOVF1 : 1; + __IOM uint32_t WDTOVF2 : 1; + uint32_t : 13; + __IOM uint32_t WDTOVF0_WEN : 1; + __IOM uint32_t WDTOVF1_WEN : 1; + __IOM uint32_t WDTOVF2_WEN : 1; + uint32_t : 13; + } CPG_WDTOVF_RST_b; + }; + union + { + __IOM uint32_t CPG_WDTRST_SEL; + struct + { + __IOM uint32_t WDTRSTSEL0 : 1; + __IOM uint32_t WDTRSTSEL1 : 1; + __IOM uint32_t WDTRSTSEL2 : 1; + uint32_t : 1; + __IOM uint32_t WDTRSTSEL4 : 1; + __IOM uint32_t WDTRSTSEL5 : 1; + __IOM uint32_t WDTRSTSEL6 : 1; + uint32_t : 1; + __IOM uint32_t WDTRSTSEL8 : 1; + __IOM uint32_t WDTRSTSEL9 : 1; + __IOM uint32_t WDTRSTSEL10 : 1; + uint32_t : 5; + __IOM uint32_t WDTRSTSEL0_WEN : 1; + __IOM uint32_t WDTRSTSEL1_WEN : 1; + __IOM uint32_t WDTRSTSEL2_WEN : 1; + uint32_t : 1; + __IOM uint32_t WDTRSTSEL4_WEN : 1; + __IOM uint32_t WDTRSTSEL5_WEN : 1; + __IOM uint32_t WDTRSTSEL6_WEN : 1; + uint32_t : 1; + __IOM uint32_t WDTRSTSEL8_WEN : 1; + __IOM uint32_t WDTRSTSEL9_WEN : 1; + __IOM uint32_t WDTRSTSEL10_WEN : 1; + uint32_t : 5; + } CPG_WDTRST_SEL_b; + }; + __IM uint8_t RESERVED52[24]; + union + { + __IM uint32_t CPG_CLUSTER_PCHMON; + struct + { + __IM uint32_t PACCEPT_MON : 1; + __IM uint32_t PDENY_MON : 1; + uint32_t : 30; + } CPG_CLUSTER_PCHMON_b; + }; + union + { + __IOM uint32_t CPG_CLUSTER_PCHCTL; + struct + { + __IOM uint32_t PREQ_SET : 1; + uint32_t : 15; + __IOM uint32_t PSTATE0_SET : 7; + uint32_t : 9; + } CPG_CLUSTER_PCHCTL_b; + }; + union + { + __IM uint32_t CPG_CORE0_PCHMON; + struct + { + __IM uint32_t PACCEPT0_MON : 1; + __IM uint32_t PDENY0_MON : 1; + uint32_t : 30; + } CPG_CORE0_PCHMON_b; + }; + union + { + __IOM uint32_t CPG_CORE0_PCHCTL; + struct + { + __IOM uint32_t PREQ0_SET : 1; + uint32_t : 15; + __IOM uint32_t PSTATE0_SET : 6; + uint32_t : 10; + } CPG_CORE0_PCHCTL_b; + }; + __IM uint8_t RESERVED53[32]; + union + { + __IOM uint32_t CPG_BUS_ACPU_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + uint32_t : 15; + __IOM uint32_t MSTOP0_ON_WEN : 1; + uint32_t : 15; + } CPG_BUS_ACPU_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_BUS_MCPU1_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + __IOM uint32_t MSTOP3_ON : 1; + __IOM uint32_t MSTOP4_ON : 1; + __IOM uint32_t MSTOP5_ON : 1; + __IOM uint32_t MSTOP6_ON : 1; + __IOM uint32_t MSTOP7_ON : 1; + __IOM uint32_t MSTOP8_ON : 1; + __IOM uint32_t MSTOP9_ON : 1; + __IOM uint32_t MSTOP10_ON : 1; + __IOM uint32_t MSTOP11_ON : 1; + __IOM uint32_t MSTOP12_ON : 1; + __IOM uint32_t MSTOP13_ON : 1; + __IOM uint32_t MSTOP14_ON : 1; + __IOM uint32_t MSTOP15_ON : 1; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + __IOM uint32_t MSTOP3_ON_WEN : 1; + __IOM uint32_t MSTOP4_ON_WEN : 1; + __IOM uint32_t MSTOP5_ON_WEN : 1; + __IOM uint32_t MSTOP6_ON_WEN : 1; + __IOM uint32_t MSTOP7_ON_WEN : 1; + __IOM uint32_t MSTOP8_ON_WEN : 1; + __IOM uint32_t MSTOP9_ON_WEN : 1; + __IOM uint32_t MSTOP10_ON_WEN : 1; + __IOM uint32_t MSTOP11_ON_WEN : 1; + __IOM uint32_t MSTOP12_ON_WEN : 1; + __IOM uint32_t MSTOP13_ON_WEN : 1; + __IOM uint32_t MSTOP14_ON_WEN : 1; + __IOM uint32_t MSTOP15_ON_WEN : 1; + } CPG_BUS_MCPU1_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_BUS_MCPU2_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + __IOM uint32_t MSTOP3_ON : 1; + __IOM uint32_t MSTOP4_ON : 1; + __IOM uint32_t MSTOP5_ON : 1; + __IOM uint32_t MSTOP6_ON : 1; + __IOM uint32_t MSTOP7_ON : 1; + __IOM uint32_t MSTOP8_ON : 1; + __IOM uint32_t MSTOP9_ON : 1; + __IOM uint32_t MSTOP10_ON : 1; + __IOM uint32_t MSTOP11_ON : 1; + __IOM uint32_t MSTOP12_ON : 1; + __IOM uint32_t MSTOP13_ON : 1; + __IOM uint32_t MSTOP14_ON : 1; + __IOM uint32_t MSTOP15_ON : 1; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + __IOM uint32_t MSTOP3_ON_WEN : 1; + __IOM uint32_t MSTOP4_ON_WEN : 1; + __IOM uint32_t MSTOP5_ON_WEN : 1; + __IOM uint32_t MSTOP6_ON_WEN : 1; + __IOM uint32_t MSTOP7_ON_WEN : 1; + __IOM uint32_t MSTOP8_ON_WEN : 1; + __IOM uint32_t MSTOP9_ON_WEN : 1; + __IOM uint32_t MSTOP10_ON_WEN : 1; + __IOM uint32_t MSTOP11_ON_WEN : 1; + __IOM uint32_t MSTOP12_ON_WEN : 1; + __IOM uint32_t MSTOP13_ON_WEN : 1; + __IOM uint32_t MSTOP14_ON_WEN : 1; + __IOM uint32_t MSTOP15_ON_WEN : 1; + } CPG_BUS_MCPU2_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_BUS_PERI_COM_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + __IOM uint32_t MSTOP3_ON : 1; + __IOM uint32_t MSTOP4_ON : 1; + __IOM uint32_t MSTOP5_ON : 1; + __IOM uint32_t MSTOP6_ON : 1; + __IOM uint32_t MSTOP7_ON : 1; + __IOM uint32_t MSTOP8_ON : 1; + __IOM uint32_t MSTOP9_ON : 1; + __IOM uint32_t MSTOP10_ON : 1; + __IOM uint32_t MSTOP11_ON : 1; + uint32_t : 4; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + __IOM uint32_t MSTOP3_ON_WEN : 1; + __IOM uint32_t MSTOP4_ON_WEN : 1; + __IOM uint32_t MSTOP5_ON_WEN : 1; + __IOM uint32_t MSTOP6_ON_WEN : 1; + __IOM uint32_t MSTOP7_ON_WEN : 1; + __IOM uint32_t MSTOP8_ON_WEN : 1; + __IOM uint32_t MSTOP9_ON_WEN : 1; + __IOM uint32_t MSTOP10_ON_WEN : 1; + __IOM uint32_t MSTOP11_ON_WEN : 1; + uint32_t : 4; + } CPG_BUS_PERI_COM_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_BUS_PERI_CPU_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + __IOM uint32_t MSTOP3_ON : 1; + __IOM uint32_t MSTOP4_ON : 1; + uint32_t : 1; + __IOM uint32_t MSTOP6_ON : 1; + __IOM uint32_t MSTOP7_ON : 1; + __IOM uint32_t MSTOP8_ON : 1; + __IOM uint32_t MSTOP9_ON : 1; + __IOM uint32_t MSTOP10_ON : 1; + __IOM uint32_t MSTOP11_ON : 1; + __IOM uint32_t MSTOP12_ON : 1; + __IOM uint32_t MSTOP13_ON : 1; + __IOM uint32_t MSTOP14_ON : 1; + __IOM uint32_t MSTOP15_ON : 1; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + __IOM uint32_t MSTOP3_ON_WEN : 1; + __IOM uint32_t MSTOP4_ON_WEN : 1; + uint32_t : 1; + __IOM uint32_t MSTOP6_ON_WEN : 1; + __IOM uint32_t MSTOP7_ON_WEN : 1; + __IOM uint32_t MSTOP8_ON_WEN : 1; + __IOM uint32_t MSTOP9_ON_WEN : 1; + __IOM uint32_t MSTOP10_ON_WEN : 1; + __IOM uint32_t MSTOP11_ON_WEN : 1; + __IOM uint32_t MSTOP12_ON_WEN : 1; + __IOM uint32_t MSTOP13_ON_WEN : 1; + __IOM uint32_t MSTOP14_ON_WEN : 1; + __IOM uint32_t MSTOP15_ON_WEN : 1; + } CPG_BUS_PERI_CPU_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_BUS_PERI_DDR_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + uint32_t : 14; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + uint32_t : 14; + } CPG_BUS_PERI_DDR_MSTOP_b; + }; + __IM uint8_t RESERVED54[4]; + union + { + __IOM uint32_t CPG_BUS_REG0_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + uint32_t : 1; + __IOM uint32_t MSTOP4_ON : 1; + __IOM uint32_t MSTOP5_ON : 1; + __IOM uint32_t MSTOP6_ON : 1; + __IOM uint32_t MSTOP7_ON : 1; + __IOM uint32_t MSTOP8_ON : 1; + __IOM uint32_t MSTOP9_ON : 1; + __IOM uint32_t MSTOP10_ON : 1; + __IOM uint32_t MSTOP11_ON : 1; + uint32_t : 4; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + uint32_t : 1; + __IOM uint32_t MSTOP4_ON_WEN : 1; + __IOM uint32_t MSTOP5_ON_WEN : 1; + __IOM uint32_t MSTOP6_ON_WEN : 1; + __IOM uint32_t MSTOP7_ON_WEN : 1; + __IOM uint32_t MSTOP8_ON_WEN : 1; + __IOM uint32_t MSTOP9_ON_WEN : 1; + __IOM uint32_t MSTOP10_ON_WEN : 1; + __IOM uint32_t MSTOP11_ON_WEN : 1; + uint32_t : 4; + } CPG_BUS_REG0_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_BUS_REG1_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + __IOM uint32_t MSTOP3_ON : 1; + uint32_t : 1; + __IOM uint32_t MSTOP5_ON : 1; + __IOM uint32_t MSTOP6_ON : 1; + uint32_t : 9; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + __IOM uint32_t MSTOP3_ON_WEN : 1; + uint32_t : 1; + __IOM uint32_t MSTOP5_ON_WEN : 1; + __IOM uint32_t MSTOP6_ON_WEN : 1; + uint32_t : 9; + } CPG_BUS_REG1_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_BUS_TZCDDR_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + uint32_t : 13; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + uint32_t : 13; + } CPG_BUS_TZCDDR_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_MHU_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + uint32_t : 15; + __IOM uint32_t MSTOP0_ON_WEN : 1; + uint32_t : 15; + } CPG_MHU_MSTOP_b; + }; + __IM uint8_t RESERVED55[4]; + union + { + __IOM uint32_t CPG_BUS_MCPU3_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + __IOM uint32_t MSTOP3_ON : 1; + __IOM uint32_t MSTOP4_ON : 1; + __IOM uint32_t MSTOP5_ON : 1; + __IOM uint32_t MSTOP6_ON : 1; + __IOM uint32_t MSTOP7_ON : 1; + __IOM uint32_t MSTOP8_ON : 1; + __IOM uint32_t MSTOP9_ON : 1; + __IOM uint32_t MSTOP10_ON : 1; + uint32_t : 5; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + __IOM uint32_t MSTOP3_ON_WEN : 1; + __IOM uint32_t MSTOP4_ON_WEN : 1; + __IOM uint32_t MSTOP5_ON_WEN : 1; + __IOM uint32_t MSTOP6_ON_WEN : 1; + __IOM uint32_t MSTOP7_ON_WEN : 1; + __IOM uint32_t MSTOP8_ON_WEN : 1; + __IOM uint32_t MSTOP9_ON_WEN : 1; + __IOM uint32_t MSTOP10_ON_WEN : 1; + uint32_t : 5; + } CPG_BUS_MCPU3_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_BUS_PERI_CPU2_MSTOP; + struct + { + __IOM uint32_t MSTOP0_ON : 1; + __IOM uint32_t MSTOP1_ON : 1; + __IOM uint32_t MSTOP2_ON : 1; + __IOM uint32_t MSTOP3_ON : 1; + __IOM uint32_t MSTOP4_ON : 1; + __IOM uint32_t MSTOP5_ON : 1; + __IOM uint32_t MSTOP6_ON : 1; + __IOM uint32_t MSTOP7_ON : 1; + __IOM uint32_t MSTOP8_ON : 1; + __IOM uint32_t MSTOP9_ON : 1; + uint32_t : 6; + __IOM uint32_t MSTOP0_ON_WEN : 1; + __IOM uint32_t MSTOP1_ON_WEN : 1; + __IOM uint32_t MSTOP2_ON_WEN : 1; + __IOM uint32_t MSTOP3_ON_WEN : 1; + __IOM uint32_t MSTOP4_ON_WEN : 1; + __IOM uint32_t MSTOP5_ON_WEN : 1; + __IOM uint32_t MSTOP6_ON_WEN : 1; + __IOM uint32_t MSTOP7_ON_WEN : 1; + __IOM uint32_t MSTOP8_ON_WEN : 1; + __IOM uint32_t MSTOP9_ON_WEN : 1; + uint32_t : 6; + } CPG_BUS_PERI_CPU2_MSTOP_b; + }; + __IM uint8_t RESERVED56[24]; + union + { + __IOM uint32_t CPG_PWRDN_IP1; + struct + { + __IOM uint32_t PWRDN0_ON : 1; + __IOM uint32_t PWRDN1_ON : 1; + __IOM uint32_t PWRDN2_ON : 1; + __IOM uint32_t PWRDN3_ON : 1; + __IOM uint32_t PWRDN4_ON : 1; + __IOM uint32_t PWRDN5_ON : 1; + __IOM uint32_t PWRDN6_ON : 1; + uint32_t : 1; + __IOM uint32_t PWRDN8_ON : 1; + __IOM uint32_t PWRDN9_ON : 1; + __IOM uint32_t PWRDN10_ON : 1; + __IOM uint32_t PWRDN11_ON : 1; + __IOM uint32_t PWRDN12_ON : 1; + __IOM uint32_t PWRDN13_ON : 1; + __IOM uint32_t PWRDN14_ON : 1; + __IOM uint32_t PWRDN15_ON : 1; + __IOM uint32_t PWRDN0_ON_WEN : 1; + __IOM uint32_t PWRDN1_ON_WEN : 1; + __IOM uint32_t PWRDN2_ON_WEN : 1; + __IOM uint32_t PWRDN3_ON_WEN : 1; + __IOM uint32_t PWRDN4_ON_WEN : 1; + __IOM uint32_t PWRDN5_ON_WEN : 1; + __IOM uint32_t PWRDN6_ON_WEN : 1; + uint32_t : 1; + __IOM uint32_t PWRDN8_ON_WEN : 1; + __IOM uint32_t PWRDN9_ON_WEN : 1; + __IOM uint32_t PWRDN10_ON_WEN : 1; + __IOM uint32_t PWRDN11_ON_WEN : 1; + __IOM uint32_t PWRDN12_ON_WEN : 1; + __IOM uint32_t PWRDN13_ON_WEN : 1; + __IOM uint32_t PWRDN14_ON_WEN : 1; + __IOM uint32_t PWRDN15_ON_WEN : 1; + } CPG_PWRDN_IP1_b; + }; + union + { + __IOM uint32_t CPG_PWRDN_IP2; + struct + { + __IOM uint32_t PWRDN0_ON : 1; + __IOM uint32_t PWRDN1_ON : 1; + __IOM uint32_t PWRDN2_ON : 1; + __IOM uint32_t PWRDN3_ON : 1; + __IOM uint32_t PWRDN4_ON : 1; + uint32_t : 11; + __IOM uint32_t PWRDN0_ON_WEN : 1; + __IOM uint32_t PWRDN1_ON_WEN : 1; + __IOM uint32_t PWRDN2_ON_WEN : 1; + __IOM uint32_t PWRDN3_ON_WEN : 1; + __IOM uint32_t PWRDN4_ON_WEN : 1; + uint32_t : 11; + } CPG_PWRDN_IP2_b; + }; + __IM uint8_t RESERVED57[8]; + union + { + __IOM uint32_t CPG_PWRDN_MSTOP; + struct + { + __IOM uint32_t PWRDN0_ON : 1; + uint32_t : 15; + __IOM uint32_t PWRDN0_ON_WEN : 1; + uint32_t : 15; + } CPG_PWRDN_MSTOP_b; + }; + union + { + __IOM uint32_t CPG_PWRDN_CLKON; + struct + { + __IOM uint32_t PWRDN0_ON : 1; + uint32_t : 15; + __IOM uint32_t PWRDN0_ON_WEN : 1; + uint32_t : 15; + } CPG_PWRDN_CLKON_b; + }; + union + { + __IOM uint32_t CPG_PWRDN_RST; + struct + { + __IOM uint32_t PWRDN0_RST : 1; + uint32_t : 15; + __IOM uint32_t PWRDN0_RST_WEN : 1; + uint32_t : 15; + } CPG_PWRDN_RST_b; + }; + __IM uint8_t RESERVED58[4]; + union + { + __IOM uint32_t CPG_RET_FUNC1; + struct + { + __IOM uint32_t RSTB : 1; + uint32_t : 15; + __IOM uint32_t RSTB_WEN : 1; + uint32_t : 15; + } CPG_RET_FUNC1_b; + }; + union + { + __IOM uint32_t CPG_RET_FUNC2; + struct + { + __IOM uint32_t FUNC_EN : 3; + uint32_t : 29; + } CPG_RET_FUNC2_b; + }; + union + { + __IM uint32_t CPG_RET_FUNC3; + struct + { + __IM uint32_t STATUS : 1; + uint32_t : 31; + } CPG_RET_FUNC3_b; + }; + __IM uint8_t RESERVED59[16]; + union + { + __IOM uint32_t CPG_OTHERFUNC2_REG; + struct + { + __IOM uint32_t RES0_SET : 1; + __IOM uint32_t RES1_SET : 1; + __IOM uint32_t RES2_SET : 1; + __IOM uint32_t RES3_SET : 1; + __IOM uint32_t RES4_SET : 1; + __IOM uint32_t RES5_SET : 1; + __IOM uint32_t RES6_SET : 1; + __IOM uint32_t RES7_SET : 1; + __IOM uint32_t RES8_SET : 1; + __IOM uint32_t RES9_SET : 1; + __IOM uint32_t RES10_SET : 1; + __IOM uint32_t RES11_SET : 1; + __IOM uint32_t RES12_SET : 1; + __IOM uint32_t RES13_SET : 1; + __IOM uint32_t RES14_SET : 1; + __IOM uint32_t RES15_SET : 1; + __IOM uint32_t RES0_ON_WEN : 1; + __IOM uint32_t RES1_ON_WEN : 1; + __IOM uint32_t RES2_ON_WEN : 1; + __IOM uint32_t RES3_ON_WEN : 1; + __IOM uint32_t RES4_ON_WEN : 1; + __IOM uint32_t RES5_ON_WEN : 1; + __IOM uint32_t RES6_ON_WEN : 1; + __IOM uint32_t RES7_ON_WEN : 1; + __IOM uint32_t RES8_ON_WEN : 1; + __IOM uint32_t RES9_ON_WEN : 1; + __IOM uint32_t RES10_ON_WEN : 1; + __IOM uint32_t RES11_ON_WEN : 1; + __IOM uint32_t RES12_ON_WEN : 1; + __IOM uint32_t RES13_ON_WEN : 1; + __IOM uint32_t RES14_ON_WEN : 1; + __IOM uint32_t RES15_ON_WEN : 1; + } CPG_OTHERFUNC2_REG_b; + }; +} R_CPG_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_CPG_BASE 0x41010000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_CPG ((R_CPG_Type *) R_CPG_BASE) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/dmac_b_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/dmac_b_iodefine.h new file mode 100644 index 00000000..44319dd3 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/dmac_b_iodefine.h @@ -0,0 +1,393 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : dmac_b_iodefine.h + * Version : 1.00 + * Description : IO define file for dmac. + *********************************************************************************************************************/ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef DMAC_B_IODEFINE_H +#define DMAC_B_IODEFINE_H + +typedef struct +{ + __IOM uint32_t SA; + __IOM uint32_t DA; + __IOM uint32_t TB; +} R_DMAC_B0_GRP_CH_N_Type; + +typedef struct +{ + __IOM R_DMAC_B0_GRP_CH_N_Type N[2]; + __IM uint32_t CRSA; + __IM uint32_t CRDA; + __IM uint32_t CRTB; + + union + { + __IM uint32_t CHSTAT; + + struct + { + __IM uint32_t EN : 1; + __IM uint32_t RQST : 1; + __IM uint32_t TACT : 1; + __IM uint32_t SUS : 1; + __IM uint32_t ER : 1; + __IM uint32_t END : 1; + __IM uint32_t TC : 1; + __IM uint32_t SR : 1; + __IM uint32_t DL : 1; + __IM uint32_t DW : 1; + __IM uint32_t DER : 1; + __IM uint32_t MODE : 1; + uint32_t : 4; + __IM uint32_t INTMSK : 1; + uint32_t : 15; + } CHSTAT_b; + }; + + union + { + __IOM uint32_t CHCTRL; + + struct + { + __IOM uint32_t SETEN : 1; + __IOM uint32_t CLREN : 1; + __IOM uint32_t STG : 1; + __IOM uint32_t SWRST : 1; + __IOM uint32_t CLRRQ : 1; + __IOM uint32_t CLREND : 1; + __IOM uint32_t CLRTC : 1; + uint32_t : 1; + __IOM uint32_t SETSUS : 1; + __IOM uint32_t CLRSUS : 1; + uint32_t : 6; + __IOM uint32_t SETINTMSK : 1; + __IOM uint32_t CLRINTMSK : 1; + uint32_t : 14; + } CHCTRL_b; + }; + + union + { + __IOM uint32_t CHCFG; + + struct + { + __IOM uint32_t SEL : 3; + __IOM uint32_t REQD : 1; + __IOM uint32_t LOEN : 1; + __IOM uint32_t HIEN : 1; + __IOM uint32_t LVL : 1; + uint32_t : 1; + __IOM uint32_t AM : 3; + uint32_t : 1; + __IOM uint32_t SDS : 4; + __IOM uint32_t DDS : 4; + __IOM uint32_t SAD : 1; + __IOM uint32_t DAD : 1; + __IOM uint32_t TM : 1; + uint32_t : 1; + __IOM uint32_t DEM : 1; + __IOM uint32_t TCM : 1; + uint32_t : 1; + __IOM uint32_t SBE : 1; + __IOM uint32_t RSEL : 1; + __IOM uint32_t RSW : 1; + __IOM uint32_t REN : 1; + __IOM uint32_t DMS : 1; + } CHCFG_b; + }; + + union + { + __IOM uint32_t CHITVL; + + struct + { + __IOM uint32_t ITVL : 16; + uint32_t : 16; + } CHITVL_b; + }; + + union + { + __IOM uint32_t CHEXT; + + struct + { + __IOM uint32_t SPR : 3; + uint32_t : 1; + __IOM uint32_t SCA : 4; + __IOM uint32_t DPR : 3; + uint32_t : 1; + __IOM uint32_t DCA : 4; + uint32_t : 16; + } CHEXT_b; + }; + + __IOM uint32_t NXLA; + __IM uint32_t CRLA; +} R_DMAC_B0_GRP_CH_Type; + +typedef struct +{ + __IOM R_DMAC_B0_GRP_CH_Type CH[8]; + __IM uint32_t RESERVED[64]; + + union + { + __IOM uint32_t DCTRL; + + struct + { + __IOM uint32_t PR : 1; + __IOM uint32_t LVINT : 1; + uint32_t : 14; + __IOM uint32_t LDPR : 3; + uint32_t : 1; + __IOM uint32_t LDCA : 4; + __IOM uint32_t LWPR : 3; + uint32_t : 1; + __IOM uint32_t LWCA : 4; + } DCTRL_b; + }; + + __IM uint32_t RESERVED1[3]; + + union + { + __IM uint32_t DSTAT_EN; + + struct + { + __IM uint32_t EN0 : 1; + __IM uint32_t EN1 : 1; + __IM uint32_t EN2 : 1; + __IM uint32_t EN3 : 1; + __IM uint32_t EN4 : 1; + __IM uint32_t EN5 : 1; + __IM uint32_t EN6 : 1; + __IM uint32_t EN7 : 1; + uint32_t : 24; + } DSTAT_EN_b; + }; + + union + { + __IM uint32_t DSTAT_ER; + + struct + { + __IM uint32_t ER0 : 1; + __IM uint32_t ER1 : 1; + __IM uint32_t ER2 : 1; + __IM uint32_t ER3 : 1; + __IM uint32_t ER4 : 1; + __IM uint32_t ER5 : 1; + __IM uint32_t ER6 : 1; + __IM uint32_t ER7 : 1; + uint32_t : 24; + } DSTAT_ER_b; + }; + + union + { + __IM uint32_t DSTAT_END; + + struct + { + __IM uint32_t END0 : 1; + __IM uint32_t END1 : 1; + __IM uint32_t END2 : 1; + __IM uint32_t END3 : 1; + __IM uint32_t END4 : 1; + __IM uint32_t END5 : 1; + __IM uint32_t END6 : 1; + __IM uint32_t END7 : 1; + uint32_t : 24; + } DSTAT_END_b; + }; + + union + { + __IM uint32_t DST_TC; + + struct + { + __IM uint32_t TC0 : 1; + __IM uint32_t TC1 : 1; + __IM uint32_t TC2 : 1; + __IM uint32_t TC3 : 1; + __IM uint32_t TC4 : 1; + __IM uint32_t TC5 : 1; + __IM uint32_t TC6 : 1; + __IM uint32_t TC7 : 1; + uint32_t : 24; + } DST_TC_b; + }; + + union + { + __IM uint32_t DSTAT_SUS; + + struct + { + __IM uint32_t SUS0 : 1; + __IM uint32_t SUS1 : 1; + __IM uint32_t SUS2 : 1; + __IM uint32_t SUS3 : 1; + __IM uint32_t SUS4 : 1; + __IM uint32_t SUS5 : 1; + __IM uint32_t SUS6 : 1; + __IM uint32_t SUS7 : 1; + uint32_t : 24; + } DSTAT_SUS_b; + }; + __IM uint32_t RESERVED3[55]; +} R_DMAC_B0_GRP_Type; + +typedef struct +{ + __IOM R_DMAC_B0_GRP_Type GRP[2]; +} R_DMAC_B0_Type; + +typedef struct +{ + union + { + __IOM uint32_t DMARS0; + struct + { + __IOM uint32_t CH0_RID : 2; + __IOM uint32_t CH0_MID : 8; + uint32_t : 6; + __IOM uint32_t CH1_RID : 2; + __IOM uint32_t CH1_MID : 8; + uint32_t : 6; + } DMARS0_b; + }; + union + { + __IOM uint32_t DMARS1; + struct + { + __IOM uint32_t CH2_RID : 2; + __IOM uint32_t CH2_MID : 8; + uint32_t : 6; + __IOM uint32_t CH3_RID : 2; + __IOM uint32_t CH3_MID : 8; + uint32_t : 6; + } DMARS1_b; + }; + union + { + __IOM uint32_t DMARS2; + struct + { + __IOM uint32_t CH4_RID : 2; + __IOM uint32_t CH4_MID : 8; + uint32_t : 6; + __IOM uint32_t CH5_RID : 2; + __IOM uint32_t CH5_MID : 8; + uint32_t : 6; + } DMARS2_b; + }; + union + { + __IOM uint32_t DMARS3; + struct + { + __IOM uint32_t CH6_RID : 2; + __IOM uint32_t CH6_MID : 8; + uint32_t : 6; + __IOM uint32_t CH7_RID : 2; + __IOM uint32_t CH7_MID : 8; + uint32_t : 6; + } DMARS3_b; + }; + union + { + __IOM uint32_t DMARS4; + struct + { + __IOM uint32_t CH8_RID : 2; + __IOM uint32_t CH8_MID : 8; + uint32_t : 6; + __IOM uint32_t CH9_RID : 2; + __IOM uint32_t CH9_MID : 8; + uint32_t : 6; + } DMARS4_b; + }; + union + { + __IOM uint32_t DMARS5; + struct + { + __IOM uint32_t CH10_RID : 2; + __IOM uint32_t CH10_MID : 8; + uint32_t : 6; + __IOM uint32_t CH11_RID : 2; + __IOM uint32_t CH11_MID : 8; + uint32_t : 6; + } DMARS5_b; + }; + union + { + __IOM uint32_t DMARS6; + struct + { + __IOM uint32_t CH12_RID : 2; + __IOM uint32_t CH12_MID : 8; + uint32_t : 6; + __IOM uint32_t CH13_RID : 2; + __IOM uint32_t CH13_MID : 8; + uint32_t : 6; + } DMARS6_b; + }; + union + { + __IOM uint32_t DMARS7; + struct + { + __IOM uint32_t CH14_RID : 2; + __IOM uint32_t CH14_MID : 8; + uint32_t : 6; + __IOM uint32_t CH15_RID : 2; + __IOM uint32_t CH15_MID : 8; + uint32_t : 6; + } DMARS7_b; + }; +} R_DMAC_B0_EX_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +#define R_DMAC_B0_BASE 0x41800000 +#define R_DMAC_B1_BASE 0x41820000 +#define R_DMAC_B0_EX_BASE 0x41810000 +#define R_DMAC_B1_EX_BASE 0x41830000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +#define R_DMAC_B0 ((R_DMAC_B0_Type *) R_DMAC_B0_BASE) +#define R_DMAC_B1 ((R_DMAC_B0_Type *) R_DMAC_B1_BASE) +#define R_DMAC_B0_EX ((R_DMAC_B0_EX_Type *) R_DMAC_B0_EX_BASE) +#define R_DMAC_B1_EX ((R_DMAC_B0_EX_Type *) R_DMAC_B1_EX_BASE) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gpio_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gpio_iodefine.h new file mode 100644 index 00000000..fc29c0e6 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gpio_iodefine.h @@ -0,0 +1,6964 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : gpio_iodefine.h + * Version : 1.00 + * Description : IO define file for gpio. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef GPIO_IODEFINE_H +#define GPIO_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint8_t P_20; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + uint8_t : 4; + } P_20_b; + }; + union + { + __IOM uint8_t P_21; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + uint8_t : 3; + } P_21_b; + }; + union + { + __IOM uint8_t P_22; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + uint8_t : 3; + } P_22_b; + }; + union + { + __IOM uint8_t P_23; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + uint8_t : 4; + } P_23_b; + }; + union + { + __IOM uint8_t P_24; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + uint8_t : 6; + } P_24_b; + }; + union + { + __IOM uint8_t P_25; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + uint8_t : 3; + } P_25_b; + }; + union + { + __IOM uint8_t P_26; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + uint8_t : 5; + } P_26_b; + }; + union + { + __IOM uint8_t P_27; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + uint8_t : 4; + } P_27_b; + }; + union + { + __IOM uint8_t P_28; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + uint8_t : 6; + } P_28_b; + }; + union + { + __IOM uint8_t P_29; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + uint8_t : 4; + } P_29_b; + }; + union + { + __IOM uint8_t P_2A; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + __IOM uint8_t P5 : 1; + uint8_t : 2; + } P_2A_b; + }; + __IM uint8_t RESERVED[5]; + union + { + __IOM uint8_t P_30; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + uint8_t : 3; + } P_30_b; + }; + union + { + __IOM uint8_t P_31; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + uint8_t : 4; + } P_31_b; + }; + union + { + __IOM uint8_t P_32; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + uint8_t : 4; + } P_32_b; + }; + union + { + __IOM uint8_t P_33; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + __IOM uint8_t P5 : 1; + uint8_t : 2; + } P_33_b; + }; + union + { + __IOM uint8_t P_34; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + uint8_t : 3; + } P_34_b; + }; + union + { + __IOM uint8_t P_35; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + uint8_t : 3; + } P_35_b; + }; + union + { + __IOM uint8_t P_36; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + uint8_t : 4; + } P_36_b; + }; + union + { + __IOM uint8_t P_37; + struct + { + __IOM uint8_t P0 : 1; + __IOM uint8_t P1 : 1; + __IOM uint8_t P2 : 1; + __IOM uint8_t P3 : 1; + __IOM uint8_t P4 : 1; + uint8_t : 3; + } P_37_b; + }; + __IM uint8_t RESERVED1[264]; + union + { + __IOM uint16_t PM_20; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_20_byte; + struct + { + __IOM uint8_t PM20_0 : 2; + __IOM uint8_t PM20_1 : 2; + __IOM uint8_t PM20_2 : 2; + __IOM uint8_t PM20_3 : 2; + uint8_t : 8; + } PM_20_b; + }; + union + { + __IOM uint16_t PM_21; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_21_byte; + struct + { + __IOM uint8_t PM21_0 : 2; + __IOM uint8_t PM21_1 : 2; + __IOM uint8_t PM21_2 : 2; + __IOM uint8_t PM21_3 : 2; + __IOM uint8_t PM21_4 : 2; + uint8_t : 6; + } PM_21_b; + }; + union + { + __IOM uint16_t PM_22; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_22_byte; + struct + { + __IOM uint8_t PM22_0 : 2; + __IOM uint8_t PM22_1 : 2; + __IOM uint8_t PM22_2 : 2; + __IOM uint8_t PM22_3 : 2; + __IOM uint8_t PM22_4 : 2; + uint8_t : 6; + } PM_22_b; + }; + union + { + __IOM uint16_t PM_23; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_23_byte; + struct + { + __IOM uint8_t PM23_0 : 2; + __IOM uint8_t PM23_1 : 2; + __IOM uint8_t PM23_2 : 2; + __IOM uint8_t PM23_3 : 2; + uint8_t : 8; + } PM_23_b; + }; + union + { + __IOM uint16_t PM_24; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_24_byte; + struct + { + __IOM uint8_t PM24_0 : 2; + __IOM uint8_t PM24_1 : 2; + uint8_t : 4; + uint8_t : 8; + } PM_24_b; + }; + union + { + __IOM uint16_t PM_25; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_25_byte; + struct + { + __IOM uint8_t PM25_0 : 2; + __IOM uint8_t PM25_1 : 2; + __IOM uint8_t PM25_2 : 2; + __IOM uint8_t PM25_3 : 2; + uint8_t : 8; + } PM_25_b; + }; + union + { + __IOM uint16_t PM_26; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_26_byte; + struct + { + __IOM uint8_t PM26_0 : 2; + __IOM uint8_t PM26_1 : 2; + __IOM uint8_t PM26_2 : 2; + uint8_t : 2; + uint8_t : 8; + } PM_26_b; + }; + union + { + __IOM uint16_t PM_27; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_27_byte; + struct + { + __IOM uint8_t PM27_0 : 2; + __IOM uint8_t PM27_1 : 2; + __IOM uint8_t PM27_2 : 2; + __IOM uint8_t PM27_3 : 2; + uint8_t : 8; + } PM_27_b; + }; + union + { + __IOM uint16_t PM_28; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_28_byte; + struct + { + __IOM uint8_t PM28_0 : 2; + __IOM uint8_t PM28_1 : 2; + uint8_t : 4; + uint8_t : 8; + } PM_28_b; + }; + union + { + __IOM uint16_t PM_29; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_29_byte; + struct + { + __IOM uint8_t PM29_0 : 2; + __IOM uint8_t PM29_1 : 2; + __IOM uint8_t PM29_2 : 2; + __IOM uint8_t PM29_3 : 2; + uint8_t : 8; + } PM_29_b; + }; + union + { + __IOM uint16_t PM_2A; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_2A_byte; + struct + { + __IOM uint8_t PM2A_0 : 2; + __IOM uint8_t PM2A_1 : 2; + __IOM uint8_t PM2A_2 : 2; + __IOM uint8_t PM2A_3 : 2; + __IOM uint8_t PM2A_4 : 2; + __IOM uint8_t PM2A_5 : 2; + uint8_t : 4; + } PM_2A_b; + }; + __IM uint8_t RESERVED2[10]; + union + { + __IOM uint16_t PM_30; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_30_byte; + struct + { + __IOM uint8_t PM30_0 : 2; + __IOM uint8_t PM30_1 : 2; + __IOM uint8_t PM30_2 : 2; + __IOM uint8_t PM30_3 : 2; + uint8_t : 8; + } PM_30_b; + }; + union + { + __IOM uint16_t PM_31; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_31_byte; + struct + { + __IOM uint8_t PM31_0 : 2; + __IOM uint8_t PM31_1 : 2; + __IOM uint8_t PM31_2 : 2; + uint8_t : 2; + uint8_t : 8; + } PM_31_b; + }; + union + { + __IOM uint16_t PM_32; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_32_byte; + struct + { + __IOM uint8_t PM32_0 : 2; + __IOM uint8_t PM32_1 : 2; + __IOM uint8_t PM32_2 : 2; + uint8_t : 2; + uint8_t : 8; + } PM_32_b; + }; + union + { + __IOM uint16_t PM_33; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_33_byte; + struct + { + __IOM uint8_t PM33_0 : 2; + __IOM uint8_t PM33_1 : 2; + __IOM uint8_t PM33_2 : 2; + __IOM uint8_t PM33_3 : 2; + __IOM uint8_t PM33_4 : 2; + __IOM uint8_t PM33_5 : 2; + uint8_t : 4; + } PM_33_b; + }; + union + { + __IOM uint16_t PM_34; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_34_byte; + struct + { + __IOM uint8_t PM34_0 : 2; + __IOM uint8_t PM34_1 : 2; + __IOM uint8_t PM34_2 : 2; + __IOM uint8_t PM34_3 : 2; + uint8_t : 8; + } PM_34_b; + }; + union + { + __IOM uint16_t PM_35; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_35_byte; + struct + { + __IOM uint8_t PM35_0 : 2; + __IOM uint8_t PM35_1 : 2; + __IOM uint8_t PM35_2 : 2; + __IOM uint8_t PM35_3 : 2; + uint8_t : 8; + } PM_35_b; + }; + union + { + __IOM uint16_t PM_36; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_36_byte; + struct + { + __IOM uint8_t PM36_0 : 2; + __IOM uint8_t PM36_1 : 2; + __IOM uint8_t PM36_2 : 2; + uint8_t : 2; + uint8_t : 8; + } PM_36_b; + }; + union + { + __IOM uint16_t PM_37; + struct + { + __IOM uint8_t L; + __IOM uint8_t H; + } PM_37_byte; + struct + { + __IOM uint8_t PM37_0 : 2; + __IOM uint8_t PM37_1 : 2; + __IOM uint8_t PM37_2 : 2; + __IOM uint8_t PM37_3 : 2; + uint8_t : 8; + } PM_37_b; + }; + __IM uint8_t RESERVED3[176]; + union + { + __IOM uint8_t PMC_20; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + uint8_t : 4; + } PMC_20_b; + }; + union + { + __IOM uint8_t PMC_21; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + uint8_t : 3; + } PMC_21_b; + }; + union + { + __IOM uint8_t PMC_22; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + uint8_t : 3; + } PMC_22_b; + }; + union + { + __IOM uint8_t PMC_23; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + uint8_t : 4; + } PMC_23_b; + }; + union + { + __IOM uint8_t PMC_24; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + uint8_t : 6; + } PMC_24_b; + }; + union + { + __IOM uint8_t PMC_25; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + uint8_t : 3; + } PMC_25_b; + }; + union + { + __IOM uint8_t PMC_26; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + uint8_t : 5; + } PMC_26_b; + }; + union + { + __IOM uint8_t PMC_27; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + uint8_t : 4; + } PMC_27_b; + }; + union + { + __IOM uint8_t PMC_28; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + uint8_t : 6; + } PMC_28_b; + }; + union + { + __IOM uint8_t PMC_29; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + uint8_t : 4; + } PMC_29_b; + }; + union + { + __IOM uint8_t PMC_2A; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + __IOM uint8_t PMC5 : 1; + uint8_t : 2; + } PMC_2A_b; + }; + __IM uint8_t RESERVED4[5]; + union + { + __IOM uint8_t PMC_30; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + uint8_t : 3; + } PMC_30_b; + }; + union + { + __IOM uint8_t PMC_31; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + uint8_t : 4; + } PMC_31_b; + }; + union + { + __IOM uint8_t PMC_32; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + uint8_t : 4; + } PMC_32_b; + }; + union + { + __IOM uint8_t PMC_33; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + __IOM uint8_t PMC5 : 1; + uint8_t : 2; + } PMC_33_b; + }; + union + { + __IOM uint8_t PMC_34; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + uint8_t : 3; + } PMC_34_b; + }; + union + { + __IOM uint8_t PMC_35; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + uint8_t : 3; + } PMC_35_b; + }; + union + { + __IOM uint8_t PMC_36; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + uint8_t : 4; + } PMC_36_b; + }; + union + { + __IOM uint8_t PMC_37; + struct + { + __IOM uint8_t PMC0 : 1; + __IOM uint8_t PMC1 : 1; + __IOM uint8_t PMC2 : 1; + __IOM uint8_t PMC3 : 1; + __IOM uint8_t PMC4 : 1; + uint8_t : 3; + } PMC_37_b; + }; + __IM uint8_t RESERVED5[584]; + union + { + __IOM uint32_t PFC_20; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_20_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_20_byte; + struct + { + __IOM uint8_t PFC20_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC20_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC20_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC20_3 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + } PFC_20_b; + }; + union + { + __IOM uint32_t PFC_21; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_21_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_21_byte; + struct + { + __IOM uint8_t PFC21_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC21_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC21_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC21_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC21_4 : 3; + uint8_t : 5; + uint8_t : 8; + } PFC_21_b; + }; + union + { + __IOM uint32_t PFC_22; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_22_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_22_byte; + struct + { + __IOM uint8_t PFC22_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC22_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC22_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC22_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC22_4 : 3; + uint8_t : 5; + uint8_t : 8; + } PFC_22_b; + }; + union + { + __IOM uint32_t PFC_23; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_23_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_23_byte; + struct + { + __IOM uint8_t PFC23_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC23_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC23_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC23_3 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + } PFC_23_b; + }; + union + { + __IOM uint32_t PFC_24; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_24_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_24_byte; + struct + { + __IOM uint8_t PFC24_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC24_1 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PFC_24_b; + }; + union + { + __IOM uint32_t PFC_25; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_25_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_25_byte; + struct + { + __IOM uint8_t PFC25_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC25_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC25_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC25_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC25_4 : 3; + uint8_t : 5; + uint8_t : 8; + } PFC_25_b; + }; + union + { + __IOM uint32_t PFC_26; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_26_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_26_byte; + struct + { + __IOM uint8_t PFC26_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC26_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC26_2 : 3; + uint8_t : 5; + uint8_t : 8; + uint8_t : 8; + } PFC_26_b; + }; + union + { + __IOM uint32_t PFC_27; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_27_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_27_byte; + struct + { + __IOM uint8_t PFC27_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC27_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC27_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC27_3 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + } PFC_27_b; + }; + union + { + __IOM uint32_t PFC_28; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_28_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_28_byte; + struct + { + __IOM uint8_t PFC28_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC28_1 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PFC_28_b; + }; + union + { + __IOM uint32_t PFC_29; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_29_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_29_byte; + struct + { + __IOM uint8_t PFC29_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC29_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC29_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC29_3 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + } PFC_29_b; + }; + union + { + __IOM uint32_t PFC_2A; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_2A_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_2A_byte; + struct + { + __IOM uint8_t PFC2A_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC2A_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC2A_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC2A_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC2A_4 : 3; + uint8_t : 1; + __IOM uint8_t PFC2A_5 : 3; + uint8_t : 1; + uint8_t : 8; + } PFC_2A_b; + }; + __IM uint8_t RESERVED6[20]; + union + { + __IOM uint32_t PFC_30; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_30_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_30_byte; + struct + { + __IOM uint8_t PFC30_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC30_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC30_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC30_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC30_4 : 3; + uint8_t : 5; + uint8_t : 8; + } PFC_30_b; + }; + union + { + __IOM uint32_t PFC_31; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_31_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_31_byte; + struct + { + __IOM uint8_t PFC31_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC31_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC31_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC31_3 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + } PFC_31_b; + }; + union + { + __IOM uint32_t PFC_32; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_32_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_32_byte; + struct + { + __IOM uint8_t PFC32_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC32_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC32_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC32_3 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + } PFC_32_b; + }; + union + { + __IOM uint32_t PFC_33; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_33_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_33_byte; + struct + { + __IOM uint8_t PFC33_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC33_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC33_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC33_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC33_4 : 3; + uint8_t : 1; + __IOM uint8_t PFC33_5 : 3; + uint8_t : 1; + uint8_t : 8; + } PFC_33_b; + }; + union + { + __IOM uint32_t PFC_34; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_34_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_34_byte; + struct + { + __IOM uint8_t PFC34_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC34_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC34_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC34_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC34_4 : 3; + uint8_t : 5; + uint8_t : 8; + } PFC_34_b; + }; + union + { + __IOM uint32_t PFC_35; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_35_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_35_byte; + struct + { + __IOM uint8_t PFC35_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC35_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC35_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC35_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC35_4 : 3; + uint8_t : 5; + uint8_t : 8; + } PFC_35_b; + }; + union + { + __IOM uint32_t PFC_36; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_36_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_36_byte; + struct + { + __IOM uint8_t PFC36_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC36_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC36_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC36_3 : 3; + uint8_t : 1; + uint8_t : 8; + uint8_t : 8; + } PFC_36_b; + }; + union + { + __IOM uint32_t PFC_37; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PFC_37_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PFC_37_byte; + struct + { + __IOM uint8_t PFC37_0 : 3; + uint8_t : 1; + __IOM uint8_t PFC37_1 : 3; + uint8_t : 1; + __IOM uint8_t PFC37_2 : 3; + uint8_t : 1; + __IOM uint8_t PFC37_3 : 3; + uint8_t : 1; + __IOM uint8_t PFC37_4 : 3; + uint8_t : 5; + uint8_t : 8; + } PFC_37_b; + }; + __IM uint8_t RESERVED7[832]; + union + { + __IM uint8_t PIN_20; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + uint8_t : 4; + } PIN_20_b; + }; + union + { + __IM uint8_t PIN_21; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + uint8_t : 3; + } PIN_21_b; + }; + union + { + __IM uint8_t PIN_22; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + uint8_t : 3; + } PIN_22_b; + }; + union + { + __IM uint8_t PIN_23; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + uint8_t : 4; + } PIN_23_b; + }; + union + { + __IM uint8_t PIN_24; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + uint8_t : 6; + } PIN_24_b; + }; + union + { + __IM uint8_t PIN_25; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + uint8_t : 3; + } PIN_25_b; + }; + union + { + __IM uint8_t PIN_26; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + uint8_t : 5; + } PIN_26_b; + }; + union + { + __IM uint8_t PIN_27; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + uint8_t : 4; + } PIN_27_b; + }; + union + { + __IM uint8_t PIN_28; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + uint8_t : 6; + } PIN_28_b; + }; + union + { + __IM uint8_t PIN_29; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + uint8_t : 4; + } PIN_29_b; + }; + union + { + __IM uint8_t PIN_2A; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + __IM uint8_t PIN5 : 1; + uint8_t : 2; + } PIN_2A_b; + }; + __IM uint8_t RESERVED8[5]; + union + { + __IM uint8_t PIN_30; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + uint8_t : 3; + } PIN_30_b; + }; + union + { + __IM uint8_t PIN_31; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + uint8_t : 4; + } PIN_31_b; + }; + union + { + __IM uint8_t PIN_32; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + uint8_t : 4; + } PIN_32_b; + }; + union + { + __IM uint8_t PIN_33; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + __IM uint8_t PIN5 : 1; + uint8_t : 2; + } PIN_33_b; + }; + union + { + __IM uint8_t PIN_34; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + uint8_t : 3; + } PIN_34_b; + }; + union + { + __IM uint8_t PIN_35; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + uint8_t : 3; + } PIN_35_b; + }; + union + { + __IM uint8_t PIN_36; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + uint8_t : 4; + } PIN_36_b; + }; + union + { + __IM uint8_t PIN_37; + struct + { + __IM uint8_t PIN0 : 1; + __IM uint8_t PIN1 : 1; + __IM uint8_t PIN2 : 1; + __IM uint8_t PIN3 : 1; + __IM uint8_t PIN4 : 1; + uint8_t : 3; + } PIN_37_b; + }; + __IM uint8_t RESERVED9[2000]; + union + { + __IOM uint32_t IOLH_01; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_01_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_01_byte; + struct + { + __IOM uint8_t TMS_SWDIO : 2; + uint8_t : 6; + __IOM uint8_t TDO : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } IOLH_01_b; + }; + __IM uint8_t RESERVED10[20]; + union + { + __IOM uint32_t IOLH_04_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_04_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_04_L_byte; + struct + { + __IOM uint8_t XSPI_SPCLK : 2; + uint8_t : 6; + __IOM uint8_t XSPI_RESET_N : 2; + uint8_t : 6; + __IOM uint8_t XSPI_WP_N : 2; + uint8_t : 6; + __IOM uint8_t XSPI_DS : 2; + uint8_t : 6; + } IOLH_04_L_b; + }; + union + { + __IOM uint32_t IOLH_04_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_04_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_04_H_byte; + struct + { + __IOM uint8_t XSPI_CS0_N : 2; + uint8_t : 6; + __IOM uint8_t XSPI_CS1_N : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } IOLH_04_H_b; + }; + union + { + __IOM uint32_t IOLH_05_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_05_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_05_L_byte; + struct + { + __IOM uint8_t XSPI_IO0 : 2; + uint8_t : 6; + __IOM uint8_t XSPI_IO1 : 2; + uint8_t : 6; + __IOM uint8_t XSPI_IO2 : 2; + uint8_t : 6; + __IOM uint8_t XSPI_IO3 : 2; + uint8_t : 6; + } IOLH_05_L_b; + }; + union + { + __IOM uint32_t IOLH_05_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_05_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_05_H_byte; + struct + { + __IOM uint8_t XSPI_IO4 : 2; + uint8_t : 6; + __IOM uint8_t XSPI_IO5 : 2; + uint8_t : 6; + __IOM uint8_t XSPI_IO6 : 2; + uint8_t : 6; + __IOM uint8_t XSPI_IO7 : 2; + uint8_t : 6; + } IOLH_05_H_b; + }; + union + { + __IOM uint32_t IOLH_06; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_06_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_06_byte; + struct + { + __IOM uint8_t WDTOVF_PERROUT : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IOLH_06_b; + }; + __IM uint8_t RESERVED11[76]; + union + { + __IOM uint32_t IOLH_10; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_10_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_10_byte; + struct + { + __IOM uint8_t SD0_CLK : 2; + uint8_t : 6; + __IOM uint8_t SD0_CMD : 2; + uint8_t : 6; + __IOM uint8_t SD0_RST_N : 2; + uint8_t : 6; + uint8_t : 8; + } IOLH_10_b; + }; + __IM uint8_t RESERVED12[4]; + union + { + __IOM uint32_t IOLH_11_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_11_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_11_L_byte; + struct + { + __IOM uint8_t SD0_DATA0 : 2; + uint8_t : 6; + __IOM uint8_t SD0_DATA1 : 2; + uint8_t : 6; + __IOM uint8_t SD0_DATA2 : 2; + uint8_t : 6; + __IOM uint8_t SD0_DATA3 : 2; + uint8_t : 6; + } IOLH_11_L_b; + }; + union + { + __IOM uint32_t IOLH_11_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_11_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_11_H_byte; + struct + { + __IOM uint8_t SD0_DATA4 : 2; + uint8_t : 6; + __IOM uint8_t SD0_DATA5 : 2; + uint8_t : 6; + __IOM uint8_t SD0_DATA6 : 2; + uint8_t : 6; + __IOM uint8_t SD0_DATA7 : 2; + uint8_t : 6; + } IOLH_11_H_b; + }; + union + { + __IOM uint32_t IOLH_12; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_12_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_12_byte; + struct + { + __IOM uint8_t SD1_CLK : 2; + uint8_t : 6; + __IOM uint8_t SD1_CMD : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } IOLH_12_b; + }; + __IM uint8_t RESERVED13[4]; + union + { + __IOM uint32_t IOLH_13; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_13_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_13_byte; + struct + { + __IOM uint8_t SD1_DATA0 : 2; + uint8_t : 6; + __IOM uint8_t SD1_DATA1 : 2; + uint8_t : 6; + __IOM uint8_t SD1_DATA2 : 2; + uint8_t : 6; + __IOM uint8_t SD1_DATA3 : 2; + uint8_t : 6; + } IOLH_13_b; + }; + __IM uint8_t RESERVED14[100]; + union + { + __IOM uint32_t IOLH_20; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_20_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_20_byte; + struct + { + __IOM uint8_t IOLH20_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH20_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH20_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH20_3 : 2; + uint8_t : 6; + } IOLH_20_b; + }; + __IM uint8_t RESERVED15[4]; + union + { + __IOM uint32_t IOLH_21_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_21_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_21_L_byte; + struct + { + __IOM uint8_t IOLH21_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH21_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH21_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH21_L_3 : 2; + uint8_t : 6; + } IOLH_21_L_b; + }; + union + { + __IOM uint32_t IOLH_21_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_21_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_21_H_byte; + struct + { + __IOM uint8_t IOLH21_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IOLH_21_H_b; + }; + union + { + __IOM uint32_t IOLH_22_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_22_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_22_L_byte; + struct + { + __IOM uint8_t IOLH22_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH22_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH22_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH22_L_3 : 2; + uint8_t : 6; + } IOLH_22_L_b; + }; + union + { + __IOM uint32_t IOLH_22_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_22_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_22_H_byte; + struct + { + __IOM uint8_t IOLH22_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IOLH_22_H_b; + }; + union + { + __IOM uint32_t IOLH_23; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_23_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_23_byte; + struct + { + __IOM uint8_t IOLH23_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH23_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH23_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH23_3 : 2; + uint8_t : 6; + } IOLH_23_b; + }; + __IM uint8_t RESERVED16[4]; + union + { + __IOM uint32_t IOLH_24; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_24_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_24_byte; + struct + { + __IOM uint8_t IOLH24_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH24_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } IOLH_24_b; + }; + __IM uint8_t RESERVED17[4]; + union + { + __IOM uint32_t IOLH_25_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_25_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_25_L_byte; + struct + { + __IOM uint8_t IOLH25_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH25_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH25_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH25_L_3 : 2; + uint8_t : 6; + } IOLH_25_L_b; + }; + union + { + __IOM uint32_t IOLH_25_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_25_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_25_H_byte; + struct + { + __IOM uint8_t IOLH25_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IOLH_25_H_b; + }; + union + { + __IOM uint32_t IOLH_26; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_26_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_26_byte; + struct + { + __IOM uint8_t IOLH26_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH26_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH26_2 : 2; + uint8_t : 6; + uint8_t : 8; + } IOLH_26_b; + }; + __IM uint8_t RESERVED18[4]; + union + { + __IOM uint32_t IOLH_27; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_27_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_27_byte; + struct + { + __IOM uint8_t IOLH27_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH27_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH27_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH27_3 : 2; + uint8_t : 6; + } IOLH_27_b; + }; + __IM uint8_t RESERVED19[4]; + union + { + __IOM uint32_t IOLH_28; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_28_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_28_byte; + struct + { + __IOM uint8_t IOLH28_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH28_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } IOLH_28_b; + }; + __IM uint8_t RESERVED20[4]; + union + { + __IOM uint32_t IOLH_29; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_29_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_29_byte; + struct + { + __IOM uint8_t IOLH29_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH29_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH29_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH29_3 : 2; + uint8_t : 6; + } IOLH_29_b; + }; + __IM uint8_t RESERVED21[4]; + union + { + __IOM uint32_t IOLH_2A_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_2A_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_2A_L_byte; + struct + { + __IOM uint8_t IOLH2A_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH2A_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH2A_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH2A_L_3 : 2; + uint8_t : 6; + } IOLH_2A_L_b; + }; + union + { + __IOM uint32_t IOLH_2A_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_2A_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_2A_H_byte; + struct + { + __IOM uint8_t IOLH2A_H_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH2A_H_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } IOLH_2A_H_b; + }; + __IM uint8_t RESERVED22[40]; + union + { + __IOM uint32_t IOLH_30_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_30_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_30_L_byte; + struct + { + __IOM uint8_t IOLH30_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH30_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH30_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH30_L_3 : 2; + uint8_t : 6; + } IOLH_30_L_b; + }; + union + { + __IOM uint32_t IOLH_30_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_30_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_30_H_byte; + struct + { + __IOM uint8_t IOLH30_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IOLH_30_H_b; + }; + union + { + __IOM uint32_t IOLH_31; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_31_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_31_byte; + struct + { + __IOM uint8_t IOLH31_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH31_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH31_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH31_3 : 2; + uint8_t : 6; + } IOLH_31_b; + }; + __IM uint8_t RESERVED23[4]; + union + { + __IOM uint32_t IOLH_32; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_32_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_32_byte; + struct + { + __IOM uint8_t IOLH32_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH32_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH32_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH32_3 : 2; + uint8_t : 6; + } IOLH_32_b; + }; + __IM uint8_t RESERVED24[4]; + union + { + __IOM uint32_t IOLH_33_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_33_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_33_L_byte; + struct + { + __IOM uint8_t IOLH33_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH33_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH33_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH33_L_3 : 2; + uint8_t : 6; + } IOLH_33_L_b; + }; + union + { + __IOM uint32_t IOLH_33_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_33_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_33_H_byte; + struct + { + __IOM uint8_t IOLH33_H_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH33_H_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } IOLH_33_H_b; + }; + union + { + __IOM uint32_t IOLH_34_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_34_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_34_L_byte; + struct + { + __IOM uint8_t IOLH34_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH34_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH34_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH34_L_3 : 2; + uint8_t : 6; + } IOLH_34_L_b; + }; + union + { + __IOM uint32_t IOLH_34_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_34_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_34_H_byte; + struct + { + __IOM uint8_t IOLH34_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IOLH_34_H_b; + }; + union + { + __IOM uint32_t IOLH_35_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_35_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_35_L_byte; + struct + { + __IOM uint8_t IOLH35_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH35_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH35_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH35_L_3 : 2; + uint8_t : 6; + } IOLH_35_L_b; + }; + union + { + __IOM uint32_t IOLH_35_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_35_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_35_H_byte; + struct + { + __IOM uint8_t IOLH35_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IOLH_35_H_b; + }; + union + { + __IOM uint32_t IOLH_36; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_36_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_36_byte; + struct + { + __IOM uint8_t IOLH36_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH36_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH36_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH36_3 : 2; + uint8_t : 6; + } IOLH_36_b; + }; + __IM uint8_t RESERVED25[4]; + union + { + __IOM uint32_t IOLH_37_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_37_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_37_L_byte; + struct + { + __IOM uint8_t IOLH37_L_0 : 2; + uint8_t : 6; + __IOM uint8_t IOLH37_L_1 : 2; + uint8_t : 6; + __IOM uint8_t IOLH37_L_2 : 2; + uint8_t : 6; + __IOM uint8_t IOLH37_L_3 : 2; + uint8_t : 6; + } IOLH_37_L_b; + }; + union + { + __IOM uint32_t IOLH_37_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IOLH_37_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IOLH_37_H_byte; + struct + { + __IOM uint8_t IOLH37_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IOLH_37_H_b; + }; + __IM uint8_t RESERVED26[1608]; + union + { + __IOM uint32_t IEN_01; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_01_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_01_byte; + struct + { + __IOM uint8_t TMS_SWDIO : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IEN_01_b; + }; + __IM uint8_t RESERVED27[4]; + union + { + __IOM uint32_t IEN_02; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_02_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_02_byte; + struct + { + __IOM uint8_t AUDIO_CLK1 : 1; + uint8_t : 7; + __IOM uint8_t AUDIO_CLK2 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } IEN_02_b; + }; + __IM uint8_t RESERVED28[52]; + union + { + __IOM uint32_t IEN_09; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_09_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_09_byte; + struct + { + __IOM uint8_t I3C_SDA : 1; + uint8_t : 7; + __IOM uint8_t I3C_SCL : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } IEN_09_b; + }; + __IM uint8_t RESERVED29[52]; + union + { + __IOM uint32_t IEN_10; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_10_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_10_byte; + struct + { + uint8_t : 8; + __IOM uint8_t SD0_CMD : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } IEN_10_b; + }; + __IM uint8_t RESERVED30[4]; + union + { + __IOM uint32_t IEN_11_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_11_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_11_L_byte; + struct + { + __IOM uint8_t SD0_DATA0 : 1; + uint8_t : 7; + __IOM uint8_t SD0_DATA1 : 1; + uint8_t : 7; + __IOM uint8_t SD0_DATA2 : 1; + uint8_t : 7; + __IOM uint8_t SD0_DATA3 : 1; + uint8_t : 7; + } IEN_11_L_b; + }; + union + { + __IOM uint32_t IEN_11_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_11_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_11_H_byte; + struct + { + __IOM uint8_t SD0_DATA4 : 1; + uint8_t : 7; + __IOM uint8_t SD0_DATA5 : 1; + uint8_t : 7; + __IOM uint8_t SD0_DATA6 : 1; + uint8_t : 7; + __IOM uint8_t SD0_DATA7 : 1; + uint8_t : 7; + } IEN_11_H_b; + }; + union + { + __IOM uint32_t IEN_12; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_12_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_12_byte; + struct + { + uint8_t : 8; + __IOM uint8_t SD1_CMD : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } IEN_12_b; + }; + __IM uint8_t RESERVED31[4]; + union + { + __IOM uint32_t IEN_13; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_13_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_13_byte; + struct + { + __IOM uint8_t SD1_DATA0 : 1; + uint8_t : 7; + __IOM uint8_t SD1_DATA1 : 1; + uint8_t : 7; + __IOM uint8_t SD1_DATA2 : 1; + uint8_t : 7; + __IOM uint8_t SD1_DATA3 : 1; + uint8_t : 7; + } IEN_13_b; + }; + __IM uint8_t RESERVED32[124]; + union + { + __IOM uint32_t IEN_23; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_23_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_23_byte; + struct + { + uint8_t : 8; + __IOM uint8_t P11_1 : 1; + uint8_t : 7; + __IOM uint8_t P11_2 : 1; + uint8_t : 7; + __IOM uint8_t P11_3 : 1; + uint8_t : 7; + } IEN_23_b; + }; + __IM uint8_t RESERVED33[4]; + union + { + __IOM uint32_t IEN_24; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_24_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_24_byte; + struct + { + __IOM uint8_t P12_0 : 1; + uint8_t : 7; + __IOM uint8_t P12_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } IEN_24_b; + }; + __IM uint8_t RESERVED34[92]; + union + { + __IOM uint32_t IEN_30; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_30_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_30_byte; + struct + { + __IOM uint8_t P1_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IEN_30_b; + }; + __IM uint8_t RESERVED35[28]; + union + { + __IOM uint32_t IEN_34; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } IEN_34_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } IEN_34_byte; + struct + { + __IOM uint8_t P7_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } IEN_34_b; + }; + __IM uint8_t RESERVED36[860]; + union + { + __IOM uint32_t PUPD_20; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_20_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_20_byte; + struct + { + __IOM uint8_t PUPD20_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD20_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD20_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD20_3 : 2; + uint8_t : 6; + } PUPD_20_b; + }; + __IM uint8_t RESERVED37[4]; + union + { + __IOM uint32_t PUPD_21_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_21_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_21_L_byte; + struct + { + __IOM uint8_t PUPD21_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD21_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD21_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD21_L_3 : 2; + uint8_t : 6; + } PUPD_21_L_b; + }; + union + { + __IOM uint32_t PUPD_21_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_21_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_21_H_byte; + struct + { + __IOM uint8_t PUPD21_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PUPD_21_H_b; + }; + union + { + __IOM uint32_t PUPD_22_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_22_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_22_L_byte; + struct + { + __IOM uint8_t PUPD22_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD22_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD22_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD22_L_3 : 2; + uint8_t : 6; + } PUPD_22_L_b; + }; + union + { + __IOM uint32_t PUPD_22_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_22_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_22_H_byte; + struct + { + __IOM uint8_t PUPD22_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PUPD_22_H_b; + }; + union + { + __IOM uint32_t PUPD_23; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_23_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_23_byte; + struct + { + __IOM uint8_t PUPD23_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD23_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD23_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD23_3 : 2; + uint8_t : 6; + } PUPD_23_b; + }; + __IM uint8_t RESERVED38[4]; + union + { + __IOM uint32_t PUPD_24; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_24_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_24_byte; + struct + { + __IOM uint8_t PUPD24_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD24_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } PUPD_24_b; + }; + __IM uint8_t RESERVED39[4]; + union + { + __IOM uint32_t PUPD_25_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_25_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_25_L_byte; + struct + { + __IOM uint8_t PUPD25_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD25_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD25_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD25_L_3 : 2; + uint8_t : 6; + } PUPD_25_L_b; + }; + union + { + __IOM uint32_t PUPD_25_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_25_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_25_H_byte; + struct + { + __IOM uint8_t PUPD25_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PUPD_25_H_b; + }; + union + { + __IOM uint32_t PUPD_26; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_26_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_26_byte; + struct + { + __IOM uint8_t PUPD26_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD26_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD26_2 : 2; + uint8_t : 6; + uint8_t : 8; + } PUPD_26_b; + }; + __IM uint8_t RESERVED40[4]; + union + { + __IOM uint32_t PUPD_27; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_27_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_27_byte; + struct + { + __IOM uint8_t PUPD27_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD27_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD27_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD27_3 : 2; + uint8_t : 6; + } PUPD_27_b; + }; + __IM uint8_t RESERVED41[4]; + union + { + __IOM uint32_t PUPD_28; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_28_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_28_byte; + struct + { + __IOM uint8_t PUPD28_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD28_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } PUPD_28_b; + }; + __IM uint8_t RESERVED42[4]; + union + { + __IOM uint32_t PUPD_29; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_29_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_29_byte; + struct + { + __IOM uint8_t PUPD29_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD29_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD29_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD29_3 : 2; + uint8_t : 6; + } PUPD_29_b; + }; + __IM uint8_t RESERVED43[4]; + union + { + __IOM uint32_t PUPD_2A_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_2A_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_2A_L_byte; + struct + { + __IOM uint8_t PUPD2A_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD2A_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD2A_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD2A_L_3 : 2; + uint8_t : 6; + } PUPD_2A_L_b; + }; + union + { + __IOM uint32_t PUPD_2A_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_2A_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_2A_H_byte; + struct + { + __IOM uint8_t PUPD2A_H_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD2A_H_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } PUPD_2A_H_b; + }; + __IM uint8_t RESERVED44[40]; + union + { + __IOM uint32_t PUPD_30_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_30_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_30_L_byte; + struct + { + __IOM uint8_t PUPD30_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD30_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD30_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD30_L_3 : 2; + uint8_t : 6; + } PUPD_30_L_b; + }; + union + { + __IOM uint32_t PUPD_30_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_30_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_30_H_byte; + struct + { + __IOM uint8_t PUPD30_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PUPD_30_H_b; + }; + union + { + __IOM uint32_t PUPD_31; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_31_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_31_byte; + struct + { + __IOM uint8_t PUPD31_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD31_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD31_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD31_3 : 2; + uint8_t : 6; + } PUPD_31_b; + }; + __IM uint8_t RESERVED45[4]; + union + { + __IOM uint32_t PUPD_32; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_32_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_32_byte; + struct + { + __IOM uint8_t PUPD32_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD32_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD32_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD32_3 : 2; + uint8_t : 6; + } PUPD_32_b; + }; + __IM uint8_t RESERVED46[4]; + union + { + __IOM uint32_t PUPD_33_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_33_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_33_L_byte; + struct + { + __IOM uint8_t PUPD33_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD33_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD33_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD33_L_3 : 2; + uint8_t : 6; + } PUPD_33_L_b; + }; + union + { + __IOM uint32_t PUPD_33_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_33_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_33_H_byte; + struct + { + __IOM uint8_t PUPD33_H_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD33_H_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } PUPD_33_H_b; + }; + union + { + __IOM uint32_t PUPD_34_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_34_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_34_L_byte; + struct + { + __IOM uint8_t PUPD34_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD34_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD34_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD34_L_3 : 2; + uint8_t : 6; + } PUPD_34_L_b; + }; + union + { + __IOM uint32_t PUPD_34_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_34_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_34_H_byte; + struct + { + __IOM uint8_t PUPD34_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PUPD_34_H_b; + }; + union + { + __IOM uint32_t PUPD_35_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_35_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_35_L_byte; + struct + { + __IOM uint8_t PUPD35_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD35_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD35_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD35_L_3 : 2; + uint8_t : 6; + } PUPD_35_L_b; + }; + union + { + __IOM uint32_t PUPD_35_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_35_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_35_H_byte; + struct + { + __IOM uint8_t PUPD35_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PUPD_35_H_b; + }; + union + { + __IOM uint32_t PUPD_36; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_36_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_36_byte; + struct + { + __IOM uint8_t PUPD36_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD36_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD36_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD36_3 : 2; + uint8_t : 6; + } PUPD_36_b; + }; + __IM uint8_t RESERVED47[4]; + union + { + __IOM uint32_t PUPD_37_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_37_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_37_L_byte; + struct + { + __IOM uint8_t PUPD37_L_0 : 2; + uint8_t : 6; + __IOM uint8_t PUPD37_L_1 : 2; + uint8_t : 6; + __IOM uint8_t PUPD37_L_2 : 2; + uint8_t : 6; + __IOM uint8_t PUPD37_L_3 : 2; + uint8_t : 6; + } PUPD_37_L_b; + }; + union + { + __IOM uint32_t PUPD_37_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PUPD_37_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PUPD_37_H_byte; + struct + { + __IOM uint8_t PUPD37_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PUPD_37_H_b; + }; + __IM uint8_t RESERVED48[576]; + union + { + __IOM uint32_t FILONOFF_00; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_00_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_00_byte; + struct + { + __IOM uint8_t FILONOFF00_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_00_b; + }; + __IM uint8_t RESERVED49[252]; + union + { + __IOM uint32_t FILONOFF_20; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_20_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_20_byte; + struct + { + __IOM uint8_t FILONOFF20_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF20_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF20_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF20_3 : 1; + uint8_t : 7; + } FILONOFF_20_b; + }; + __IM uint8_t RESERVED50[4]; + union + { + __IOM uint32_t FILONOFF_21_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_21_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_21_L_byte; + struct + { + __IOM uint8_t FILONOFF21_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF21_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF21_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF21_L_3 : 1; + uint8_t : 7; + } FILONOFF_21_L_b; + }; + union + { + __IOM uint32_t FILONOFF_21_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_21_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_21_H_byte; + struct + { + __IOM uint8_t FILONOFF21_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_21_H_b; + }; + union + { + __IOM uint32_t FILONOFF_22_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_22_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_22_L_byte; + struct + { + __IOM uint8_t FILONOFF22_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF22_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF22_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF22_L_3 : 1; + uint8_t : 7; + } FILONOFF_22_L_b; + }; + union + { + __IOM uint32_t FILONOFF_22_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_22_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_22_H_byte; + struct + { + __IOM uint8_t FILONOFF22_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_22_H_b; + }; + union + { + __IOM uint32_t FILONOFF_23; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_23_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_23_byte; + struct + { + __IOM uint8_t FILONOFF23_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF23_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF23_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF23_3 : 1; + uint8_t : 7; + } FILONOFF_23_b; + }; + __IM uint8_t RESERVED51[4]; + union + { + __IOM uint32_t FILONOFF_24; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_24_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_24_byte; + struct + { + __IOM uint8_t FILONOFF24_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF24_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_24_b; + }; + __IM uint8_t RESERVED52[4]; + union + { + __IOM uint32_t FILONOFF_25_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_25_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_25_L_byte; + struct + { + __IOM uint8_t FILONOFF25_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF25_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF25_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF25_L_3 : 1; + uint8_t : 7; + } FILONOFF_25_L_b; + }; + union + { + __IOM uint32_t FILONOFF_25_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_25_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_25_H_byte; + struct + { + __IOM uint8_t FILONOFF25_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_25_H_b; + }; + union + { + __IOM uint32_t FILONOFF_26; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_26_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_26_byte; + struct + { + __IOM uint8_t FILONOFF26_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF26_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF26_2 : 1; + uint8_t : 7; + uint8_t : 8; + } FILONOFF_26_b; + }; + __IM uint8_t RESERVED53[4]; + union + { + __IOM uint32_t FILONOFF_27; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_27_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_27_byte; + struct + { + __IOM uint8_t FILONOFF27_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF27_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF27_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF27_3 : 1; + uint8_t : 7; + } FILONOFF_27_b; + }; + __IM uint8_t RESERVED54[4]; + union + { + __IOM uint32_t FILONOFF_28; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_28_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_28_byte; + struct + { + __IOM uint8_t FILONOFF28_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF28_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_28_b; + }; + __IM uint8_t RESERVED55[4]; + union + { + __IOM uint32_t FILONOFF_29; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_29_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_29_byte; + struct + { + __IOM uint8_t FILONOFF29_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF29_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF29_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF29_3 : 1; + uint8_t : 7; + } FILONOFF_29_b; + }; + __IM uint8_t RESERVED56[4]; + union + { + __IOM uint32_t FILONOFF_2A_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_2A_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_2A_L_byte; + struct + { + __IOM uint8_t FILONOFF2A_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF2A_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF2A_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF2A_L_3 : 1; + uint8_t : 7; + } FILONOFF_2A_L_b; + }; + union + { + __IOM uint32_t FILONOFF_2A_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_2A_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_2A_H_byte; + struct + { + __IOM uint8_t FILONOFF2A_H_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF2A_H_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_2A_H_b; + }; + __IM uint8_t RESERVED57[40]; + union + { + __IOM uint32_t FILONOFF_30_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_30_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_30_L_byte; + struct + { + __IOM uint8_t FILONOFF30_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF30_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF30_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF30_L_3 : 1; + uint8_t : 7; + } FILONOFF_30_L_b; + }; + union + { + __IOM uint32_t FILONOFF_30_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_30_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_30_H_byte; + struct + { + __IOM uint8_t FILONOFF30_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_30_H_b; + }; + union + { + __IOM uint32_t FILONOFF_31; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_31_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_31_byte; + struct + { + __IOM uint8_t FILONOFF31_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF31_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF31_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF31_3 : 1; + uint8_t : 7; + } FILONOFF_31_b; + }; + __IM uint8_t RESERVED58[4]; + union + { + __IOM uint32_t FILONOFF_32; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_32_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_32_byte; + struct + { + __IOM uint8_t FILONOFF32_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF32_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF32_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF32_3 : 1; + uint8_t : 7; + } FILONOFF_32_b; + }; + __IM uint8_t RESERVED59[4]; + union + { + __IOM uint32_t FILONOFF_33_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_33_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_33_L_byte; + struct + { + __IOM uint8_t FILONOFF33_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF33_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF33_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF33_L_3 : 1; + uint8_t : 7; + } FILONOFF_33_L_b; + }; + union + { + __IOM uint32_t FILONOFF_33_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_33_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_33_H_byte; + struct + { + __IOM uint8_t FILONOFF33_H_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF33_H_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_33_H_b; + }; + union + { + __IOM uint32_t FILONOFF_34_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_34_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_34_L_byte; + struct + { + __IOM uint8_t FILONOFF34_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF34_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF34_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF34_L_3 : 1; + uint8_t : 7; + } FILONOFF_34_L_b; + }; + union + { + __IOM uint32_t FILONOFF_34_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_34_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_34_H_byte; + struct + { + __IOM uint8_t FILONOFF34_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_34_H_b; + }; + union + { + __IOM uint32_t FILONOFF_35_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_35_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_35_L_byte; + struct + { + __IOM uint8_t FILONOFF35_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF35_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF35_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF35_L_3 : 1; + uint8_t : 7; + } FILONOFF_35_L_b; + }; + union + { + __IOM uint32_t FILONOFF_35_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_35_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_35_H_byte; + struct + { + __IOM uint8_t FILONOFF35_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_35_H_b; + }; + union + { + __IOM uint32_t FILONOFF_36; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_36_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_36_byte; + struct + { + __IOM uint8_t FILONOFF36_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF36_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF36_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF36_3 : 1; + uint8_t : 7; + } FILONOFF_36_b; + }; + __IM uint8_t RESERVED60[4]; + union + { + __IOM uint32_t FILONOFF_37_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_37_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_37_L_byte; + struct + { + __IOM uint8_t FILONOFF37_L_0 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF37_L_1 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF37_L_2 : 1; + uint8_t : 7; + __IOM uint8_t FILONOFF37_L_3 : 1; + uint8_t : 7; + } FILONOFF_37_L_b; + }; + union + { + __IOM uint32_t FILONOFF_37_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILONOFF_37_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILONOFF_37_H_byte; + struct + { + __IOM uint8_t FILONOFF37_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILONOFF_37_H_b; + }; + __IM uint8_t RESERVED61[576]; + union + { + __IOM uint32_t FILNUM_00; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_00_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_00_byte; + struct + { + __IOM uint8_t FILNUM00_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILNUM_00_b; + }; + __IM uint8_t RESERVED62[252]; + union + { + __IOM uint32_t FILNUM_20; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_20_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_20_byte; + struct + { + __IOM uint8_t FILNUM20_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM20_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM20_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM20_3 : 2; + uint8_t : 6; + } FILNUM_20_b; + }; + __IM uint8_t RESERVED63[4]; + union + { + __IOM uint32_t FILNUM_21_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_21_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_21_L_byte; + struct + { + __IOM uint8_t FILNUM21_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM21_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM21_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM21_L_3 : 2; + uint8_t : 6; + } FILNUM_21_L_b; + }; + union + { + __IOM uint32_t FILNUM_21_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_21_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_21_H_byte; + struct + { + __IOM uint8_t FILNUM21_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILNUM_21_H_b; + }; + union + { + __IOM uint32_t FILNUM_22_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_22_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_22_L_byte; + struct + { + __IOM uint8_t FILNUM22_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM22_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM22_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM22_L_3 : 2; + uint8_t : 6; + } FILNUM_22_L_b; + }; + union + { + __IOM uint32_t FILNUM_22_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_22_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_22_H_byte; + struct + { + __IOM uint8_t FILNUM22_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILNUM_22_H_b; + }; + union + { + __IOM uint32_t FILNUM_23; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_23_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_23_byte; + struct + { + __IOM uint8_t FILNUM23_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM23_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM23_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM23_3 : 2; + uint8_t : 6; + } FILNUM_23_b; + }; + __IM uint8_t RESERVED64[4]; + union + { + __IOM uint32_t FILNUM_24; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_24_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_24_byte; + struct + { + __IOM uint8_t FILNUM24_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM24_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } FILNUM_24_b; + }; + __IM uint8_t RESERVED65[4]; + union + { + __IOM uint32_t FILNUM_25_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_25_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_25_L_byte; + struct + { + __IOM uint8_t FILNUM25_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM25_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM25_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM25_L_3 : 2; + uint8_t : 6; + } FILNUM_25_L_b; + }; + union + { + __IOM uint32_t FILNUM_25_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_25_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_25_H_byte; + struct + { + __IOM uint8_t FILNUM25_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILNUM_25_H_b; + }; + union + { + __IOM uint32_t FILNUM_26; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_26_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_26_byte; + struct + { + __IOM uint8_t FILNUM26_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM26_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM26_2 : 2; + uint8_t : 6; + uint8_t : 8; + } FILNUM_26_b; + }; + __IM uint8_t RESERVED66[4]; + union + { + __IOM uint32_t FILNUM_27; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_27_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_27_byte; + struct + { + __IOM uint8_t FILNUM27_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM27_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM27_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM27_3 : 2; + uint8_t : 6; + } FILNUM_27_b; + }; + __IM uint8_t RESERVED67[4]; + union + { + __IOM uint32_t FILNUM_28; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_28_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_28_byte; + struct + { + __IOM uint8_t FILNUM28_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM28_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } FILNUM_28_b; + }; + __IM uint8_t RESERVED68[4]; + union + { + __IOM uint32_t FILNUM_29; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_29_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_29_byte; + struct + { + __IOM uint8_t FILNUM29_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM29_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM29_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM29_3 : 2; + uint8_t : 6; + } FILNUM_29_b; + }; + __IM uint8_t RESERVED69[4]; + union + { + __IOM uint32_t FILNUM_2A_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_2A_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_2A_L_byte; + struct + { + __IOM uint8_t FILNUM2A_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM2A_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM2A_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM2A_L_3 : 2; + uint8_t : 6; + } FILNUM_2A_L_b; + }; + union + { + __IOM uint32_t FILNUM_2A_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_2A_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_2A_H_byte; + struct + { + __IOM uint8_t FILNUM2A_H_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM2A_H_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } FILNUM_2A_H_b; + }; + __IM uint8_t RESERVED70[40]; + union + { + __IOM uint32_t FILNUM_30_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_30_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_30_L_byte; + struct + { + __IOM uint8_t FILNUM30_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM30_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM30_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM30_L_3 : 2; + uint8_t : 6; + } FILNUM_30_L_b; + }; + union + { + __IOM uint32_t FILNUM_30_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_30_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_30_H_byte; + struct + { + __IOM uint8_t FILNUM30_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILNUM_30_H_b; + }; + union + { + __IOM uint32_t FILNUM_31; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_31_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_31_byte; + struct + { + __IOM uint8_t FILNUM31_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM31_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM31_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM31_3 : 2; + uint8_t : 6; + } FILNUM_31_b; + }; + __IM uint8_t RESERVED71[4]; + union + { + __IOM uint32_t FILNUM_32; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_32_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_32_byte; + struct + { + __IOM uint8_t FILNUM32_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM32_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM32_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM32_3 : 2; + uint8_t : 6; + } FILNUM_32_b; + }; + __IM uint8_t RESERVED72[4]; + union + { + __IOM uint32_t FILNUM_33_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_33_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_33_L_byte; + struct + { + __IOM uint8_t FILNUM33_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM33_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM33_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM33_L_3 : 2; + uint8_t : 6; + } FILNUM_33_L_b; + }; + union + { + __IOM uint32_t FILNUM_33_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_33_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_33_H_byte; + struct + { + __IOM uint8_t FILNUM33_H_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM33_H_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } FILNUM_33_H_b; + }; + union + { + __IOM uint32_t FILNUM_34_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_34_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_34_L_byte; + struct + { + __IOM uint8_t FILNUM34_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM34_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM34_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM34_L_3 : 2; + uint8_t : 6; + } FILNUM_34_L_b; + }; + union + { + __IOM uint32_t FILNUM_34_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_34_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_34_H_byte; + struct + { + __IOM uint8_t FILNUM34_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILNUM_34_H_b; + }; + union + { + __IOM uint32_t FILNUM_35_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_35_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_35_L_byte; + struct + { + __IOM uint8_t FILNUM35_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM35_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM35_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM35_L_3 : 2; + uint8_t : 6; + } FILNUM_35_L_b; + }; + union + { + __IOM uint32_t FILNUM_35_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_35_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_35_H_byte; + struct + { + __IOM uint8_t FILNUM35_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILNUM_35_H_b; + }; + union + { + __IOM uint32_t FILNUM_36; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_36_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_36_byte; + struct + { + __IOM uint8_t FILNUM36_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM36_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM36_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM36_3 : 2; + uint8_t : 6; + } FILNUM_36_b; + }; + __IM uint8_t RESERVED73[4]; + union + { + __IOM uint32_t FILNUM_37_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_37_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_37_L_byte; + struct + { + __IOM uint8_t FILNUM37_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM37_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM37_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILNUM37_L_3 : 2; + uint8_t : 6; + } FILNUM_37_L_b; + }; + union + { + __IOM uint32_t FILNUM_37_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILNUM_37_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILNUM_37_H_byte; + struct + { + __IOM uint8_t FILNUM37_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILNUM_37_H_b; + }; + __IM uint8_t RESERVED74[576]; + union + { + __IOM uint32_t FILCLKSEL_00; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_00_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_00_byte; + struct + { + __IOM uint8_t FILCLKSEL00_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_00_b; + }; + __IM uint8_t RESERVED75[252]; + union + { + __IOM uint32_t FILCLKSEL_20; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_20_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_20_byte; + struct + { + __IOM uint8_t FILCLKSEL20_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL20_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL20_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL20_3 : 2; + uint8_t : 6; + } FILCLKSEL_20_b; + }; + __IM uint8_t RESERVED76[4]; + union + { + __IOM uint32_t FILCLKSEL_21_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_21_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_21_L_byte; + struct + { + __IOM uint8_t FILCLKSEL21_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL21_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL21_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL21_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_21_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_21_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_21_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_21_H_byte; + struct + { + __IOM uint8_t FILCLKSEL21_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_21_H_b; + }; + union + { + __IOM uint32_t FILCLKSEL_22_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_22_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_22_L_byte; + struct + { + __IOM uint8_t FILCLKSEL22_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL22_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL22_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL22_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_22_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_22_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_22_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_22_H_byte; + struct + { + __IOM uint8_t FILCLKSEL22_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_22_H_b; + }; + union + { + __IOM uint32_t FILCLKSEL_23; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_23_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_23_byte; + struct + { + __IOM uint8_t FILCLKSEL23_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL23_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL23_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL23_3 : 2; + uint8_t : 6; + } FILCLKSEL_23_b; + }; + __IM uint8_t RESERVED77[4]; + union + { + __IOM uint32_t FILCLKSEL_24; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_24_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_24_byte; + struct + { + __IOM uint8_t FILCLKSEL24_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL24_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_24_b; + }; + __IM uint8_t RESERVED78[4]; + union + { + __IOM uint32_t FILCLKSEL_25_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_25_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_25_L_byte; + struct + { + __IOM uint8_t FILCLKSEL25_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL25_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL25_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL25_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_25_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_25_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_25_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_25_H_byte; + struct + { + __IOM uint8_t FILCLKSEL25_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_25_H_b; + }; + union + { + __IOM uint32_t FILCLKSEL_26; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_26_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_26_byte; + struct + { + __IOM uint8_t FILCLKSEL26_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL26_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL26_2 : 2; + uint8_t : 6; + uint8_t : 8; + } FILCLKSEL_26_b; + }; + __IM uint8_t RESERVED79[4]; + union + { + __IOM uint32_t FILCLKSEL_27; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_27_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_27_byte; + struct + { + __IOM uint8_t FILCLKSEL27_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL27_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL27_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL27_3 : 2; + uint8_t : 6; + } FILCLKSEL_27_b; + }; + __IM uint8_t RESERVED80[4]; + union + { + __IOM uint32_t FILCLKSEL_28; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_28_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_28_byte; + struct + { + __IOM uint8_t FILCLKSEL28_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL28_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_28_b; + }; + __IM uint8_t RESERVED81[4]; + union + { + __IOM uint32_t FILCLKSEL_29; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_29_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_29_byte; + struct + { + __IOM uint8_t FILCLKSEL29_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL29_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL29_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL29_3 : 2; + uint8_t : 6; + } FILCLKSEL_29_b; + }; + __IM uint8_t RESERVED82[4]; + union + { + __IOM uint32_t FILCLKSEL_2A_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_2A_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_2A_L_byte; + struct + { + __IOM uint8_t FILCLKSEL2A_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL2A_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL2A_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL2A_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_2A_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_2A_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_2A_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_2A_H_byte; + struct + { + __IOM uint8_t FILCLKSEL2A_H_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL2A_H_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_2A_H_b; + }; + __IM uint8_t RESERVED83[40]; + union + { + __IOM uint32_t FILCLKSEL_30_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_30_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_30_L_byte; + struct + { + __IOM uint8_t FILCLKSEL30_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL30_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL30_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL30_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_30_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_30_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_30_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_30_H_byte; + struct + { + __IOM uint8_t FILCLKSEL30_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_30_H_b; + }; + union + { + __IOM uint32_t FILCLKSEL_31; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_31_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_31_byte; + struct + { + __IOM uint8_t FILCLKSEL31_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL31_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL31_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL31_3 : 2; + uint8_t : 6; + } FILCLKSEL_31_b; + }; + __IM uint8_t RESERVED84[4]; + union + { + __IOM uint32_t FILCLKSEL_32; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_32_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_32_byte; + struct + { + __IOM uint8_t FILCLKSEL32_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL32_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL32_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL32_3 : 2; + uint8_t : 6; + } FILCLKSEL_32_b; + }; + __IM uint8_t RESERVED85[4]; + union + { + __IOM uint32_t FILCLKSEL_33_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_33_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_33_L_byte; + struct + { + __IOM uint8_t FILCLKSEL33_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL33_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL33_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL33_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_33_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_33_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_33_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_33_H_byte; + struct + { + __IOM uint8_t FILCLKSEL33_H_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL33_H_1 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_33_H_b; + }; + union + { + __IOM uint32_t FILCLKSEL_34_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_34_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_34_L_byte; + struct + { + __IOM uint8_t FILCLKSEL34_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL34_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL34_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL34_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_34_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_34_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_34_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_34_H_byte; + struct + { + __IOM uint8_t FILCLKSEL34_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_34_H_b; + }; + union + { + __IOM uint32_t FILCLKSEL_35_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_35_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_35_L_byte; + struct + { + __IOM uint8_t FILCLKSEL35_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL35_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL35_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL35_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_35_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_35_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_35_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_35_H_byte; + struct + { + __IOM uint8_t FILCLKSEL35_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_35_H_b; + }; + union + { + __IOM uint32_t FILCLKSEL_36; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_36_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_36_byte; + struct + { + __IOM uint8_t FILCLKSEL36_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL36_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL36_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL36_3 : 2; + uint8_t : 6; + } FILCLKSEL_36_b; + }; + __IM uint8_t RESERVED86[4]; + union + { + __IOM uint32_t FILCLKSEL_37_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_37_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_37_L_byte; + struct + { + __IOM uint8_t FILCLKSEL37_L_0 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL37_L_1 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL37_L_2 : 2; + uint8_t : 6; + __IOM uint8_t FILCLKSEL37_L_3 : 2; + uint8_t : 6; + } FILCLKSEL_37_L_b; + }; + union + { + __IOM uint32_t FILCLKSEL_37_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } FILCLKSEL_37_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } FILCLKSEL_37_H_byte; + struct + { + __IOM uint8_t FILCLKSEL37_H_0 : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } FILCLKSEL_37_H_b; + }; + __IM uint8_t RESERVED87[832]; + union + { + __IOM uint32_t ISEL_20; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_20_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_20_byte; + struct + { + __IOM uint8_t ISEL20_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL20_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL20_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL20_3 : 1; + uint8_t : 7; + } ISEL_20_b; + }; + __IM uint8_t RESERVED88[4]; + union + { + __IOM uint32_t ISEL_21_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_21_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_21_L_byte; + struct + { + __IOM uint8_t ISEL21_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL21_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL21_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL21_L_3 : 1; + uint8_t : 7; + } ISEL_21_L_b; + }; + union + { + __IOM uint32_t ISEL_21_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_21_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_21_H_byte; + struct + { + __IOM uint8_t ISEL21_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ISEL_21_H_b; + }; + union + { + __IOM uint32_t ISEL_22_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_22_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_22_L_byte; + struct + { + __IOM uint8_t ISEL22_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL22_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL22_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL22_L_3 : 1; + uint8_t : 7; + } ISEL_22_L_b; + }; + union + { + __IOM uint32_t ISEL_22_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_22_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_22_H_byte; + struct + { + __IOM uint8_t ISEL22_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ISEL_22_H_b; + }; + union + { + __IOM uint32_t ISEL_23; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_23_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_23_byte; + struct + { + __IOM uint8_t ISEL23_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL23_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL23_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL23_3 : 1; + uint8_t : 7; + } ISEL_23_b; + }; + __IM uint8_t RESERVED89[4]; + union + { + __IOM uint32_t ISEL_24; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_24_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_24_byte; + struct + { + __IOM uint8_t ISEL24_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL24_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } ISEL_24_b; + }; + __IM uint8_t RESERVED90[4]; + union + { + __IOM uint32_t ISEL_25_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_25_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_25_L_byte; + struct + { + __IOM uint8_t ISEL25_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL25_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL25_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL25_L_3 : 1; + uint8_t : 7; + } ISEL_25_L_b; + }; + union + { + __IOM uint32_t ISEL_25_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_25_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_25_H_byte; + struct + { + __IOM uint8_t ISEL25_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ISEL_25_H_b; + }; + union + { + __IOM uint32_t ISEL_26; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_26_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_26_byte; + struct + { + __IOM uint8_t ISEL26_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL26_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL26_2 : 1; + uint8_t : 7; + uint8_t : 8; + } ISEL_26_b; + }; + __IM uint8_t RESERVED91[4]; + union + { + __IOM uint32_t ISEL_27; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_27_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_27_byte; + struct + { + __IOM uint8_t ISEL27_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL27_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL27_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL27_3 : 1; + uint8_t : 7; + } ISEL_27_b; + }; + __IM uint8_t RESERVED92[4]; + union + { + __IOM uint32_t ISEL_28; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_28_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_28_byte; + struct + { + __IOM uint8_t ISEL28_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL28_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } ISEL_28_b; + }; + __IM uint8_t RESERVED93[4]; + union + { + __IOM uint32_t ISEL_29; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_29_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_29_byte; + struct + { + __IOM uint8_t ISEL29_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL29_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL29_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL29_3 : 1; + uint8_t : 7; + } ISEL_29_b; + }; + __IM uint8_t RESERVED94[4]; + union + { + __IOM uint32_t ISEL_2A_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_2A_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_2A_L_byte; + struct + { + __IOM uint8_t ISEL2A_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL2A_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL2A_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL2A_L_3 : 1; + uint8_t : 7; + } ISEL_2A_L_b; + }; + union + { + __IOM uint32_t ISEL_2A_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_2A_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_2A_H_byte; + struct + { + __IOM uint8_t ISEL2A_H_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL2A_H_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } ISEL_2A_H_b; + }; + __IM uint8_t RESERVED95[40]; + union + { + __IOM uint32_t ISEL_30_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_30_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_30_L_byte; + struct + { + __IOM uint8_t ISEL30_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL30_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL30_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL30_L_3 : 1; + uint8_t : 7; + } ISEL_30_L_b; + }; + union + { + __IOM uint32_t ISEL_30_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_30_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_30_H_byte; + struct + { + __IOM uint8_t ISEL30_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ISEL_30_H_b; + }; + union + { + __IOM uint32_t ISEL_31; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_31_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_31_byte; + struct + { + __IOM uint8_t ISEL31_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL31_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL31_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL31_3 : 1; + uint8_t : 7; + } ISEL_31_b; + }; + __IM uint8_t RESERVED96[4]; + union + { + __IOM uint32_t ISEL_32; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_32_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_32_byte; + struct + { + __IOM uint8_t ISEL32_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL32_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL32_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL32_3 : 1; + uint8_t : 7; + } ISEL_32_b; + }; + __IM uint8_t RESERVED97[4]; + union + { + __IOM uint32_t ISEL_33_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_33_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_33_L_byte; + struct + { + __IOM uint8_t ISEL33_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL33_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL33_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL33_L_3 : 1; + uint8_t : 7; + } ISEL_33_L_b; + }; + union + { + __IOM uint32_t ISEL_33_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_33_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_33_H_byte; + struct + { + __IOM uint8_t ISEL33_H_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL33_H_1 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + } ISEL_33_H_b; + }; + union + { + __IOM uint32_t ISEL_34_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_34_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_34_L_byte; + struct + { + __IOM uint8_t ISEL34_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL34_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL34_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL34_L_3 : 1; + uint8_t : 7; + } ISEL_34_L_b; + }; + union + { + __IOM uint32_t ISEL_34_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_34_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_34_H_byte; + struct + { + __IOM uint8_t ISEL34_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ISEL_34_H_b; + }; + union + { + __IOM uint32_t ISEL_35_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_35_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_35_L_byte; + struct + { + __IOM uint8_t ISEL35_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL35_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL35_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL35_L_3 : 1; + uint8_t : 7; + } ISEL_35_L_b; + }; + union + { + __IOM uint32_t ISEL_35_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_35_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_35_H_byte; + struct + { + __IOM uint8_t ISEL35_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ISEL_35_H_b; + }; + union + { + __IOM uint32_t ISEL_36; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_36_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_36_byte; + struct + { + __IOM uint8_t ISEL36_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL36_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL36_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL36_3 : 1; + uint8_t : 7; + } ISEL_36_b; + }; + __IM uint8_t RESERVED98[4]; + union + { + __IOM uint32_t ISEL_37_L; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_37_L_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_37_L_byte; + struct + { + __IOM uint8_t ISEL37_L_0 : 1; + uint8_t : 7; + __IOM uint8_t ISEL37_L_1 : 1; + uint8_t : 7; + __IOM uint8_t ISEL37_L_2 : 1; + uint8_t : 7; + __IOM uint8_t ISEL37_L_3 : 1; + uint8_t : 7; + } ISEL_37_L_b; + }; + union + { + __IOM uint32_t ISEL_37_H; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ISEL_37_H_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ISEL_37_H_byte; + struct + { + __IOM uint8_t ISEL37_H_0 : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ISEL_37_H_b; + }; + __IM uint8_t RESERVED99[576]; + union + { + __IOM uint32_t PWPR; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } PWPR_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } PWPR_byte; + struct + { + uint8_t : 6; + __IOM uint8_t PFCWE : 1; + __IOM uint8_t BOWI : 1; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } PWPR_b; + }; + union + { + __IOM uint32_t SD_CH0_POC; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } SD_CH0_POC_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } SD_CH0_POC_byte; + struct + { + __IOM uint8_t SD0_POC : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } SD_CH0_POC_b; + }; + union + { + __IOM uint32_t SD_CH1_POC; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } SD_CH1_POC_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } SD_CH1_POC_byte; + struct + { + __IOM uint8_t SD1_POC : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } SD_CH1_POC_b; + }; + union + { + __IOM uint32_t XSPI_POC; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } XSPI_POC_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } XSPI_POC_byte; + struct + { + __IOM uint8_t XSPI_POC : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } XSPI_POC_b; + }; + union + { + __IOM uint32_t ETH0_POC; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ETH0_POC_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ETH0_POC_byte; + struct + { + __IOM uint8_t ETH0_POC : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ETH0_POC_b; + }; + union + { + __IOM uint32_t ETH1_POC; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ETH1_POC_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ETH1_POC_byte; + struct + { + __IOM uint8_t ETH1_POC : 2; + uint8_t : 6; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ETH1_POC_b; + }; + union + { + __IOM uint32_t ETH_MODE; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } ETH_MODE_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } ETH_MODE_byte; + struct + { + __IOM uint8_t OEN0 : 1; + __IOM uint8_t OEN1 : 1; + __IOM uint8_t OEN2 : 1; + __IOM uint8_t OEN3 : 1; + uint8_t : 4; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } ETH_MODE_b; + }; + union + { + __IOM uint32_t I3C_SET; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } I3C_SET_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } I3C_SET_byte; + struct + { + __IOM uint8_t STBN : 1; + uint8_t : 1; + __IOM uint8_t POC : 1; + uint8_t : 5; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } I3C_SET_b; + }; + union + { + __IOM uint32_t SPI_OCTA_RESET; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } SPI_OCTA_RESET_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } SPI_OCTA_RESET_byte; + struct + { + __IOM uint8_t SORST_N : 1; + uint8_t : 7; + uint8_t : 8; + uint8_t : 8; + uint8_t : 8; + } SPI_OCTA_RESET_b; + }; +} R_GPIO_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_GPIO_BASE 0x41030020 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_GPIO ((R_GPIO_Type *) R_GPIO_BASE) + +#endif /* GPIO_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gpt_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gpt_iodefine.h new file mode 100644 index 00000000..5efa72bb --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gpt_iodefine.h @@ -0,0 +1,667 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : gpt_iodefine.h + * Version : 1.00 + * Description : IO define file for gpt. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef GPT_IODEFINE_H +#define GPT_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t GTWP; + struct + { + __IOM uint32_t WP : 1; + uint32_t : 7; + __IOM uint32_t PRKEY : 8; + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; + struct + { + __IOM uint32_t CSTRT0 : 1; + __IOM uint32_t CSTRT1 : 1; + __IOM uint32_t CSTRT2 : 1; + __IOM uint32_t CSTRT3 : 1; + __IOM uint32_t CSTRT4 : 1; + __IOM uint32_t CSTRT5 : 1; + __IOM uint32_t CSTRT6 : 1; + __IOM uint32_t CSTRT7 : 1; + uint32_t : 24; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; + struct + { + __IOM uint32_t CSTOP0 : 1; + __IOM uint32_t CSTOP1 : 1; + __IOM uint32_t CSTOP2 : 1; + __IOM uint32_t CSTOP3 : 1; + __IOM uint32_t CSTOP4 : 1; + __IOM uint32_t CSTOP5 : 1; + __IOM uint32_t CSTOP6 : 1; + __IOM uint32_t CSTOP7 : 1; + uint32_t : 24; + } GTSTP_b; + }; + + union + { + __IOM uint32_t GTCLR; + struct + { + __IOM uint32_t CCLR0 : 1; + __IOM uint32_t CCLR1 : 1; + __IOM uint32_t CCLR2 : 1; + __IOM uint32_t CCLR3 : 1; + __IOM uint32_t CCLR4 : 1; + __IOM uint32_t CCLR5 : 1; + __IOM uint32_t CCLR6 : 1; + __IOM uint32_t CCLR7 : 1; + uint32_t : 24; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; + struct + { + __IOM uint32_t SSGTRGAR : 1; + __IOM uint32_t SSGTRGAF : 1; + __IOM uint32_t SSGTRGBR : 1; + __IOM uint32_t SSGTRGBF : 1; + __IOM uint32_t SSGTRGCR : 1; + __IOM uint32_t SSGTRGCF : 1; + __IOM uint32_t SSGTRGDR : 1; + __IOM uint32_t SSGTRGDF : 1; + __IOM uint32_t SSCARBL : 1; + __IOM uint32_t SSCARBH : 1; + __IOM uint32_t SSCAFBL : 1; + __IOM uint32_t SSCAFBH : 1; + __IOM uint32_t SSCBRAL : 1; + __IOM uint32_t SSCBRAH : 1; + __IOM uint32_t SSCBFAL : 1; + __IOM uint32_t SSCBFAH : 1; + uint32_t : 15; + __IOM uint32_t CSTRT : 1; + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; + struct + { + __IOM uint32_t PSGTRGAR : 1; + __IOM uint32_t PSGTRGAF : 1; + __IOM uint32_t PSGTRGBR : 1; + __IOM uint32_t PSGTRGBF : 1; + __IOM uint32_t PSGTRGCR : 1; + __IOM uint32_t PSGTRGCF : 1; + __IOM uint32_t PSGTRGDR : 1; + __IOM uint32_t PSGTRGDF : 1; + __IOM uint32_t PSCARBL : 1; + __IOM uint32_t PSCARBH : 1; + __IOM uint32_t PSCAFBL : 1; + __IOM uint32_t PSCAFBH : 1; + __IOM uint32_t PSCBRAL : 1; + __IOM uint32_t PSCBRAH : 1; + __IOM uint32_t PSCBFAL : 1; + __IOM uint32_t PSCBFAH : 1; + uint32_t : 15; + __IOM uint32_t CSTOP : 1; + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; + struct + { + __IOM uint32_t CSGTRGAR : 1; + __IOM uint32_t CSGTRGAF : 1; + __IOM uint32_t CSGTRGBR : 1; + __IOM uint32_t CSGTRGBF : 1; + __IOM uint32_t CSGTRGCR : 1; + __IOM uint32_t CSGTRGCF : 1; + __IOM uint32_t CSGTRGDR : 1; + __IOM uint32_t CSGTRGDF : 1; + __IOM uint32_t CSCARBL : 1; + __IOM uint32_t CSCARBH : 1; + __IOM uint32_t CSCAFBL : 1; + __IOM uint32_t CSCAFBH : 1; + __IOM uint32_t CSCBRAL : 1; + __IOM uint32_t CSCBRAH : 1; + __IOM uint32_t CSCBFAL : 1; + __IOM uint32_t CSCBFAH : 1; + uint32_t : 15; + __IOM uint32_t CCLR : 1; + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; + struct + { + __IOM uint32_t USGTRGAR : 1; + __IOM uint32_t USGTRGAF : 1; + __IOM uint32_t USGTRGBR : 1; + __IOM uint32_t USGTRGBF : 1; + __IOM uint32_t USGTRGCR : 1; + __IOM uint32_t USGTRGCF : 1; + __IOM uint32_t USGTRGDR : 1; + __IOM uint32_t USGTRGDF : 1; + __IOM uint32_t USCARBL : 1; + __IOM uint32_t USCARBH : 1; + __IOM uint32_t USCAFBL : 1; + __IOM uint32_t USCAFBH : 1; + __IOM uint32_t USCBRAL : 1; + __IOM uint32_t USCBRAH : 1; + __IOM uint32_t USCBFAL : 1; + __IOM uint32_t USCBFAH : 1; + uint32_t : 16; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; + struct + { + __IOM uint32_t DSGTRGAR : 1; + __IOM uint32_t DSGTRGAF : 1; + __IOM uint32_t DSGTRGBR : 1; + __IOM uint32_t DSGTRGBF : 1; + __IOM uint32_t DSGTRGCR : 1; + __IOM uint32_t DSGTRGCF : 1; + __IOM uint32_t DSGTRGDR : 1; + __IOM uint32_t DSGTRGDF : 1; + __IOM uint32_t DSCARBL : 1; + __IOM uint32_t DSCARBH : 1; + __IOM uint32_t DSCAFBL : 1; + __IOM uint32_t DSCAFBH : 1; + __IOM uint32_t DSCBRAL : 1; + __IOM uint32_t DSCBRAH : 1; + __IOM uint32_t DSCBFAL : 1; + __IOM uint32_t DSCBFAH : 1; + uint32_t : 16; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; + struct + { + __IOM uint32_t ASGTRGAR : 1; + __IOM uint32_t ASGTRGAF : 1; + __IOM uint32_t ASGTRGBR : 1; + __IOM uint32_t ASGTRGBF : 1; + __IOM uint32_t ASGTRGCR : 1; + __IOM uint32_t ASGTRGCF : 1; + __IOM uint32_t ASGTRGDR : 1; + __IOM uint32_t ASGTRGDF : 1; + __IOM uint32_t ASCARBL : 1; + __IOM uint32_t ASCARBH : 1; + __IOM uint32_t ASCAFBL : 1; + __IOM uint32_t ASCAFBH : 1; + __IOM uint32_t ASCBRAL : 1; + __IOM uint32_t ASCBRAH : 1; + __IOM uint32_t ASCBFAL : 1; + __IOM uint32_t ASCBFAH : 1; + uint32_t : 16; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; + struct + { + __IOM uint32_t BSGTRGAR : 1; + __IOM uint32_t BSGTRGAF : 1; + __IOM uint32_t BSGTRGBR : 1; + __IOM uint32_t BSGTRGBF : 1; + __IOM uint32_t BSGTRGCR : 1; + __IOM uint32_t BSGTRGCF : 1; + __IOM uint32_t BSGTRGDR : 1; + __IOM uint32_t BSGTRGDF : 1; + __IOM uint32_t BSCARBL : 1; + __IOM uint32_t BSCARBH : 1; + __IOM uint32_t BSCAFBL : 1; + __IOM uint32_t BSCAFBH : 1; + __IOM uint32_t BSCBRAL : 1; + __IOM uint32_t BSCBRAH : 1; + __IOM uint32_t BSCBFAL : 1; + __IOM uint32_t BSCBFAH : 1; + uint32_t : 16; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; + struct + { + __IOM uint32_t CST : 1; + uint32_t : 15; + __IOM uint32_t MD : 3; + uint32_t : 5; + __IOM uint32_t TPCS : 3; + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; + struct + { + __IOM uint32_t UD : 1; + __IOM uint32_t UDF : 1; + uint32_t : 14; + __IOM uint32_t OADTY : 2; + __IOM uint32_t OADTYF : 1; + __IOM uint32_t OADTYR : 1; + uint32_t : 4; + __IOM uint32_t OBDTY : 2; + __IOM uint32_t OBDTYF : 1; + __IOM uint32_t OBDTYR : 1; + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; + struct + { + __IOM uint32_t GTIOA : 5; + uint32_t : 1; + __IOM uint32_t OADFLT : 1; + __IOM uint32_t OAHLD : 1; + __IOM uint32_t OAE : 1; + __IOM uint32_t OADF : 2; + uint32_t : 2; + __IOM uint32_t NFAEN : 1; + __IOM uint32_t NFCSA : 2; + __IOM uint32_t GTIOB : 5; + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; + __IOM uint32_t OBHLD : 1; + __IOM uint32_t OBE : 1; + __IOM uint32_t OBDF : 2; + uint32_t : 2; + __IOM uint32_t NFBEN : 1; + __IOM uint32_t NFCSB : 2; + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; + struct + { + __IOM uint32_t GTINTA : 1; + __IOM uint32_t GTINTB : 1; + __IOM uint32_t GTINTC : 1; + __IOM uint32_t GTINTD : 1; + __IOM uint32_t GTINTE : 1; + __IOM uint32_t GTINTF : 1; + __IOM uint32_t GTINTPR : 2; + uint32_t : 8; + __IOM uint32_t ADTRAUEN : 1; + __IOM uint32_t ADTRADEN : 1; + __IOM uint32_t ADTRBUEN : 1; + __IOM uint32_t ADTRBDEN : 1; + uint32_t : 4; + __IOM uint32_t GRP : 2; + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; + __IOM uint32_t GRPABH : 1; + __IOM uint32_t GRPABL : 1; + uint32_t : 1; + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; + struct + { + __IOM uint32_t TCFA : 1; + __IOM uint32_t TCFB : 1; + __IOM uint32_t TCFC : 1; + __IOM uint32_t TCFD : 1; + __IOM uint32_t TCFE : 1; + __IOM uint32_t TCFF : 1; + __IOM uint32_t TCFPO : 1; + __IOM uint32_t TCFPU : 1; + __IM uint32_t ITCNT : 3; + uint32_t : 4; + __IM uint32_t TUCF : 1; + __IOM uint32_t ADTRAUF : 1; + __IOM uint32_t ADTRADF : 1; + __IOM uint32_t ADTRBUF : 1; + __IOM uint32_t ADTRBDF : 1; + uint32_t : 4; + __IM uint32_t ODF : 1; + uint32_t : 3; + __IM uint32_t DTEF : 1; + __IM uint32_t OABHF : 1; + __IM uint32_t OABLF : 1; + uint32_t : 1; + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; + struct + { + __IOM uint32_t BD : 4; + uint32_t : 12; + __IOM uint32_t CCRA : 2; + __IOM uint32_t CCRB : 2; + __IOM uint32_t PR : 2; + __IOM uint32_t CCRSWT : 1; + uint32_t : 1; + __IOM uint32_t ADTTA : 2; + __IOM uint32_t ADTDA : 1; + uint32_t : 1; + __IOM uint32_t ADTTB : 2; + __IOM uint32_t ADTDB : 1; + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; + struct + { + __IOM uint32_t ITLA : 1; + __IOM uint32_t ITLB : 1; + __IOM uint32_t ITLC : 1; + __IOM uint32_t ITLD : 1; + __IOM uint32_t ITLE : 1; + __IOM uint32_t ITLF : 1; + __IOM uint32_t IVTC : 2; + __IOM uint32_t IVTT : 3; + uint32_t : 1; + __IOM uint32_t ADTAL : 1; + uint32_t : 1; + __IOM uint32_t ADTBL : 1; + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; + struct + { + __IOM uint32_t GTCNT : 32; + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCRA; + struct + { + __IOM uint32_t GTCCRA : 32; + } GTCCRA_b; + }; + + union + { + __IOM uint32_t GTCCRB; + struct + { + __IOM uint32_t GTCCRB : 32; + } GTCCRB_b; + }; + + union + { + __IOM uint32_t GTCCRC; + struct + { + __IOM uint32_t GTCCRC : 32; + } GTCCRC_b; + }; + + union + { + __IOM uint32_t GTCCRE; + struct + { + __IOM uint32_t GTCCRE : 32; + } GTCCRE_b; + }; + + union + { + __IOM uint32_t GTCCRD; + struct + { + __IOM uint32_t GTCCRD : 32; + } GTCCRD_b; + }; + + union + { + __IOM uint32_t GTCCRF; + struct + { + __IOM uint32_t GTCCRF : 32; + } GTCCRF_b; + }; + + union + { + __IOM uint32_t GTPR; + struct + { + __IOM uint32_t GTPR : 32; + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; + struct + { + __IOM uint32_t GTPBR : 32; + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; + struct + { + __IOM uint32_t GTPDBR : 32; + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; + struct + { + __IOM uint32_t GTADTRA : 32; + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; + struct + { + __IOM uint32_t GTADTBRA : 32; + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; + struct + { + __IOM uint32_t GTADTDBRA : 32; + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; + struct + { + __IOM uint32_t GTADTRB : 32; + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; + struct + { + __IOM uint32_t GTADTBRB : 32; + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; + struct + { + __IOM uint32_t GTADTDBRB : 32; + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; + struct + { + __IOM uint32_t TDE : 1; + uint32_t : 3; + __IOM uint32_t TDBUE : 1; + __IOM uint32_t TDBDE : 1; + uint32_t : 2; + __IOM uint32_t TDFER : 1; + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; + struct + { + __IOM uint32_t GTDVU : 32; + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; + struct + { + __IOM uint32_t GTDVD : 32; + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; + struct + { + __IOM uint32_t GTDBU : 32; + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; + struct + { + __IOM uint32_t GTDBD : 32; + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; + struct + { + __IM uint32_t SOS : 2; + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; + struct + { + __IOM uint32_t SOTR : 1; + uint32_t : 31; + } GTSOTR_b; + }; +} R_GPT0_Type; + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Address Map ====== */ +/* ================================================================================================================= */ + +#define R_GPT0_BASE 0x40048000 +#define R_GPT1_BASE 0x40048100 +#define R_GPT2_BASE 0x40048200 +#define R_GPT3_BASE 0x40048300 +#define R_GPT4_BASE 0x40048400 +#define R_GPT5_BASE 0x40048500 +#define R_GPT6_BASE 0x40048600 +#define R_GPT7_BASE 0x40048700 + +/* ================================================================================================================= */ +/* ================ Peripheral declaration ====== */ +/* ================================================================================================================= */ + +#define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) +#define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) +#define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) +#define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) +#define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) +#define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) +#define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) +#define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + +#endif /* GPT_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gtm_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gtm_iodefine.h new file mode 100644 index 00000000..fcd9d635 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/gtm_iodefine.h @@ -0,0 +1,116 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : gtm_iodefine.h + * Version : 1.00 + * Description : IO define file for gtm. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef GTM_IODEFINE_H +#define GTM_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t OSTMnCMP; + struct + { + __IOM uint32_t OSTMnCMP : 32; + } OSTMnCMP_b; + }; + + union + { + __IM uint32_t OSTMnCNT; + struct + { + __IM uint32_t OSTMnCNT : 32; + } OSTMnCNT_b; + }; + + __IM uint8_t RESERVED[8]; + union + { + __IM uint8_t OSTMnTE; + struct + { + __IM uint8_t OSTMnTE : 1; + uint8_t : 7; + } OSTMnTE_b; + }; + + __IM uint8_t RESERVED1[3]; + union + { + __IOM uint8_t OSTMnTS; + struct + { + __OM uint8_t OSTMnTS : 1; + uint8_t : 7; + } OSTMnTS_b; + }; + + __IM uint8_t RESERVED2[3]; + union + { + __IOM uint8_t OSTMnTT; + struct + { + __OM uint8_t OSTMnTT : 1; + uint8_t : 7; + } OSTMnTT_b; + }; + + __IM uint8_t RESERVED3[7]; + union + { + __IOM uint8_t OSTMnCTL; + struct + { + __IOM uint8_t OSTMnMD0 : 1; + __IOM uint8_t OSTMnMD1 : 1; + uint8_t : 6; + } OSTMnCTL_b; + }; +} R_GTM0_Type; + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Address Map ====== */ +/* ================================================================================================================= */ + +#define R_GTM0_BASE 0x42801000 +#define R_GTM1_BASE 0x42801400 +#define R_GTM2_BASE 0x42801800 +#define R_GTM3_BASE 0x42801C00 +#define R_GTM4_BASE 0x42802000 +#define R_GTM5_BASE 0x42802400 +#define R_GTM6_BASE 0x42802800 +#define R_GTM7_BASE 0x42802C00 + +/* ================================================================================================================= */ +/* ================ Peripheral declaration ====== */ +/* ================================================================================================================= */ + +#define R_GTM0 ((R_GTM0_Type *) R_GTM0_BASE) +#define R_GTM1 ((R_GTM0_Type *) R_GTM1_BASE) +#define R_GTM2 ((R_GTM0_Type *) R_GTM2_BASE) +#define R_GTM3 ((R_GTM0_Type *) R_GTM3_BASE) +#define R_GTM4 ((R_GTM0_Type *) R_GTM4_BASE) +#define R_GTM5 ((R_GTM0_Type *) R_GTM5_BASE) +#define R_GTM6 ((R_GTM0_Type *) R_GTM6_BASE) +#define R_GTM7 ((R_GTM0_Type *) R_GTM7_BASE) + +#endif /* GTM_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/intc_im33_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/intc_im33_iodefine.h new file mode 100644 index 00000000..9653dd50 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/intc_im33_iodefine.h @@ -0,0 +1,570 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : intc_im33_iodefine.h + * Version : 1.00 + * Description : IO define file for intc_im33. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef INTC_IM33_IODEFINE_H +#define INTC_IM33_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t NSCR; + struct + { + __IOM uint32_t NSTAT : 1; + uint32_t : 15; + __IM uint32_t NSMON : 1; + uint32_t : 15; + } NSCR_b; + }; + union + { + __IOM uint32_t NITSR; + struct + { + __IOM uint32_t NTSEL : 1; + uint32_t : 31; + } NITSR_b; + }; + __IM uint8_t RESERVED[8]; + union + { + __IOM uint32_t ISCR; + struct + { + __IOM uint32_t ISTAT0 : 1; + __IOM uint32_t ISTAT1 : 1; + __IOM uint32_t ISTAT2 : 1; + __IOM uint32_t ISTAT3 : 1; + __IOM uint32_t ISTAT4 : 1; + __IOM uint32_t ISTAT5 : 1; + __IOM uint32_t ISTAT6 : 1; + __IOM uint32_t ISTAT7 : 1; + uint32_t : 24; + } ISCR_b; + }; + union + { + __IOM uint32_t IITSR; + struct + { + __IOM uint32_t IITSEL0 : 2; + __IOM uint32_t IITSEL1 : 2; + __IOM uint32_t IITSEL2 : 2; + __IOM uint32_t IITSEL3 : 2; + __IOM uint32_t IITSEL4 : 2; + __IOM uint32_t IITSEL5 : 2; + __IOM uint32_t IITSEL6 : 2; + __IOM uint32_t IITSEL7 : 2; + uint32_t : 16; + } IITSR_b; + }; + __IM uint8_t RESERVED1[8]; + union + { + __IOM uint32_t TSCR; + struct + { + __IOM uint32_t TSTAT0 : 1; + __IOM uint32_t TSTAT1 : 1; + __IOM uint32_t TSTAT2 : 1; + __IOM uint32_t TSTAT3 : 1; + __IOM uint32_t TSTAT4 : 1; + __IOM uint32_t TSTAT5 : 1; + __IOM uint32_t TSTAT6 : 1; + __IOM uint32_t TSTAT7 : 1; + __IOM uint32_t TSTAT8 : 1; + __IOM uint32_t TSTAT9 : 1; + __IOM uint32_t TSTAT10 : 1; + __IOM uint32_t TSTAT11 : 1; + __IOM uint32_t TSTAT12 : 1; + __IOM uint32_t TSTAT13 : 1; + __IOM uint32_t TSTAT14 : 1; + __IOM uint32_t TSTAT15 : 1; + __IOM uint32_t TSTAT16 : 1; + __IOM uint32_t TSTAT17 : 1; + __IOM uint32_t TSTAT18 : 1; + __IOM uint32_t TSTAT19 : 1; + __IOM uint32_t TSTAT20 : 1; + __IOM uint32_t TSTAT21 : 1; + __IOM uint32_t TSTAT22 : 1; + __IOM uint32_t TSTAT23 : 1; + __IOM uint32_t TSTAT24 : 1; + __IOM uint32_t TSTAT25 : 1; + __IOM uint32_t TSTAT26 : 1; + __IOM uint32_t TSTAT27 : 1; + __IOM uint32_t TSTAT28 : 1; + __IOM uint32_t TSTAT29 : 1; + __IOM uint32_t TSTAT30 : 1; + __IOM uint32_t TSTAT31 : 1; + } TSCR_b; + }; + union + { + __IOM uint32_t TITSR0; + struct + { + __IOM uint32_t TITSEL0 : 2; + __IOM uint32_t TITSEL1 : 2; + __IOM uint32_t TITSEL2 : 2; + __IOM uint32_t TITSEL3 : 2; + __IOM uint32_t TITSEL4 : 2; + __IOM uint32_t TITSEL5 : 2; + __IOM uint32_t TITSEL6 : 2; + __IOM uint32_t TITSEL7 : 2; + __IOM uint32_t TITSEL8 : 2; + __IOM uint32_t TITSEL9 : 2; + __IOM uint32_t TITSEL10 : 2; + __IOM uint32_t TITSEL11 : 2; + __IOM uint32_t TITSEL12 : 2; + __IOM uint32_t TITSEL13 : 2; + __IOM uint32_t TITSEL14 : 2; + __IOM uint32_t TITSEL15 : 2; + } TITSR0_b; + }; + union + { + __IOM uint32_t TITSR1; + struct + { + __IOM uint32_t TITSEL16 : 2; + __IOM uint32_t TITSEL17 : 2; + __IOM uint32_t TITSEL18 : 2; + __IOM uint32_t TITSEL19 : 2; + __IOM uint32_t TITSEL20 : 2; + __IOM uint32_t TITSEL21 : 2; + __IOM uint32_t TITSEL22 : 2; + __IOM uint32_t TITSEL23 : 2; + __IOM uint32_t TITSEL24 : 2; + __IOM uint32_t TITSEL25 : 2; + __IOM uint32_t TITSEL26 : 2; + __IOM uint32_t TITSEL27 : 2; + __IOM uint32_t TITSEL28 : 2; + __IOM uint32_t TITSEL29 : 2; + __IOM uint32_t TITSEL30 : 2; + __IOM uint32_t TITSEL31 : 2; + } TITSR1_b; + }; + __IM uint8_t RESERVED2[4]; + union + { + __IOM uint32_t TSSR0; + struct + { + __IOM uint32_t TSSEL0 : 7; + __IOM uint32_t TIEN0 : 1; + __IOM uint32_t TSSEL1 : 7; + __IOM uint32_t TIEN1 : 1; + __IOM uint32_t TSSEL2 : 7; + __IOM uint32_t TIEN2 : 1; + __IOM uint32_t TSSEL3 : 7; + __IOM uint32_t TIEN3 : 1; + } TSSR0_b; + }; + union + { + __IOM uint32_t TSSR1; + struct + { + __IOM uint32_t TSSEL4 : 7; + __IOM uint32_t TIEN4 : 1; + __IOM uint32_t TSSEL5 : 7; + __IOM uint32_t TIEN5 : 1; + __IOM uint32_t TSSEL6 : 7; + __IOM uint32_t TIEN6 : 1; + __IOM uint32_t TSSEL7 : 7; + __IOM uint32_t TIEN7 : 1; + } TSSR1_b; + }; + union + { + __IOM uint32_t TSSR2; + struct + { + __IOM uint32_t TSSEL8 : 7; + __IOM uint32_t TIEN8 : 1; + __IOM uint32_t TSSEL9 : 7; + __IOM uint32_t TIEN9 : 1; + __IOM uint32_t TSSEL10 : 7; + __IOM uint32_t TIEN10 : 1; + __IOM uint32_t TSSEL11 : 7; + __IOM uint32_t TIEN11 : 1; + } TSSR2_b; + }; + union + { + __IOM uint32_t TSSR3; + struct + { + __IOM uint32_t TSSEL12 : 7; + __IOM uint32_t TIEN12 : 1; + __IOM uint32_t TSSEL13 : 7; + __IOM uint32_t TIEN13 : 1; + __IOM uint32_t TSSEL14 : 7; + __IOM uint32_t TIEN14 : 1; + __IOM uint32_t TSSEL15 : 7; + __IOM uint32_t TIEN15 : 1; + } TSSR3_b; + }; + union + { + __IOM uint32_t TSSR4; + struct + { + __IOM uint32_t TSSEL16 : 7; + __IOM uint32_t TIEN16 : 1; + __IOM uint32_t TSSEL17 : 7; + __IOM uint32_t TIEN17 : 1; + __IOM uint32_t TSSEL18 : 7; + __IOM uint32_t TIEN18 : 1; + __IOM uint32_t TSSEL19 : 7; + __IOM uint32_t TIEN19 : 1; + } TSSR4_b; + }; + union + { + __IOM uint32_t TSSR5; + struct + { + __IOM uint32_t TSSEL20 : 7; + __IOM uint32_t TIEN20 : 1; + __IOM uint32_t TSSEL21 : 7; + __IOM uint32_t TIEN21 : 1; + __IOM uint32_t TSSEL22 : 7; + __IOM uint32_t TIEN22 : 1; + __IOM uint32_t TSSEL23 : 7; + __IOM uint32_t TIEN23 : 1; + } TSSR5_b; + }; + union + { + __IOM uint32_t TSSR6; + struct + { + __IOM uint32_t TSSEL24 : 7; + __IOM uint32_t TIEN24 : 1; + __IOM uint32_t TSSEL25 : 7; + __IOM uint32_t TIEN25 : 1; + __IOM uint32_t TSSEL26 : 7; + __IOM uint32_t TIEN26 : 1; + __IOM uint32_t TSSEL27 : 7; + __IOM uint32_t TIEN27 : 1; + } TSSR6_b; + }; + union + { + __IOM uint32_t TSSR7; + struct + { + __IOM uint32_t TSSEL28 : 7; + __IOM uint32_t TIEN28 : 1; + __IOM uint32_t TSSEL29 : 7; + __IOM uint32_t TIEN29 : 1; + __IOM uint32_t TSSEL30 : 7; + __IOM uint32_t TIEN30 : 1; + __IOM uint32_t TSSEL31 : 7; + __IOM uint32_t TIEN31 : 1; + } TSSR7_b; + }; + union + { + __IOM uint32_t BEISR0; + struct + { + __IOM uint32_t BESTAT0 : 1; + __IOM uint32_t BESTAT1 : 1; + __IOM uint32_t BESTAT2 : 1; + __IOM uint32_t BESTAT3 : 1; + __IOM uint32_t BESTAT4 : 1; + __IOM uint32_t BESTAT5 : 1; + __IOM uint32_t BESTAT6 : 1; + __IOM uint32_t BESTAT7 : 1; + __IOM uint32_t BESTAT8 : 1; + __IOM uint32_t BESTAT9 : 1; + __IOM uint32_t BESTAT10 : 1; + __IOM uint32_t BESTAT11 : 1; + __IOM uint32_t BESTAT12 : 1; + __IOM uint32_t BESTAT13 : 1; + __IOM uint32_t BESTAT14 : 1; + __IOM uint32_t BESTAT15 : 1; + __IOM uint32_t BESTAT16 : 1; + __IOM uint32_t BESTAT17 : 1; + __IOM uint32_t BESTAT18 : 1; + __IOM uint32_t BESTAT19 : 1; + __IOM uint32_t BESTAT20 : 1; + __IOM uint32_t BESTAT21 : 1; + __IOM uint32_t BESTAT22 : 1; + __IOM uint32_t BESTAT23 : 1; + __IOM uint32_t BESTAT24 : 1; + __IOM uint32_t BESTAT25 : 1; + __IOM uint32_t BESTAT26 : 1; + __IOM uint32_t BESTAT27 : 1; + __IOM uint32_t BESTAT28 : 1; + __IOM uint32_t BESTAT29 : 1; + __IOM uint32_t BESTAT30 : 1; + __IOM uint32_t BESTAT31 : 1; + } BEISR0_b; + }; + union + { + __IOM uint32_t BEISR1; + struct + { + __IOM uint32_t BESTAT32 : 1; + __IOM uint32_t BESTAT33 : 1; + __IOM uint32_t BESTAT34 : 1; + __IOM uint32_t BESTAT35 : 1; + __IOM uint32_t BESTAT36 : 1; + __IOM uint32_t BESTAT37 : 1; + __IOM uint32_t BESTAT38 : 1; + __IOM uint32_t BESTAT39 : 1; + __IOM uint32_t BESTAT40 : 1; + __IOM uint32_t BESTAT41 : 1; + __IOM uint32_t BESTAT42 : 1; + __IOM uint32_t BESTAT43 : 1; + __IOM uint32_t BESTAT44 : 1; + __IOM uint32_t BESTAT45 : 1; + __IOM uint32_t BESTAT46 : 1; + uint32_t : 17; + } BEISR1_b; + }; + __IM uint8_t RESERVED3[8]; + union + { + __IOM uint32_t EREISR0; + struct + { + __IOM uint32_t A01ESTAT0 : 1; + __IOM uint32_t A01ESTAT1 : 1; + __IOM uint32_t A01ESTAT2 : 1; + __IOM uint32_t A01ESTAT3 : 1; + __IOM uint32_t A01ESTAT4 : 1; + __IOM uint32_t A01ESTAT5 : 1; + __IOM uint32_t A01ESTAT6 : 1; + __IOM uint32_t A01ESTAT7 : 1; + __IOM uint32_t A11ESTAT0 : 1; + __IOM uint32_t A11ESTAT1 : 1; + __IOM uint32_t A11ESTAT2 : 1; + __IOM uint32_t A11ESTAT3 : 1; + __IOM uint32_t A11ESTAT4 : 1; + __IOM uint32_t A11ESTAT5 : 1; + __IOM uint32_t A11ESTAT6 : 1; + __IOM uint32_t A11ESTAT7 : 1; + uint32_t : 16; + } EREISR0_b; + }; + union + { + __IOM uint32_t EREISR1; + struct + { + __IOM uint32_t M01ESTAT0 : 1; + __IOM uint32_t M01ESTAT1 : 1; + __IOM uint32_t M01ESTAT2 : 1; + __IOM uint32_t M01ESTAT3 : 1; + __IOM uint32_t M01ESTAT4 : 1; + __IOM uint32_t M01ESTAT5 : 1; + __IOM uint32_t M01ESTAT6 : 1; + __IOM uint32_t M01ESTAT7 : 1; + __IOM uint32_t M11ESTAT0 : 1; + __IOM uint32_t M11ESTAT1 : 1; + __IOM uint32_t M11ESTAT2 : 1; + __IOM uint32_t M11ESTAT3 : 1; + __IOM uint32_t M11ESTAT4 : 1; + __IOM uint32_t M11ESTAT5 : 1; + __IOM uint32_t M11ESTAT6 : 1; + __IOM uint32_t M11ESTAT7 : 1; + uint32_t : 16; + } EREISR1_b; + }; + union + { + __IOM uint32_t EREISR2; + struct + { + __IOM uint32_t A02ESTAT0 : 1; + __IOM uint32_t A02ESTAT1 : 1; + __IOM uint32_t A02ESTAT2 : 1; + __IOM uint32_t A02ESTAT3 : 1; + __IOM uint32_t A02ESTAT4 : 1; + __IOM uint32_t A02ESTAT5 : 1; + __IOM uint32_t A02ESTAT6 : 1; + __IOM uint32_t A02ESTAT7 : 1; + __IOM uint32_t A12ESTAT0 : 1; + __IOM uint32_t A12ESTAT1 : 1; + __IOM uint32_t A12ESTAT2 : 1; + __IOM uint32_t A12ESTAT3 : 1; + __IOM uint32_t A12ESTAT4 : 1; + __IOM uint32_t A12ESTAT5 : 1; + __IOM uint32_t A12ESTAT6 : 1; + __IOM uint32_t A12ESTAT7 : 1; + uint32_t : 16; + } EREISR2_b; + }; + union + { + __IOM uint32_t EREISR3; + struct + { + __IOM uint32_t M02ESTAT0 : 1; + __IOM uint32_t M02ESTAT1 : 1; + __IOM uint32_t M02ESTAT2 : 1; + __IOM uint32_t M02ESTAT3 : 1; + __IOM uint32_t M02ESTAT4 : 1; + __IOM uint32_t M02ESTAT5 : 1; + __IOM uint32_t M02ESTAT6 : 1; + __IOM uint32_t M02ESTAT7 : 1; + __IOM uint32_t M12ESTAT0 : 1; + __IOM uint32_t M12ESTAT1 : 1; + __IOM uint32_t M12ESTAT2 : 1; + __IOM uint32_t M12ESTAT3 : 1; + __IOM uint32_t M12ESTAT4 : 1; + __IOM uint32_t M12ESTAT5 : 1; + __IOM uint32_t M12ESTAT6 : 1; + __IOM uint32_t M12ESTAT7 : 1; + uint32_t : 16; + } EREISR3_b; + }; + union + { + __IOM uint32_t EREISR4; + struct + { + __IOM uint32_t A0OFSTAT0 : 1; + __IOM uint32_t A0OFSTAT1 : 1; + __IOM uint32_t A0OFSTAT2 : 1; + __IOM uint32_t A0OFSTAT3 : 1; + __IOM uint32_t A0OFSTAT4 : 1; + __IOM uint32_t A0OFSTAT5 : 1; + __IOM uint32_t A0OFSTAT6 : 1; + __IOM uint32_t A0OFSTAT7 : 1; + __IOM uint32_t A1OFSTAT0 : 1; + __IOM uint32_t A1OFSTAT1 : 1; + __IOM uint32_t A1OFSTAT2 : 1; + __IOM uint32_t A1OFSTAT3 : 1; + __IOM uint32_t A1OFSTAT4 : 1; + __IOM uint32_t A1OFSTAT5 : 1; + __IOM uint32_t A1OFSTAT6 : 1; + __IOM uint32_t A1OFSTAT7 : 1; + uint32_t : 16; + } EREISR4_b; + }; + union + { + __IOM uint32_t EREISR5; + struct + { + __IOM uint32_t M0OFSTAT0 : 1; + __IOM uint32_t M0OFSTAT1 : 1; + __IOM uint32_t M0OFSTAT2 : 1; + __IOM uint32_t M0OFSTAT3 : 1; + __IOM uint32_t M0OFSTAT4 : 1; + __IOM uint32_t M0OFSTAT5 : 1; + __IOM uint32_t M0OFSTAT6 : 1; + __IOM uint32_t M0OFSTAT7 : 1; + __IOM uint32_t M1OFSTAT0 : 1; + __IOM uint32_t M1OFSTAT1 : 1; + __IOM uint32_t M1OFSTAT2 : 1; + __IOM uint32_t M1OFSTAT3 : 1; + __IOM uint32_t M1OFSTAT4 : 1; + __IOM uint32_t M1OFSTAT5 : 1; + __IOM uint32_t M1OFSTAT6 : 1; + __IOM uint32_t M1OFSTAT7 : 1; + uint32_t : 16; + } EREISR5_b; + }; + __IM uint8_t RESERVED4[8]; + union + { + __IOM uint32_t INTPMSEL0; + struct + { + __IOM uint32_t PMINTSEL0 : 1; + __IOM uint32_t PMINTSEL1 : 1; + __IOM uint32_t PMINTSEL2 : 1; + __IOM uint32_t PMINTSEL3 : 1; + __IOM uint32_t PMINTSEL4 : 1; + __IOM uint32_t PMINTSEL5 : 1; + __IOM uint32_t PMINTSEL6 : 1; + __IOM uint32_t PMINTSEL7 : 1; + __IOM uint32_t PMINTSEL8 : 1; + __IOM uint32_t PMINTSEL9 : 1; + __IOM uint32_t PMINTSEL10 : 1; + __IOM uint32_t PMINTSEL11 : 1; + __IOM uint32_t PMINTSEL12 : 1; + __IOM uint32_t PMINTSEL13 : 1; + __IOM uint32_t PMINTSEL14 : 1; + __IOM uint32_t PMINTSEL15 : 1; + __IOM uint32_t PMINTSEL16 : 1; + __IOM uint32_t PMINTSEL17 : 1; + __IOM uint32_t PMINTSEL18 : 1; + __IOM uint32_t PMINTSEL19 : 1; + __IOM uint32_t PMINTSEL20 : 1; + __IOM uint32_t PMINTSEL21 : 1; + __IOM uint32_t PMINTSEL22 : 1; + __IOM uint32_t PMINTSEL23 : 1; + __IOM uint32_t PMINTSEL24 : 1; + __IOM uint32_t PMINTSEL25 : 1; + __IOM uint32_t PMINTSEL26 : 1; + __IOM uint32_t PMINTSEL27 : 1; + __IOM uint32_t PMINTSEL28 : 1; + __IOM uint32_t PMINTSEL29 : 1; + __IOM uint32_t PMINTSEL30 : 1; + __IOM uint32_t PMINTSEL31 : 1; + } INTPMSEL0_b; + }; + union + { + __IOM uint32_t INTPMSEL1; + struct + { + __IOM uint32_t PMINTSEL32 : 1; + __IOM uint32_t PMINTSEL33 : 1; + __IOM uint32_t PMINTSEL34 : 1; + __IOM uint32_t PMINTSEL35 : 1; + __IOM uint32_t PMINTSEL36 : 1; + __IOM uint32_t PMINTSEL37 : 1; + __IOM uint32_t PMINTSEL38 : 1; + __IOM uint32_t PMINTSEL39 : 1; + __IOM uint32_t PMINTSEL40 : 1; + __IOM uint32_t PMINTSEL41 : 1; + __IOM uint32_t PMINTSEL42 : 1; + __IOM uint32_t PMINTSEL43 : 1; + uint32_t : 20; + } INTPMSEL1_b; + }; +} R_INTC_IM33_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +#if BSP_FEATURE_CURRENT_CORE_IS_CM33_FPU + #define R_INTC_IM33_BASE 0x41070000 +#else + #define R_INTC_IM33_BASE 0x41060000 +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_INTC_IM33 ((R_INTC_IM33_Type *) R_INTC_IM33_BASE) + +#endif /* INTC_IM33_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/mhu_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/mhu_iodefine.h new file mode 100644 index 00000000..3f4022de --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/mhu_iodefine.h @@ -0,0 +1,163 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : mhu_iodefine.h + * Version : 1.00 + * Description : IO define file for mhu. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef MHU_IODEFINE_H +#define MHU_IODEFINE_H + +typedef struct +{ + union + { + __IM uint32_t MSG_INT_STSn; + struct + { + __IM uint32_t STAT : 1; + uint32_t : 31; + } MSG_INT_STSn_b; + }; + + union + { + __IOM uint32_t MSG_INT_SETn; + struct + { + __IOM uint32_t SET : 1; + uint32_t : 31; + } MSG_INT_SETn_b; + }; + + union + { + __IOM uint32_t MSG_INT_CLRn; + struct + { + __IOM uint32_t CLEAR : 1; + uint32_t : 31; + } MSG_INT_CLRn_b; + }; + + __IM uint8_t RESERVED[4]; + union + { + __IM uint32_t RSP_INT_STSn; + struct + { + __IM uint32_t STAT : 1; + uint32_t : 31; + } RSP_INT_STSn_b; + }; + + union + { + __IOM uint32_t RSP_INT_SETn; + struct + { + __IOM uint32_t SET : 1; + uint32_t : 31; + } RSP_INT_SETn_b; + }; + + union + { + __IOM uint32_t RSP_INT_CLRn; + struct + { + __IOM uint32_t CLEAR : 1; + uint32_t : 31; + } RSP_INT_CLRn_b; + }; +} R_MHU0_Type; + +typedef struct +{ + union + { + __IM uint32_t SW_INT_STSn; + struct + { + __IM uint32_t STAT : 1; + uint32_t : 31; + } SW_INT_STSn_b; + }; + + union + { + __IOM uint32_t SW_INT_SETn; + struct + { + __IOM uint32_t SET : 1; + uint32_t : 31; + } SW_INT_SETn_b; + }; + + union + { + __IOM uint32_t SW_INT_CLRn; + struct + { + __IOM uint32_t CLEAR : 1; + uint32_t : 31; + } SW_INT_CLRn_b; + }; +} R_MHU_SWINT0_Type; + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Address Map ====== */ +/* ================================================================================================================= */ + +#define R_MHU_NS0_BASE 0x50400000 +#define R_MHU_NS1_BASE 0x50400020 +#define R_MHU_NS2_BASE 0x50400040 +#define R_MHU_NS3_BASE 0x50400060 +#define R_MHU_NS4_BASE 0x50400080 +#define R_MHU_NS5_BASE 0x504000A0 +#define R_MHU_SWINT0_BASE 0x50400800 +#define R_MHU_SWINT1_BASE 0x50400810 +#define R_MHU_SWINT2_BASE 0x50400820 +#define R_MHU_SWINT3_BASE 0x50400830 +#define R_MHU_S0_BASE 0x40401000 +#define R_MHU_S1_BASE 0x40401020 +#define R_MHU_S2_BASE 0x40401040 +#define R_MHU_S3_BASE 0x40401060 +#define R_MHU_S4_BASE 0x40401080 +#define R_MHU_S5_BASE 0x404010A0 + +/* ================================================================================================================= */ +/* ================ Peripheral declaration ====== */ +/* ================================================================================================================= */ + +#define R_MHU_NS0 ((R_MHU0_Type *) R_MHU_NS0_BASE) +#define R_MHU_NS1 ((R_MHU0_Type *) R_MHU_NS1_BASE) +#define R_MHU_NS2 ((R_MHU0_Type *) R_MHU_NS2_BASE) +#define R_MHU_NS3 ((R_MHU0_Type *) R_MHU_NS3_BASE) +#define R_MHU_NS4 ((R_MHU0_Type *) R_MHU_NS4_BASE) +#define R_MHU_NS5 ((R_MHU0_Type *) R_MHU_NS5_BASE) +#define R_MHU_SWINT0 ((R_MHU_SWINT0_Type *) R_MHU_SWINT0_BASE) +#define R_MHU_SWINT1 ((R_MHU_SWINT0_Type *) R_MHU_SWINT1_BASE) +#define R_MHU_SWINT2 ((R_MHU_SWINT0_Type *) R_MHU_SWINT2_BASE) +#define R_MHU_SWINT3 ((R_MHU_SWINT0_Type *) R_MHU_SWINT3_BASE) +#define R_MHU_S0 ((R_MHU0_Type *) R_MHU_S0_BASE) +#define R_MHU_S1 ((R_MHU0_Type *) R_MHU_S1_BASE) +#define R_MHU_S2 ((R_MHU0_Type *) R_MHU_S2_BASE) +#define R_MHU_S3 ((R_MHU0_Type *) R_MHU_S3_BASE) +#define R_MHU_S4 ((R_MHU0_Type *) R_MHU_S4_BASE) +#define R_MHU_S5 ((R_MHU0_Type *) R_MHU_S5_BASE) + +#endif /* MHU_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/poeg_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/poeg_iodefine.h new file mode 100644 index 00000000..1749f54f --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/poeg_iodefine.h @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : poeg_iodefine.h + * Version : 1.00 + * Description : IO define file for poeg. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef POEG_IODEFINE_H +#define POEG_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t POEGGn; + struct + { + __IOM uint32_t PIDF : 1; + __IOM uint32_t IOCF : 1; + uint32_t : 1; + __IOM uint32_t SSF : 1; + __IOM uint32_t PIDE : 1; + __IOM uint32_t IOCE : 1; + uint32_t : 10; + __IM uint32_t ST : 1; + uint32_t : 11; + __IOM uint32_t INV : 1; + __IOM uint32_t NFEN : 1; + __IOM uint32_t NFCS : 2; + } POEGGn_b; + }; +} R_POEGA_Type; + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Address Map ====== */ +/* ================================================================================================================= */ + +#define R_POEGA_BASE 0x40048800 +#define R_POEGB_BASE 0x40048C00 +#define R_POEGC_BASE 0x40049000 +#define R_POEGD_BASE 0x40049400 + +/* ================================================================================================================= */ +/* ================ Peripheral declaration ====== */ +/* ================================================================================================================= */ + +#define R_POEGA ((R_POEGA_Type *) R_POEGA_BASE) +#define R_POEGB ((R_POEGA_Type *) R_POEGB_BASE) +#define R_POEGC ((R_POEGA_Type *) R_POEGC_BASE) +#define R_POEGD ((R_POEGA_Type *) R_POEGD_BASE) + +#endif /* POEG_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/riic_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/riic_iodefine.h new file mode 100644 index 00000000..205ddb1a --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/riic_iodefine.h @@ -0,0 +1,280 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : riic_iodefine.h + * Version : 1.00 + * Description : IO define file for riic. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef RIIC_IODEFINE_H +#define RIIC_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint8_t ICCR1; + struct + { + __IM uint8_t SDAI : 1; + __IM uint8_t SCLI : 1; + __IOM uint8_t SDAO : 1; + __IOM uint8_t SCLO : 1; + __IOM uint8_t SOWP : 1; + __IOM uint8_t CLO : 1; + __IOM uint8_t IICRST : 1; + __IOM uint8_t ICE : 1; + } ICCR1_b; + }; + union + { + __IOM uint8_t ICCR2; + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; + __IOM uint8_t RS : 1; + __IOM uint8_t SP : 1; + uint8_t : 1; + __IM uint8_t TRS : 1; + __IM uint8_t MST : 1; + __IM uint8_t BBSY : 1; + } ICCR2_b; + }; + union + { + __IOM uint8_t ICMR1; + struct + { + __IOM uint8_t BC : 3; + __IOM uint8_t BCWP : 1; + __IOM uint8_t CKS : 3; + uint8_t : 1; + } ICMR1_b; + }; + union + { + __IOM uint8_t ICMR2; + struct + { + __IOM uint8_t TMOS : 1; + __IOM uint8_t TMOL : 1; + __IOM uint8_t TMOH : 1; + uint8_t : 1; + __IOM uint8_t SDDL : 3; + __IOM uint8_t DLCS : 1; + } ICMR2_b; + }; + union + { + __IOM uint8_t ICMR3; + struct + { + __IOM uint8_t NF : 2; + __IM uint8_t ACKBR : 1; + __IOM uint8_t ACKBT : 1; + __OM uint8_t ACKWP : 1; + __IOM uint8_t RDRFS : 1; + __IOM uint8_t WAIT : 1; + __IOM uint8_t SMBE : 1; + } ICMR3_b; + }; + union + { + __IOM uint8_t ICFER; + struct + { + __IOM uint8_t TMOE : 1; + __IOM uint8_t MALE : 1; + __IOM uint8_t NALE : 1; + __IOM uint8_t SALE : 1; + __IOM uint8_t NACKE : 1; + __IOM uint8_t NFE : 1; + __IOM uint8_t SCLE : 1; + __IOM uint8_t FMPE : 1; + } ICFER_b; + }; + union + { + __IOM uint8_t ICSER; + struct + { + __IOM uint8_t SAR0 : 1; + __IOM uint8_t SAR1 : 1; + __IOM uint8_t SAR2 : 1; + __IOM uint8_t GCE : 1; + uint8_t : 1; + __IOM uint8_t DIDE : 1; + uint8_t : 1; + __IOM uint8_t HOAE : 1; + } ICSER_b; + }; + union + { + __IOM uint8_t ICIER; + struct + { + __IOM uint8_t TMOIE : 1; + __IOM uint8_t ALIE : 1; + __IOM uint8_t STIE : 1; + __IOM uint8_t SPIE : 1; + __IOM uint8_t NAKIE : 1; + __IOM uint8_t RIE : 1; + __IOM uint8_t TEIE : 1; + __IOM uint8_t TIE : 1; + } ICIER_b; + }; + union + { + __IOM uint8_t ICSR1; + struct + { + __IOM uint8_t AAS0 : 1; + __IOM uint8_t AAS1 : 1; + __IOM uint8_t AAS2 : 1; + __IOM uint8_t GCA : 1; + uint8_t : 1; + __IOM uint8_t DID : 1; + uint8_t : 1; + __IOM uint8_t HOA : 1; + } ICSR1_b; + }; + union + { + __IOM uint8_t ICSR2; + struct + { + __IOM uint8_t TMOF : 1; + __IOM uint8_t AL : 1; + __IOM uint8_t START : 1; + __IOM uint8_t STOP : 1; + __IOM uint8_t NACKF : 1; + __IOM uint8_t RDRF : 1; + __IOM uint8_t TEND : 1; + __IM uint8_t TDRE : 1; + } ICSR2_b; + }; + union + { + __IOM uint8_t ICSAR0; + struct + { + __IOM uint8_t SVA0 : 1; + __IOM uint8_t SVA : 7; + } ICSAR0_b; + }; + union + { + __IOM uint8_t ICSARU0; + struct + { + __IOM uint8_t FS : 1; + __IOM uint8_t SVA : 2; + uint8_t : 5; + } ICSARU0_b; + }; + union + { + __IOM uint8_t ICSAR1; + struct + { + __IOM uint8_t SVA0 : 1; + __IOM uint8_t SVA : 7; + } ICSAR1_b; + }; + union + { + __IOM uint8_t ICSARU1; + struct + { + __IOM uint8_t FS : 1; + __IOM uint8_t SVA : 2; + uint8_t : 5; + } ICSARU1_b; + }; + union + { + __IOM uint8_t ICSAR2; + struct + { + __IOM uint8_t SVA0 : 1; + __IOM uint8_t SVA : 7; + } ICSAR2_b; + }; + union + { + __IOM uint8_t ICSARU2; + struct + { + __IOM uint8_t FS : 1; + __IOM uint8_t SVA : 2; + uint8_t : 5; + } ICSARU2_b; + }; + union + { + __IOM uint8_t ICBRL; + struct + { + __IOM uint8_t BRL : 5; + uint8_t : 3; + } ICBRL_b; + }; + union + { + __IOM uint8_t ICBRH; + struct + { + __IOM uint8_t BRH : 5; + uint8_t : 3; + } ICBRH_b; + }; + union + { + __IOM uint8_t ICDRT; + struct + { + __IOM uint8_t DRT : 8; + } ICDRT_b; + }; + union + { + __IM uint8_t ICDRR; + struct + { + __IM uint8_t DRR : 8; + } ICDRR_b; + }; +} R_RIIC0_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_RIIC0_BASE 0x40090000 +#define R_RIIC1_BASE 0x40090400 +#define R_RIIC2_BASE 0x40090800 +#define R_RIIC3_BASE 0x40090C00 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_RIIC0 ((R_RIIC0_Type *) R_RIIC0_BASE) +#define R_RIIC1 ((R_RIIC0_Type *) R_RIIC1_BASE) +#define R_RIIC2 ((R_RIIC0_Type *) R_RIIC2_BASE) +#define R_RIIC3 ((R_RIIC0_Type *) R_RIIC3_BASE) + +#endif /* RIIC_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/rspi_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/rspi_iodefine.h new file mode 100644 index 00000000..b8b38f3f --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/rspi_iodefine.h @@ -0,0 +1,291 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : rspi_iodefine.h + * Version : 1.00 + * Description : IO define file for rspi. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef RSPI_IODEFINE_H +#define RSPI_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint8_t SPCR; + struct + { + uint8_t : 2; + __IOM uint8_t MODFEN : 1; + __IOM uint8_t MSTR : 1; + __IOM uint8_t SPEIE : 1; + __IOM uint8_t SPTIE : 1; + __IOM uint8_t SPE : 1; + __IOM uint8_t SPRIE : 1; + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; + struct + { + __IOM uint8_t SSL0P : 1; + uint8_t : 7; + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; + struct + { + __IOM uint8_t SPLP : 1; + uint8_t : 3; + __IOM uint8_t MOIFV : 1; + __IOM uint8_t MOIFE : 1; + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; + struct + { + __IOM uint8_t OVRF : 1; + uint8_t : 1; + __IOM uint8_t MODF : 1; + uint8_t : 2; + __IM uint8_t SPTEF : 1; + __IM uint8_t TEND : 1; + __IM uint8_t SPRF : 1; + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; + struct + { + __IOM uint16_t L; + __IOM uint16_t H; + } SPDR_hword; + struct + { + __IOM uint8_t LL; + __IOM uint8_t LH; + __IOM uint8_t HL; + __IOM uint8_t HH; + } SPDR_byte; + struct + { + __IOM uint32_t SPD : 32; + } SPDR_b; + }; + + union + { + __IOM uint8_t SPSCR; + struct + { + __IOM uint8_t SPSLN : 2; + uint8_t : 6; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; + struct + { + __IM uint8_t SPCP : 2; + uint8_t : 6; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; + struct + { + __IOM uint8_t SPR : 8; + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; + struct + { + uint8_t : 5; + __IOM uint8_t SPLW : 2; + __IOM uint8_t TXDMY : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; + struct + { + __IOM uint8_t SCKDL : 3; + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; + struct + { + __IOM uint8_t SLNDL : 3; + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; + struct + { + __IOM uint8_t SPNDL : 3; + uint8_t : 5; + } SPND_b; + }; + + __IM uint8_t RESERVED[1]; + union + { + __IOM uint16_t SPCMD0; + struct + { + __IOM uint16_t CPHA : 1; + __IOM uint16_t CPOL : 1; + __IOM uint16_t BRDV : 2; + uint16_t : 3; + __IOM uint16_t SSLKP : 1; + __IOM uint16_t SPB : 4; + __IOM uint16_t LSBF : 1; + __IOM uint16_t SPNDEN : 1; + __IOM uint16_t SLNDEN : 1; + __IOM uint16_t SCKDEN : 1; + } SPCMD0_b; + }; + + union + { + __IOM uint16_t SPCMD1; + struct + { + __IOM uint16_t CPHA : 1; + __IOM uint16_t CPOL : 1; + __IOM uint16_t BRDV : 2; + uint16_t : 3; + __IOM uint16_t SSLKP : 1; + __IOM uint16_t SPB : 4; + __IOM uint16_t LSBF : 1; + __IOM uint16_t SPNDEN : 1; + __IOM uint16_t SLNDEN : 1; + __IOM uint16_t SCKDEN : 1; + } SPCMD1_b; + }; + + union + { + __IOM uint16_t SPCMD2; + struct + { + __IOM uint16_t CPHA : 1; + __IOM uint16_t CPOL : 1; + __IOM uint16_t BRDV : 2; + uint16_t : 3; + __IOM uint16_t SSLKP : 1; + __IOM uint16_t SPB : 4; + __IOM uint16_t LSBF : 1; + __IOM uint16_t SPNDEN : 1; + __IOM uint16_t SLNDEN : 1; + __IOM uint16_t SCKDEN : 1; + } SPCMD2_b; + }; + + union + { + __IOM uint16_t SPCMD3; + struct + { + __IOM uint16_t CPHA : 1; + __IOM uint16_t CPOL : 1; + __IOM uint16_t BRDV : 2; + uint16_t : 3; + __IOM uint16_t SSLKP : 1; + __IOM uint16_t SPB : 4; + __IOM uint16_t LSBF : 1; + __IOM uint16_t SPNDEN : 1; + __IOM uint16_t SLNDEN : 1; + __IOM uint16_t SCKDEN : 1; + } SPCMD3_b; + }; + + __IM uint8_t RESERVED1[8]; + union + { + __IOM uint8_t SPBFCR; + struct + { + __IOM uint8_t RXTRG : 3; + uint8_t : 1; + __IOM uint8_t TXTRG : 2; + __IOM uint8_t RXRST : 1; + __IOM uint8_t TXRST : 1; + } SPBFCR_b; + }; + + __IM uint8_t RESERVED2[1]; + union + { + __IM uint16_t SPBFDR; + struct + { + __IM uint16_t R : 6; + uint16_t : 2; + __IM uint16_t T : 4; + uint16_t : 4; + } SPBFDR_b; + }; +} R_RSPI0_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_RSPI0_BASE 0x400AA000 +#define R_RSPI1_BASE 0x400AA400 +#define R_RSPI2_BASE 0x400AA800 +#define R_RSPI3_BASE 0x400AAC00 +#define R_RSPI4_BASE 0x400AB000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_RSPI0 ((R_RSPI0_Type *) R_RSPI0_BASE) +#define R_RSPI1 ((R_RSPI0_Type *) R_RSPI1_BASE) +#define R_RSPI2 ((R_RSPI0_Type *) R_RSPI2_BASE) +#define R_RSPI3 ((R_RSPI0_Type *) R_RSPI3_BASE) +#define R_RSPI4 ((R_RSPI0_Type *) R_RSPI4_BASE) + +#endif /* RSPI_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/scifa_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/scifa_iodefine.h new file mode 100644 index 00000000..65616bea --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/scifa_iodefine.h @@ -0,0 +1,230 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : scifa_iodefine.h + * Version : 1.00 + * Description : IO define file for scifa. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef SCIFA_IODEFINE_H +#define SCIFA_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint16_t SMR; + struct + { + __IOM uint16_t CKS : 2; + uint16_t : 1; + __IOM uint16_t STOP : 1; + __IOM uint16_t PM : 1; + __IOM uint16_t PE : 1; + __IOM uint16_t CHR : 1; + __IOM uint16_t CM : 1; + uint16_t : 8; + } SMR_b; + }; + + union + { + union + { + __IOM uint8_t MDDR; + struct + { + __IOM uint8_t MDDR : 8; + } MDDR_b; + }; + + union + { + __IOM uint8_t BRR; + struct + { + __IOM uint8_t BRR : 8; + } BRR_b; + }; + }; + + __IM uint8_t RESERVED[1]; + union + { + __IOM uint16_t SCR; + struct + { + __IOM uint16_t CKE : 2; + __IOM uint16_t TEIE : 1; + __IOM uint16_t REIE : 1; + __IOM uint16_t RE : 1; + __IOM uint16_t TE : 1; + __IOM uint16_t RIE : 1; + __IOM uint16_t TIE : 1; + uint16_t : 8; + } SCR_b; + }; + + union + { + __OM uint8_t FTDR; + struct + { + __OM uint8_t FTDR : 8; + } FTDR_b; + }; + + __IM uint8_t RESERVED1[1]; + union + { + __IOM uint16_t FSR; + struct + { + __IOM uint16_t DR : 1; + __IOM uint16_t RDF : 1; + __IM uint16_t PER : 1; + __IM uint16_t FER : 1; + __IOM uint16_t BRK : 1; + __IOM uint16_t TDFE : 1; + __IOM uint16_t TEND : 1; + __IOM uint16_t ER : 1; + uint16_t : 8; + } FSR_b; + }; + + union + { + __IM uint8_t FRDR; + struct + { + __IM uint8_t FRDR : 8; + } FRDR_b; + }; + + __IM uint8_t RESERVED2[1]; + union + { + __IOM uint16_t FCR; + struct + { + __IOM uint16_t LOOP : 1; + __IOM uint16_t RFRST : 1; + __IOM uint16_t TFRST : 1; + __IOM uint16_t MCE : 1; + __IOM uint16_t TTRG : 2; + __IOM uint16_t RTRG : 2; + __IOM uint16_t RSTRG : 3; + uint16_t : 5; + } FCR_b; + }; + + union + { + __IM uint16_t FDR; + struct + { + __IM uint16_t R : 5; + uint16_t : 3; + __IM uint16_t T : 5; + uint16_t : 3; + } FDR_b; + }; + + union + { + __IOM uint16_t SPTR; + struct + { + __IOM uint16_t SPB2DT : 1; + __IOM uint16_t SPB2IO : 1; + __IOM uint16_t SCKDT : 1; + __IOM uint16_t SCKIO : 1; + __IOM uint16_t CTS2DT : 1; + __IOM uint16_t CTS2IO : 1; + __IOM uint16_t RTS2DT : 1; + __IOM uint16_t RTS2IO : 1; + uint16_t : 8; + } SPTR_b; + }; + + union + { + __IOM uint16_t LSR; + struct + { + __IOM uint16_t ORER : 1; + uint16_t : 1; + __IM uint16_t FER : 4; + uint16_t : 2; + __IM uint16_t PER : 4; + uint16_t : 4; + } LSR_b; + }; + + union + { + __IOM uint8_t SEMR; + struct + { + __IOM uint8_t ABCS0 : 1; + uint8_t : 1; + __IOM uint8_t NFEN : 1; + __IOM uint8_t DIR : 1; + __IOM uint8_t MDDRS : 1; + __IOM uint8_t BRME : 1; + uint8_t : 1; + __IOM uint8_t BGDM : 1; + } SEMR_b; + }; + + __IM uint8_t RESERVED3[1]; + union + { + __IOM uint16_t FTCR; + struct + { + __IOM uint16_t TFTC : 5; + uint16_t : 2; + __IOM uint16_t TTRGS : 1; + __IOM uint16_t RFTC : 5; + uint16_t : 2; + __IOM uint16_t RTRGS : 1; + } FTCR_b; + }; +} R_SCIFA0_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_SCIFA0_BASE 0x4004B800 +#define R_SCIFA1_BASE 0x4004BC00 +#define R_SCIFA2_BASE 0x4004C000 +#define R_SCIFA3_BASE 0x4004C400 +#define R_SCIFA4_BASE 0x4004C800 +#define R_SCIFA5_BASE 0x4004E000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_SCIFA0 ((R_SCIFA0_Type *) R_SCIFA0_BASE) +#define R_SCIFA1 ((R_SCIFA0_Type *) R_SCIFA1_BASE) +#define R_SCIFA2 ((R_SCIFA0_Type *) R_SCIFA2_BASE) +#define R_SCIFA3 ((R_SCIFA0_Type *) R_SCIFA3_BASE) +#define R_SCIFA4 ((R_SCIFA0_Type *) R_SCIFA4_BASE) +#define R_SCIFA5 ((R_SCIFA0_Type *) R_SCIFA5_BASE) + +#endif /* SCIFA_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/ssi_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/ssi_iodefine.h new file mode 100644 index 00000000..6aefc80c --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/ssi_iodefine.h @@ -0,0 +1,190 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : ssi_iodefine.h + * Version : 1.00 + * Description : IO define file for ssi. + *********************************************************************************************************************/ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef SSI_IODEFINE_H +#define SSI_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t SSICR; + struct + { + __IOM uint32_t REN : 1; + __IOM uint32_t TEN : 1; + uint32_t : 1; + __IOM uint32_t MUEN : 1; + __IOM uint32_t CKDV : 4; + __IOM uint32_t DEL : 1; + __IOM uint32_t PDTA : 1; + __IOM uint32_t SDTA : 1; + __IOM uint32_t SPDP : 1; + __IOM uint32_t LRCKP : 1; + __IOM uint32_t BCKP : 1; + __IOM uint32_t MST : 1; + uint32_t : 1; + __IOM uint32_t SWL : 3; + __IOM uint32_t DWL : 3; + __IOM uint32_t FRM : 2; + uint32_t : 1; + __IOM uint32_t IIEN : 1; + __IOM uint32_t ROIEN : 1; + __IOM uint32_t RUIEN : 1; + __IOM uint32_t TOIEN : 1; + __IOM uint32_t TUIEN : 1; + __IOM uint32_t CKS : 1; + uint32_t : 1; + } SSICR_b; + }; + union + { + __IOM uint32_t SSISR; + struct + { + uint32_t : 25; + __IOM uint32_t IIRQ : 1; + __IOM uint32_t ROIRQ : 1; + __IOM uint32_t RUIRQ : 1; + __IOM uint32_t TOIRQ : 1; + __IOM uint32_t TUIRQ : 1; + uint32_t : 2; + } SSISR_b; + }; + __IM uint8_t RESERVED[8]; + union + { + __IOM uint32_t SSIFCR; + struct + { + __IOM uint32_t RFRST : 1; + __IOM uint32_t TFRST : 1; + __IOM uint32_t RIE : 1; + __IOM uint32_t TIE : 1; + uint32_t : 4; + __IOM uint32_t RXDNCE : 1; + __IOM uint32_t LRCKNCE : 1; + __IOM uint32_t BCKNCE : 1; + __IOM uint32_t BSW : 1; + uint32_t : 4; + __IOM uint32_t SSIRST : 1; + uint32_t : 14; + __IOM uint32_t AUCKE : 1; + } SSIFCR_b; + }; + union + { + __IOM uint32_t SSIFSR; + struct + { + __IOM uint32_t RDF : 1; + uint32_t : 7; + __IM uint32_t RDC : 6; + uint32_t : 2; + __IOM uint32_t TDE : 1; + uint32_t : 7; + __IM uint32_t TDC : 6; + uint32_t : 2; + } SSIFSR_b; + }; + union + { + __OM uint32_t SSIFTDR; + struct + { + __OM uint16_t L; + __OM uint16_t H; + } SSIFTDR_hword; + struct + { + __OM uint8_t LL; + __OM uint8_t LH; + __OM uint8_t HL; + __OM uint8_t HH; + } SSIFTDR_byte; + struct + { + __OM uint32_t SSIFTDR : 32; + } SSIFTDR_b; + }; + union + { + __IM uint32_t SSIFRDR; + struct + { + __IM uint16_t L; + __IM uint16_t H; + } SSIFRDR_hword; + struct + { + __IM uint8_t LL; + __IM uint8_t LH; + __IM uint8_t HL; + __IM uint8_t HH; + } SSIFRDR_byte; + struct + { + __IM uint32_t SSIFRDR : 32; + } SSIFRDR_b; + }; + union + { + __IOM uint32_t SSIOFR; + struct + { + __IOM uint32_t OMOD : 2; + uint32_t : 6; + __IOM uint32_t LRCONT : 1; + __IOM uint32_t BCKSTP : 1; + uint32_t : 22; + } SSIOFR_b; + }; + union + { + __IOM uint32_t SSISCR; + struct + { + __IOM uint32_t RDFS : 5; + uint32_t : 3; + __IOM uint32_t TDES : 5; + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_SSI0_BASE 0x40049C00 +#define R_SSI1_BASE 0x4004A000 +#define R_SSI2_BASE 0x4004A400 +#define R_SSI3_BASE 0x4004A800 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) +#define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) +#define R_SSI2 ((R_SSI0_Type *) R_SSI2_BASE) +#define R_SSI3 ((R_SSI0_Type *) R_SSI3_BASE) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/sysc_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/sysc_iodefine.h new file mode 100644 index 00000000..bc54757e --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/sysc_iodefine.h @@ -0,0 +1,1169 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : sysc_iodefine.h + * Version : 1.00 + * Description : IO define file for sysc. + *********************************************************************************************************************//* =========================================================================================================================== */ + +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef SYSC_IODEFINE_H +#define SYSC_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t SYS_MSTACCCTL0; + struct + { + __IOM uint32_t DMAC0_AWPU : 1; + __IOM uint32_t DMAC0_AWNS : 1; + uint32_t : 1; + __IOM uint32_t DMAC0_AWSEL : 1; + __IOM uint32_t DMAC0_ARPU : 1; + __IOM uint32_t DMAC0_ARNS : 1; + uint32_t : 1; + __IOM uint32_t DMAC0_ARSEL : 1; + __IM uint32_t DMAC1_AWPU : 1; + __IM uint32_t DMAC1_AWNS : 1; + uint32_t : 1; + __IM uint32_t DMAC1_AWSEL : 1; + __IM uint32_t DMAC1_ARPU : 1; + __IM uint32_t DMAC1_ARNS : 1; + uint32_t : 1; + __IM uint32_t DMAC1_ARSEL : 1; + uint32_t : 16; + } SYS_MSTACCCTL0_b; + }; + union + { + __IOM uint32_t SYS_MSTACCCTL1; + struct + { + __IOM uint32_t SDHI0_AWPU : 1; + __IOM uint32_t SDHI0_AWNS : 1; + uint32_t : 1; + __IOM uint32_t SDHI0_AWSEL : 1; + __IOM uint32_t SDHI0_ARPU : 1; + __IOM uint32_t SDHI0_ARNS : 1; + uint32_t : 1; + __IOM uint32_t SDHI0_ARSEL : 1; + __IOM uint32_t SDHI1_AWPU : 1; + __IOM uint32_t SDHI1_AWNS : 1; + uint32_t : 1; + __IOM uint32_t SDHI1_AWSEL : 1; + __IOM uint32_t SDHI1_ARPU : 1; + __IOM uint32_t SDHI1_ARNS : 1; + uint32_t : 1; + __IOM uint32_t SDHI1_ARSEL : 1; + __IOM uint32_t GEther0_AWPU : 1; + __IOM uint32_t GEther0_AWNS : 1; + uint32_t : 1; + __IOM uint32_t GEther0_AWSEL : 1; + __IOM uint32_t GEther0_ARPU : 1; + __IOM uint32_t GEther0_ARNS : 1; + uint32_t : 1; + __IOM uint32_t GEther0_ARSEL : 1; + __IOM uint32_t GEther1_AWPU : 1; + __IOM uint32_t GEther1_AWNS : 1; + uint32_t : 1; + __IOM uint32_t GEther1_AWSEL : 1; + __IOM uint32_t GEther1_ARPU : 1; + __IOM uint32_t GEther1_ARNS : 1; + uint32_t : 1; + __IOM uint32_t GEther1_ARSEL : 1; + } SYS_MSTACCCTL1_b; + }; + union + { + __IOM uint32_t SYS_MSTACCCTL2; + struct + { + __IOM uint32_t USB20H_AWPU : 1; + __IOM uint32_t USB20H_AWNS : 1; + uint32_t : 1; + __IOM uint32_t USB20H_AWSEL : 1; + __IOM uint32_t USB20H_ARPU : 1; + __IOM uint32_t USB20H_ARNS : 1; + uint32_t : 1; + __IOM uint32_t USB20H_ARSEL : 1; + __IOM uint32_t USB20D_AWPU : 1; + __IOM uint32_t USB20D_AWNS : 1; + uint32_t : 1; + __IOM uint32_t USB20D_AWSEL : 1; + __IOM uint32_t USB20D_ARPU : 1; + __IOM uint32_t USB20D_ARNS : 1; + uint32_t : 1; + __IOM uint32_t USB20D_ARSEL : 1; + __IOM uint32_t USB21H_AWPU : 1; + __IOM uint32_t USB21H_AWNS : 1; + uint32_t : 1; + __IOM uint32_t USB21H_AWSEL : 1; + __IOM uint32_t USB21H_ARPU : 1; + __IOM uint32_t USB21H_ARNS : 1; + uint32_t : 1; + __IOM uint32_t USB21H_ARSEL : 1; + uint32_t : 8; + } SYS_MSTACCCTL2_b; + }; + __IM uint8_t RESERVED[12]; + union + { + __IOM uint32_t SYS_MSTACCCTL6; + struct + { + __IOM uint32_t SDHI2_AWPU : 1; + __IOM uint32_t SDHI2_AWNS : 1; + uint32_t : 1; + __IOM uint32_t SDHI2_AWSEL : 1; + __IOM uint32_t SDHI2_ARPU : 1; + __IOM uint32_t SDHI2_ARNS : 1; + uint32_t : 1; + __IOM uint32_t SDHI2_ARSEL : 1; + __IOM uint32_t PCIE_AWPU : 1; + __IOM uint32_t PCIE_AWNS : 1; + uint32_t : 1; + __IOM uint32_t PCIE_AWSEL : 1; + __IOM uint32_t PCIE_ARPU : 1; + __IOM uint32_t PCIE_ARNS : 1; + uint32_t : 1; + __IOM uint32_t PCIE_ARSEL : 1; + uint32_t : 16; + } SYS_MSTACCCTL6_b; + }; + __IM uint8_t RESERVED1[228]; + union + { + __IOM uint32_t SYS_SLVACCCTL0; + struct + { + __IOM uint32_t SRAM0_SL : 2; + __IOM uint32_t SRAM1_SL : 2; + __IOM uint32_t SRAM2_SL : 2; + __IOM uint32_t SRAM3_SL : 2; + uint32_t : 24; + } SYS_SLVACCCTL0_b; + }; + __IM uint8_t RESERVED2[4]; + union + { + __IOM uint32_t SYS_SLVACCCTL2; + struct + { + __IOM uint32_t TZC0_SL : 2; + __IOM uint32_t TZC1_SL : 2; + __IOM uint32_t TZC2_SL : 2; + __IOM uint32_t TZC3_SL : 2; + uint32_t : 2; + __IOM uint32_t TZC5_SL : 2; + __IOM uint32_t TZC6_SL : 2; + uint32_t : 18; + } SYS_SLVACCCTL2_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL3; + struct + { + __IOM uint32_t CST_SL : 2; + __IOM uint32_t CPG_SL : 2; + __IM uint32_t SYSC_SL : 2; + __IOM uint32_t SYC_SL : 2; + __IOM uint32_t GIC_SL : 2; + __IOM uint32_t IA55IM33_SL : 2; + __IOM uint32_t GPIO_SL : 2; + __IOM uint32_t MHU_SL : 2; + uint32_t : 16; + } SYS_SLVACCCTL3_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL4; + struct + { + __IOM uint32_t DMAC0_SL : 2; + __IOM uint32_t DMAC1_SL : 2; + __IOM uint32_t OSTM0_SL : 2; + __IOM uint32_t OSTM1_SL : 2; + __IOM uint32_t OSTM2_SL : 2; + __IOM uint32_t OSTM3_SL : 2; + __IOM uint32_t OSTM4_SL : 2; + __IOM uint32_t OSTM5_SL : 2; + __IOM uint32_t OSTM6_SL : 2; + __IOM uint32_t OSTM7_SL : 2; + __IOM uint32_t WDT0_SL : 2; + __IOM uint32_t WDT1_SL : 2; + __IOM uint32_t WDT2_SL : 2; + uint32_t : 2; + __IOM uint32_t RTC_SL : 2; + uint32_t : 2; + } SYS_SLVACCCTL4_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL5; + struct + { + __IOM uint32_t MTU3A_SL : 2; + __IOM uint32_t POE3_SL : 2; + __IOM uint32_t GPT_SL : 2; + __IOM uint32_t POEG_SL : 2; + __IOM uint32_t DDR_SL : 2; + __IOM uint32_t XSPI_SL : 2; + __IOM uint32_t OCTA_SL : 2; + uint32_t : 18; + } SYS_SLVACCCTL5_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL6; + struct + { + __IOM uint32_t USBT_SL : 2; + __IOM uint32_t USBT20_SL : 2; + __IOM uint32_t USBT21_SL : 2; + __IOM uint32_t SDHI0_SL : 2; + __IOM uint32_t SDHI1_SL : 2; + __IOM uint32_t SDHI2_SL : 2; + __IOM uint32_t ETH0_SL : 2; + __IOM uint32_t ETH1_SL : 2; + __IOM uint32_t PCIE_SL : 2; + uint32_t : 14; + } SYS_SLVACCCTL6_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL7; + struct + { + __IOM uint32_t I2C0_SL : 2; + __IOM uint32_t I2C1_SL : 2; + __IOM uint32_t I2C2_SL : 2; + __IOM uint32_t I2C3_SL : 2; + __IOM uint32_t I3C_SL : 2; + __IOM uint32_t CANFD_SL : 2; + __IOM uint32_t RSPI0_SL : 2; + __IOM uint32_t RSPI1_SL : 2; + __IOM uint32_t RSPI2_SL : 2; + __IOM uint32_t RSPI3_SL : 2; + __IOM uint32_t RSPI4_SL : 2; + uint32_t : 10; + } SYS_SLVACCCTL7_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL8; + struct + { + __IOM uint32_t SCIF0_SL : 2; + __IOM uint32_t SCIF1_SL : 2; + __IOM uint32_t SCIF2_SL : 2; + __IOM uint32_t SCIF3_SL : 2; + __IOM uint32_t SCIF4_SL : 2; + __IOM uint32_t SCIF5_SL : 2; + __IOM uint32_t SCI0_SL : 2; + __IOM uint32_t SCI1_SL : 2; + __IOM uint32_t IRDA_SL : 2; + uint32_t : 14; + } SYS_SLVACCCTL8_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL9; + struct + { + __IOM uint32_t SSIF0_SL : 2; + __IOM uint32_t SSIF1_SL : 2; + __IOM uint32_t SSIF2_SL : 2; + __IOM uint32_t SSIF3_SL : 2; + __IOM uint32_t SRC_SL : 2; + __IOM uint32_t SPDIF_SL : 2; + __IOM uint32_t PDM_SL : 2; + uint32_t : 18; + } SYS_SLVACCCTL9_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL10; + struct + { + __IOM uint32_t ADC_SL : 2; + __IOM uint32_t TSU_SL : 2; + uint32_t : 28; + } SYS_SLVACCCTL10_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL11; + struct + { + uint32_t : 2; + __IOM uint32_t OTP_SL : 2; + uint32_t : 6; + __IOM uint32_t VBATT_SL : 2; + uint32_t : 20; + } SYS_SLVACCCTL11_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL12; + struct + { + __IOM uint32_t CA55_SL : 2; + __IOM uint32_t CM33_SL : 2; + __IOM uint32_t CM33FPU_SL : 2; + uint32_t : 26; + } SYS_SLVACCCTL12_b; + }; + __IM uint8_t RESERVED3[4]; + union + { + __IOM uint32_t SYS_SLVACCCTL14; + struct + { + __IOM uint32_t LSI_SL : 2; + uint32_t : 30; + } SYS_SLVACCCTL14_b; + }; + __IM uint8_t RESERVED4[4]; + union + { + __IOM uint32_t SYS_SLVACCCTL16; + struct + { + __IOM uint32_t AOF_SL : 2; + uint32_t : 30; + } SYS_SLVACCCTL16_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL17; + struct + { + __IOM uint32_t LP_SL : 2; + uint32_t : 30; + } SYS_SLVACCCTL17_b; + }; + union + { + __IOM uint32_t SYS_SLVACCCTL18; + struct + { + __IOM uint32_t GPREG_SL : 2; + uint32_t : 30; + } SYS_SLVACCCTL18_b; + }; + __IM uint8_t RESERVED5[4]; + union + { + __IOM uint32_t SYS_SLVACCCTL20; + struct + { + __IOM uint32_t IPCONT_SL : 2; + uint32_t : 30; + } SYS_SLVACCCTL20_b; + }; + __IM uint8_t RESERVED6[172]; + union + { + __IOM uint32_t SYS_RAM0_ECC; + struct + { + __IOM uint32_t VECCEN : 1; + uint32_t : 31; + } SYS_RAM0_ECC_b; + }; + union + { + __IOM uint32_t SYS_RAM0_EN; + struct + { + __IOM uint32_t VCEN : 1; + __IOM uint32_t VLWEN : 1; + uint32_t : 30; + } SYS_RAM0_EN_b; + }; + __IM uint8_t RESERVED7[8]; + union + { + __IOM uint32_t SYS_RAM1_ECC; + struct + { + __IOM uint32_t VECCEN : 1; + uint32_t : 31; + } SYS_RAM1_ECC_b; + }; + union + { + __IOM uint32_t SYS_RAM1_EN; + struct + { + __IOM uint32_t VCEN : 1; + __IOM uint32_t VLWEN : 1; + uint32_t : 30; + } SYS_RAM1_EN_b; + }; + __IM uint8_t RESERVED8[8]; + union + { + __IOM uint32_t SYS_RAM2_ECC; + struct + { + __IOM uint32_t VECCEN : 1; + uint32_t : 31; + } SYS_RAM2_ECC_b; + }; + union + { + __IOM uint32_t SYS_RAM2_EN; + struct + { + __IOM uint32_t VCEN : 1; + __IOM uint32_t VLWEN : 1; + uint32_t : 30; + } SYS_RAM2_EN_b; + }; + __IM uint8_t RESERVED9[8]; + union + { + __IOM uint32_t SYS_RAM3_ECC; + struct + { + __IOM uint32_t VECCEN : 1; + uint32_t : 31; + } SYS_RAM3_ECC_b; + }; + union + { + __IOM uint32_t SYS_RAM3_EN; + struct + { + __IOM uint32_t VCEN : 1; + __IOM uint32_t VLWEN : 1; + uint32_t : 30; + } SYS_RAM3_EN_b; + }; + __IM uint8_t RESERVED10[24]; + union + { + __IOM uint32_t SYS_WDT0_CTRL; + struct + { + __IOM uint32_t WDTSTOP : 1; + uint32_t : 15; + __IOM uint32_t WDTSTOPMASK : 1; + uint32_t : 15; + } SYS_WDT0_CTRL_b; + }; + __IM uint8_t RESERVED11[12]; + union + { + __IOM uint32_t SYS_WDT1_CTRL; + struct + { + __IOM uint32_t WDTSTOP : 1; + uint32_t : 15; + __IOM uint32_t WDTSTOPMASK : 1; + uint32_t : 15; + } SYS_WDT1_CTRL_b; + }; + __IM uint8_t RESERVED12[12]; + union + { + __IOM uint32_t SYS_WDT2_CTRL; + struct + { + __IOM uint32_t WDTSTOP : 1; + uint32_t : 15; + __IOM uint32_t WDTSTOPMASK : 1; + uint32_t : 15; + } SYS_WDT2_CTRL_b; + }; + __IM uint8_t RESERVED13[144]; + union + { + __IOM uint32_t SYS_DDR_MCAR_CTRL; + struct + { + uint32_t : 16; + __IOM uint32_t MCAR_CTRL : 1; + uint32_t : 15; + } SYS_DDR_MCAR_CTRL_b; + }; + __IM uint8_t RESERVED14[64]; + union + { + __IOM uint32_t SYS_XSPI_MAP_STAADD_CS0; + struct + { + __IOM uint32_t MAP_STAADD_CS0 : 32; + } SYS_XSPI_MAP_STAADD_CS0_b; + }; + union + { + __IOM uint32_t SYS_XSPI_MAP_ENDADD_CS0; + struct + { + __IOM uint32_t MAP_ENDADD_CS0 : 32; + } SYS_XSPI_MAP_ENDADD_CS0_b; + }; + union + { + __IOM uint32_t SYS_XSPI_MAP_STAADD_CS1; + struct + { + __IOM uint32_t MAP_STAADD_CS0 : 1; + __IOM uint32_t MAP_STAADD_CS1 : 31; + } SYS_XSPI_MAP_STAADD_CS1_b; + }; + union + { + __IOM uint32_t SYS_XSPI_MAP_ENDADD_CS1; + struct + { + __IOM uint32_t MAP_ENDADD_CS0 : 1; + __IOM uint32_t MAP_ENDADD_CS1 : 31; + } SYS_XSPI_MAP_ENDADD_CS1_b; + }; + __IM uint8_t RESERVED15[40]; + union + { + __IM uint32_t SYS_GETH0_CFG; + struct + { + uint32_t : 24; + __IM uint32_t FEC_GIGA_ENABLE : 1; + uint32_t : 7; + } SYS_GETH0_CFG_b; + }; + __IM uint8_t RESERVED16[12]; + union + { + __IM uint32_t SYS_GETH1_CFG; + struct + { + uint32_t : 24; + __IM uint32_t FEC_GIGA_ENABLE : 1; + uint32_t : 7; + } SYS_GETH1_CFG_b; + }; + __IM uint8_t RESERVED17[12]; + union + { + __IOM uint32_t SYS_PCIE_CFG; + struct + { + uint32_t : 8; + __IOM uint32_t ALLOW_ENTER_L1 : 1; + uint32_t : 23; + } SYS_PCIE_CFG_b; + }; + union + { + __IM uint32_t SYS_PCIE_MON; + struct + { + __IM uint32_t PMU_POWEROFF : 1; + __IM uint32_t CLKL1PM_REQ : 1; + uint32_t : 2; + __IM uint32_t D_STATE_OUT_F0 : 2; + uint32_t : 26; + } SYS_PCIE_MON_b; + }; + __IM uint8_t RESERVED18[4]; + union + { + __IM uint32_t SYS_PCIE_ERR_MON; + struct + { + __IM uint32_t ERR_COR_DETECTED_F0 : 1; + __IM uint32_t ERR_NONFATAL_DETECTED_F0 : 1; + __IM uint32_t ERR_FATAL_DETECTED_F0 : 1; + uint32_t : 29; + } SYS_PCIE_ERR_MON_b; + }; + __IM uint8_t RESERVED19[4]; + union + { + __IOM uint32_t SYS_PCIE_PHY; + struct + { + __IOM uint32_t MODE_RXTERMINATION : 1; + uint32_t : 31; + } SYS_PCIE_PHY_b; + }; + __IM uint8_t RESERVED20[72]; + union + { + __IOM uint32_t SYS_I2C0_CFG; + struct + { + __IOM uint32_t af_bypass : 1; + uint32_t : 31; + } SYS_I2C0_CFG_b; + }; + __IM uint8_t RESERVED21[12]; + union + { + __IOM uint32_t SYS_I2C1_CFG; + struct + { + __IOM uint32_t af_bypass : 1; + uint32_t : 31; + } SYS_I2C1_CFG_b; + }; + __IM uint8_t RESERVED22[12]; + union + { + __IOM uint32_t SYS_I2C2_CFG; + struct + { + __IOM uint32_t af_bypass : 1; + uint32_t : 31; + } SYS_I2C2_CFG_b; + }; + __IM uint8_t RESERVED23[12]; + union + { + __IOM uint32_t SYS_I2C3_CFG; + struct + { + __IOM uint32_t af_bypass : 1; + uint32_t : 31; + } SYS_I2C3_CFG_b; + }; + __IM uint8_t RESERVED24[12]; + union + { + __IOM uint32_t SYS_I3C_CFG; + struct + { + __IOM uint32_t af_bypass : 1; + uint32_t : 31; + } SYS_I3C_CFG_b; + }; + __IM uint8_t RESERVED25[980]; + union + { + __IOM uint32_t SYS_CA55_CFG_RVAL0; + struct + { + uint32_t : 2; + __IOM uint32_t RVBARADDRL0 : 30; + } SYS_CA55_CFG_RVAL0_b; + }; + union + { + __IOM uint32_t SYS_CA55_CFG_RVAH0; + struct + { + __IOM uint32_t RVBARADDRH0 : 8; + uint32_t : 24; + } SYS_CA55_CFG_RVAH0_b; + }; + __IM uint8_t RESERVED26[36]; + union + { + __IOM uint32_t SYS_CM33_CFG0; + struct + { + __IOM uint32_t CONFIGSSYSTICK : 26; + uint32_t : 6; + } SYS_CM33_CFG0_b; + }; + union + { + __IOM uint32_t SYS_CM33_CFG1; + struct + { + __IOM uint32_t CONFIGNSSYSTICK : 26; + uint32_t : 6; + } SYS_CM33_CFG1_b; + }; + union + { + __IOM uint32_t SYS_CM33_CFG2; + struct + { + uint32_t : 7; + __IOM uint32_t INITSVTOR : 25; + } SYS_CM33_CFG2_b; + }; + union + { + __IOM uint32_t SYS_CM33_CFG3; + struct + { + uint32_t : 7; + __IOM uint32_t INITNSVTOR : 25; + } SYS_CM33_CFG3_b; + }; + union + { + __IOM uint32_t SYS_CM33_LOCK; + struct + { + __IOM uint32_t LOCKSVTAIRCR : 1; + __IOM uint32_t LOCKNSVTOR : 1; + uint32_t : 30; + } SYS_CM33_LOCK_b; + }; + __IM uint8_t RESERVED27[44]; + union + { + __IOM uint32_t SYS_CM33FPU_CFG0; + struct + { + __IOM uint32_t CONFIGSSYSTICK : 26; + uint32_t : 6; + } SYS_CM33FPU_CFG0_b; + }; + union + { + __IOM uint32_t SYS_CM33FPU_CFG1; + struct + { + __IOM uint32_t CONFIGNSSYSTICK : 26; + uint32_t : 6; + } SYS_CM33FPU_CFG1_b; + }; + union + { + __IOM uint32_t SYS_CM33FPU_CFG2; + struct + { + uint32_t : 6; + __IOM uint32_t INITSVTOR : 26; + } SYS_CM33FPU_CFG2_b; + }; + union + { + __IOM uint32_t SYS_CM33FPU_CFG3; + struct + { + uint32_t : 6; + __IOM uint32_t INITNSVTOR : 26; + } SYS_CM33FPU_CFG3_b; + }; + union + { + __IOM uint32_t SYS_CM33FPU_LOCK; + struct + { + __IOM uint32_t LOCKSVTAIRCR : 1; + __IOM uint32_t LOCKNSVTOR : 1; + uint32_t : 30; + } SYS_CM33FPU_LOCK_b; + }; + __IM uint8_t RESERVED28[360]; + union + { + __IM uint32_t SYS_LSI_MODE; + struct + { + __IM uint32_t STAT_BOOTCPUSEL : 1; + uint32_t : 3; + __IM uint32_t STAT_MD_BOOT : 3; + uint32_t : 2; + __IM uint32_t STAT_DEBUGEN : 1; + uint32_t : 2; + __IM uint32_t STAT_MD_CLKS : 1; + __IM uint32_t STAT_MD_BYPASS : 1; + uint32_t : 2; + __IM uint32_t STAT_SEC_EN : 1; + uint32_t : 15; + } SYS_LSI_MODE_b; + }; + union + { + __IM uint32_t SYS_LSI_DEVID; + struct + { + uint32_t : 32; + } SYS_LSI_DEVID_b; + }; + __IM uint32_t SYS_LSI_PRR; + __IM uint8_t RESERVED29[500]; + union + { + __IOM uint32_t SYS_AOF0; + struct + { + __IOM uint32_t OFS00_SXSDHI_0 : 4; + __IOM uint32_t OFS01_SXSDHI_0 : 4; + __IOM uint32_t OFS10_SXSDHI_0 : 4; + __IOM uint32_t OFS11_SXSDHI_0 : 4; + __IOM uint32_t OFS00_SXSDHI_1 : 4; + __IOM uint32_t OFS01_SXSDHI_1 : 4; + __IOM uint32_t OFS10_SXSDHI_1 : 4; + __IOM uint32_t OFS11_SXSDHI_1 : 4; + } SYS_AOF0_b; + }; + union + { + __IOM uint32_t SYS_AOF1; + struct + { + __IOM uint32_t OFS00_SXGIGE_0 : 4; + __IOM uint32_t OFS01_SXGIGE_0 : 4; + __IOM uint32_t OFS10_SXGIGE_0 : 4; + __IOM uint32_t OFS11_SXGIGE_0 : 4; + __IOM uint32_t OFS00_SXGIGE_1 : 4; + __IOM uint32_t OFS01_SXGIGE_1 : 4; + __IOM uint32_t OFS10_SXGIGE_1 : 4; + __IOM uint32_t OFS11_SXGIGE_1 : 4; + } SYS_AOF1_b; + }; + union + { + __IOM uint32_t SYS_AOF2; + struct + { + __IOM uint32_t OFS00_SXUSB2_0_H : 4; + __IOM uint32_t OFS01_SXUSB2_0_H : 4; + __IOM uint32_t OFS10_SXUSB2_0_H : 4; + __IOM uint32_t OFS11_SXUSB2_0_H : 4; + __IOM uint32_t OFS00_SXUSB2_1 : 4; + __IOM uint32_t OFS01_SXUSB2_1 : 4; + __IOM uint32_t OFS10_SXUSB2_1 : 4; + __IOM uint32_t OFS11_SXUSB2_1 : 4; + } SYS_AOF2_b; + }; + union + { + __IOM uint32_t SYS_AOF3; + struct + { + __IOM uint32_t OFS00_SXUSB2_0_F : 4; + __IOM uint32_t OFS01_SXUSB2_0_F : 4; + __IOM uint32_t OFS10_SXUSB2_0_F : 4; + __IOM uint32_t OFS11_SXUSB2_0_F : 4; + uint32_t : 16; + } SYS_AOF3_b; + }; + __IM uint8_t RESERVED30[8]; + union + { + __IOM uint32_t SYS_AOF6; + struct + { + __IOM uint32_t OFS00_SXDMAC_S : 4; + __IOM uint32_t OFS01_SXDMAC_S : 4; + __IOM uint32_t OFS10_SXDMAC_S : 4; + __IOM uint32_t OFS11_SXDMAC_S : 4; + __IOM uint32_t OFS00_SXDMAC_NS : 4; + __IOM uint32_t OFS01_SXDMAC_NS : 4; + __IOM uint32_t OFS10_SXDMAC_NS : 4; + __IOM uint32_t OFS11_SXDMAC_NS : 4; + } SYS_AOF6_b; + }; + __IM uint8_t RESERVED31[8]; + union + { + __IOM uint32_t SYS_AOF9; + struct + { + __IOM uint32_t OFS00_SXSDHI_2 : 4; + __IOM uint32_t OFS01_SXDMAC_S : 4; + __IOM uint32_t OFS10_SXDMAC_S : 4; + __IOM uint32_t OFS11_SXDMAC_S : 4; + uint32_t : 16; + } SYS_AOF9_b; + }; + __IM uint8_t RESERVED32[220]; + union + { + __IOM uint32_t SYS_LP_CTL1; + struct + { + uint32_t : 8; + __IOM uint32_t CA55SLEEP_REQ : 1; + uint32_t : 3; + __IOM uint32_t CM33SLEEP_REQ : 1; + __IOM uint32_t CM33FPUSLEEP_REQ : 1; + uint32_t : 10; + __IOM uint32_t CA55SLEEP_ACK : 1; + uint32_t : 3; + __IOM uint32_t CM33SLEEP_ACK : 1; + __IOM uint32_t CM33FPUSLEEP_ACK : 1; + uint32_t : 2; + } SYS_LP_CTL1_b; + }; + union + { + __IOM uint32_t SYS_LP_CTL2; + struct + { + __IOM uint32_t CA55_STBYCTL : 1; + uint32_t : 31; + } SYS_LP_CTL2_b; + }; + __IM uint8_t RESERVED33[8]; + union + { + __IOM uint32_t SYS_LP_CTL5; + struct + { + uint32_t : 1; + __IOM uint32_t ASCLKQDENY_F : 1; + __IOM uint32_t AMCLKQDENY_F : 1; + uint32_t : 5; + __IOM uint32_t CA55SLEEP0_F : 1; + uint32_t : 1; + __IOM uint32_t CM33SLEEP_F : 1; + __IOM uint32_t CM33FPUSLEEP_F : 1; + uint32_t : 20; + } SYS_LP_CTL5_b; + }; + union + { + __IOM uint32_t SYS_LP_CTL6; + struct + { + uint32_t : 1; + __IOM uint32_t ASCLKQDENY_E : 1; + __IOM uint32_t AMCLKQDENY_E : 1; + uint32_t : 5; + __IOM uint32_t CA55SLEEP0_E : 1; + uint32_t : 1; + __IOM uint32_t CM33SLEEP_E : 1; + __IOM uint32_t CM33FPUSLEEP_E : 1; + uint32_t : 20; + } SYS_LP_CTL6_b; + }; + union + { + __IOM uint32_t SYS_LP_CTL7; + struct + { + __IOM uint32_t IM33_MASK : 1; + __IOM uint32_t IM33FPU_MASK : 1; + uint32_t : 30; + } SYS_LP_CTL7_b; + }; + __IM uint8_t RESERVED34[4]; + union + { + __IM uint32_t SYS_LP_CM33CTL0; + struct + { + __IM uint32_t SLEEPMODE : 1; + uint32_t : 3; + __IM uint32_t SLEEPDEEP : 1; + uint32_t : 4; + __IM uint32_t SYSRESETREQ : 1; + uint32_t : 22; + } SYS_LP_CM33CTL0_b; + }; + __IM uint8_t RESERVED35[16]; + union + { + __IM uint32_t SYS_LP_CA55CK_CTL1; + struct + { + uint32_t : 1; + __IM uint32_t ASCLKQACTIVE : 1; + __IM uint32_t AMCLKQACTIVE : 1; + uint32_t : 5; + __IM uint32_t PCLKQACTIVE : 1; + __IM uint32_t ATCLKQACTIVE : 1; + __IM uint32_t GICCLKQACTIVE : 1; + __IM uint32_t PDBGCLKQACTIVE : 1; + uint32_t : 20; + } SYS_LP_CA55CK_CTL1_b; + }; + union + { + __IOM uint32_t SYS_LP_CA55CK_CTL2; + struct + { + uint32_t : 1; + __IOM uint32_t ASCLKQREQn : 1; + __IOM uint32_t AMCLKQREQn : 1; + uint32_t : 5; + __IOM uint32_t PCLKQREQn : 1; + __IOM uint32_t ATCLKQREQn : 1; + __IOM uint32_t GICCLKQAREQn : 1; + __IOM uint32_t PDBGCLKQREQn : 1; + uint32_t : 20; + } SYS_LP_CA55CK_CTL2_b; + }; + union + { + __IM uint32_t SYS_LP_CA55CK_CTL3; + struct + { + __IM uint32_t CA55_COREINSTRRUN0 : 1; + __IM uint32_t ASCLKQACCEPTn : 1; + __IM uint32_t AMCLKQACCEPTn : 1; + uint32_t : 5; + __IM uint32_t PCLKQACCEPTn : 1; + __IM uint32_t ATCLKQACCEPTn : 1; + __IM uint32_t GICCLKQACCEPTn : 1; + __IM uint32_t PDBGCLKQACCEPTn : 1; + uint32_t : 5; + __IM uint32_t ASCLKQDENY : 1; + __IM uint32_t AMCLKQDENY : 1; + uint32_t : 5; + __IM uint32_t PCLKQDENY : 1; + __IM uint32_t ATCLKQDENY : 1; + __IM uint32_t GICCLKQDENY : 1; + __IM uint32_t PDBGCLKQDENY : 1; + uint32_t : 4; + } SYS_LP_CA55CK_CTL3_b; + }; + __IM uint8_t RESERVED36[16]; + union + { + __IM uint32_t SYS_LP_CM33FPUCTL0; + struct + { + __IM uint32_t SLEEPMODE : 1; + uint32_t : 3; + __IM uint32_t SLEEPDEEP : 1; + uint32_t : 4; + __IM uint32_t SYSRESETREQ : 1; + uint32_t : 22; + } SYS_LP_CM33FPUCTL0_b; + }; + __IM uint8_t RESERVED37[8]; + union + { + __IOM uint32_t SYS_PD_ISO_CTRL; + struct + { + __IOM uint32_t PD_ISOVCC_ISOEN : 1; + uint32_t : 31; + } SYS_PD_ISO_CTRL_b; + }; + __IM uint8_t RESERVED38[4]; + union + { + __IOM uint32_t PWRDN_DDRPHY_CTRL; + struct + { + __IOM uint32_t DDRPHY_CTRL1_EN : 1; + __IOM uint32_t DDRPHY_CTRL1 : 1; + uint32_t : 2; + __IOM uint32_t DDRPHY_CTRL2_EN : 1; + __IOM uint32_t DDRPHY_CTRL2 : 1; + uint32_t : 2; + __IOM uint32_t DDRPHY_CTRL3_EN : 1; + __IOM uint32_t DDRPHY_CTRL3 : 1; + uint32_t : 22; + } PWRDN_DDRPHY_CTRL_b; + }; + union + { + __IOM uint32_t ISO_IOBUF_SE18_CTRL; + struct + { + __IOM uint32_t ISO_IOBUF_SE18 : 1; + uint32_t : 31; + } ISO_IOBUF_SE18_CTRL_b; + }; + union + { + __IOM uint32_t SYS_USB_PWRRDY; + struct + { + __IOM uint32_t PWRRDY_N : 1; + uint32_t : 31; + } SYS_USB_PWRRDY_b; + }; + union + { + __IOM uint32_t SYS_PCIE_RST_RSM_B; + struct + { + __IOM uint32_t PCIE_RST_RSM_B : 1; + uint32_t : 31; + } SYS_PCIE_RST_RSM_B_b; + }; + __IM uint8_t RESERVED39[136]; + union + { + __IOM uint32_t SYS_GPREG_0; + struct + { + __IOM uint32_t GPREG0 : 32; + } SYS_GPREG_0_b; + }; + union + { + __IOM uint32_t SYS_GPREG_1; + struct + { + __IOM uint32_t GPREG1 : 32; + } SYS_GPREG_1_b; + }; + union + { + __IOM uint32_t SYS_GPREG_2; + struct + { + __IOM uint32_t GPREG2 : 32; + } SYS_GPREG_2_b; + }; + union + { + __IOM uint32_t SYS_GPREG_3; + struct + { + __IOM uint32_t GPREG3 : 32; + } SYS_GPREG_3_b; + }; + __IM uint8_t RESERVED40[16]; + union + { + __IOM uint32_t SYS_IPCONT_SEL_SPI_OCTA; + struct + { + __IOM uint32_t SEL_SPI_OCTA : 1; + uint32_t : 31; + } SYS_IPCONT_SEL_SPI_OCTA_b; + }; + union + { + __IOM uint32_t SYS_IPCONT_IDAUZERONS; + struct + { + __IOM uint32_t IDAUZERONS : 1; + uint32_t : 31; + } SYS_IPCONT_IDAUZERONS_b; + }; + union + { + __IOM uint32_t SYS_IPCONT_IDAUZERONS_FPU; + struct + { + __IOM uint32_t IDAUZERONS_FPU : 1; + uint32_t : 31; + } SYS_IPCONT_IDAUZERONS_FPU_b; + }; +} R_SYSC_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_SYSC_BASE 0x41020000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_SYSC ((R_SYSC_Type *) R_SYSC_BASE) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/tsu_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/tsu_iodefine.h new file mode 100644 index 00000000..d2e2ebef --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/tsu_iodefine.h @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : tsu_iodefine.h + * Version : 1.00 + * Description : IO define file for tsu. + *********************************************************************************************************************/ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef TSU_IODEFINE_H +#define TSU_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t TSU_SM; + struct + { + __IOM uint32_t EN : 1; + __IOM uint32_t OE : 1; + uint32_t : 30; + } TSU_SM_b; + }; + __IM uint8_t RESERVED[20]; + union + { + __IM uint32_t OTPTSUTRIM0_REG; + struct + { + __IM uint32_t OTPTSUTRIM0 : 12; + uint32_t : 20; + } OTPTSUTRIM0_REG_b; + }; + union + { + __IM uint32_t OTPTSUTRIM1_REG; + struct + { + __IM uint32_t OTPTSUTRIM1 : 12; + uint32_t : 20; + } OTPTSUTRIM1_REG_b; + }; +} R_TSU_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_TSU_BASE 0x40059000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_TSU ((R_TSU_Type *) R_TSU_BASE) + +#endif /* TSU_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/tzc_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/tzc_iodefine.h new file mode 100644 index 00000000..b01b4b29 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/tzc_iodefine.h @@ -0,0 +1,909 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : tzc_iodefine.h + * Version : 1.00 + * Description : IO define file for tzc. + *********************************************************************************************************************/ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef TZC400_IODEFINE_H +#define TZC400_IODEFINE_H + +typedef struct +{ + union + { + __IM uint32_t BUILD_CONFIG; + struct + { + __IM uint32_t NOR : 5; + uint32_t : 3; + __IM uint32_t ADDRW : 6; + uint32_t : 10; + __IM uint32_t NOF : 2; + uint32_t : 6; + } BUILD_CONFIG_b; + }; + union + { + __IOM uint32_t ACTION; + struct + { + __IOM uint32_t RV : 2; + uint32_t : 30; + } ACTION_b; + }; + union + { + __IOM uint32_t GATE_KEEPER; + struct + { + __IOM uint32_t OR : 4; + uint32_t : 12; + __IOM uint32_t OS : 4; + uint32_t : 12; + } GATE_KEEPER_b; + }; + union + { + __IOM uint32_t SPECULATION_CTRL; + struct + { + __IOM uint32_t RSD : 1; + __IOM uint32_t WSD : 1; + uint32_t : 30; + } SPECULATION_CTRL_b; + }; + union + { + __IM uint32_t INT_STATUS; + struct + { + __IM uint32_t STS : 4; + uint32_t : 4; + __IM uint32_t OVERRUN : 4; + uint32_t : 4; + __IM uint32_t OVERLAP : 4; + uint32_t : 12; + } INT_STATUS_b; + }; + union + { + __OM uint32_t INT_CLEAR; + struct + { + __OM uint32_t CLEAR : 4; + uint32_t : 28; + } INT_CLEAR_b; + }; + __IM uint8_t RESERVED[8]; + union + { + __IM uint32_t FAIL_ADDRESS_LOW_0; + struct + { + __IM uint32_t ASL : 32; + } FAIL_ADDRESS_LOW_0_b; + }; + union + { + __IM uint32_t FAIL_ADDRESS_HIGH_0; + struct + { + __IM uint32_t ASH : 1; + uint32_t : 31; + } FAIL_ADDRESS_HIGH_0_b; + }; + union + { + __IM uint32_t FAIL_CONTROL_0; + struct + { + uint32_t : 20; + __IM uint32_t PL : 1; + __IM uint32_t NS : 1; + uint32_t : 2; + __IM uint32_t DC : 1; + uint32_t : 7; + } FAIL_CONTROL_0_b; + }; + union + { + __IM uint32_t FAIL_ID_0; + struct + { + __IM uint32_t ID : 1; + uint32_t : 23; + __IM uint32_t VNET : 4; + uint32_t : 4; + } FAIL_ID_0_b; + }; + union + { + __IM uint32_t FAIL_ADDRESS_LOW_1; + struct + { + __IM uint32_t ASL : 32; + } FAIL_ADDRESS_LOW_1_b; + }; + union + { + __IM uint32_t FAIL_ADDRESS_HIGH_1; + struct + { + __IM uint32_t ASH : 1; + uint32_t : 31; + } FAIL_ADDRESS_HIGH_1_b; + }; + union + { + __IM uint32_t FAIL_CONTROL_1; + struct + { + uint32_t : 20; + __IM uint32_t PL : 1; + __IM uint32_t NS : 1; + uint32_t : 2; + __IM uint32_t DC : 1; + uint32_t : 7; + } FAIL_CONTROL_1_b; + }; + union + { + __IM uint32_t FAIL_ID_1; + struct + { + __IM uint32_t ID : 1; + uint32_t : 23; + __IM uint32_t VNET : 4; + uint32_t : 4; + } FAIL_ID_1_b; + }; + union + { + __IM uint32_t FAIL_ADDRESS_LOW_2; + struct + { + __IM uint32_t ASL : 32; + } FAIL_ADDRESS_LOW_2_b; + }; + union + { + __IM uint32_t FAIL_ADDRESS_HIGH_2; + struct + { + __IM uint32_t ASH : 1; + uint32_t : 31; + } FAIL_ADDRESS_HIGH_2_b; + }; + union + { + __IM uint32_t FAIL_CONTROL_2; + struct + { + uint32_t : 20; + __IM uint32_t PL : 1; + __IM uint32_t NS : 1; + uint32_t : 2; + __IM uint32_t DC : 1; + uint32_t : 7; + } FAIL_CONTROL_2_b; + }; + union + { + __IM uint32_t FAIL_ID_2; + struct + { + __IM uint32_t ID : 1; + uint32_t : 23; + __IM uint32_t VNET : 4; + uint32_t : 4; + } FAIL_ID_2_b; + }; + union + { + __IM uint32_t FAIL_ADDRESS_LOW_3; + struct + { + __IM uint32_t ASL : 32; + } FAIL_ADDRESS_LOW_3_b; + }; + union + { + __IM uint32_t FAIL_ADDRESS_HIGH_3; + struct + { + __IM uint32_t ASH : 1; + uint32_t : 31; + } FAIL_ADDRESS_HIGH_3_b; + }; + union + { + __IM uint32_t FAIL_CONTROL_3; + struct + { + uint32_t : 20; + __IM uint32_t PL : 1; + __IM uint32_t NS : 1; + uint32_t : 2; + __IM uint32_t DC : 1; + uint32_t : 7; + } FAIL_CONTROL_3_b; + }; + union + { + __IM uint32_t FAIL_ID_3; + struct + { + __IM uint32_t ID : 1; + uint32_t : 23; + __IM uint32_t VNET : 4; + uint32_t : 4; + } FAIL_ID_3_b; + }; + __IM uint8_t RESERVED1[160]; + union + { + __IM uint32_t REGION_BASE_LOW_0; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_0_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_0; + struct + { + __IM uint32_t BAH : 1; + uint32_t : 31; + } REGION_BASE_HIGH_0_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_0; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_0_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_0; + struct + { + __IM uint32_t TAH : 1; + uint32_t : 31; + } REGION_TOP_HIGH_0_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_0; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_0_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_0; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_0_b; + }; + __IM uint8_t RESERVED2[8]; + union + { + __IM uint32_t REGION_BASE_LOW_1; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_1_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_1; + struct + { + __IM uint32_t BAH : 2; + uint32_t : 30; + } REGION_BASE_HIGH_1_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_1; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_1_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_1; + struct + { + __IM uint32_t TAH : 2; + uint32_t : 30; + } REGION_TOP_HIGH_1_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_1; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_1_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_1; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_1_b; + }; + __IM uint8_t RESERVED3[8]; + union + { + __IM uint32_t REGION_BASE_LOW_2; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_2_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_2; + struct + { + __IM uint32_t BAH : 3; + uint32_t : 29; + } REGION_BASE_HIGH_2_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_2; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_2_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_2; + struct + { + __IM uint32_t TAH : 3; + uint32_t : 29; + } REGION_TOP_HIGH_2_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_2; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_2_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_2; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_2_b; + }; + __IM uint8_t RESERVED4[8]; + union + { + __IM uint32_t REGION_BASE_LOW_3; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_3_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_3; + struct + { + __IM uint32_t BAH : 4; + uint32_t : 28; + } REGION_BASE_HIGH_3_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_3; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_3_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_3; + struct + { + __IM uint32_t TAH : 4; + uint32_t : 28; + } REGION_TOP_HIGH_3_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_3; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_3_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_3; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_3_b; + }; + __IM uint8_t RESERVED5[8]; + union + { + __IM uint32_t REGION_BASE_LOW_4; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_4_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_4; + struct + { + __IM uint32_t BAH : 5; + uint32_t : 27; + } REGION_BASE_HIGH_4_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_4; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_4_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_4; + struct + { + __IM uint32_t TAH : 5; + uint32_t : 27; + } REGION_TOP_HIGH_4_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_4; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_4_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_4; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_4_b; + }; + __IM uint8_t RESERVED6[8]; + union + { + __IM uint32_t REGION_BASE_LOW_5; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_5_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_5; + struct + { + __IM uint32_t BAH : 6; + uint32_t : 26; + } REGION_BASE_HIGH_5_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_5; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_5_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_5; + struct + { + __IM uint32_t TAH : 6; + uint32_t : 26; + } REGION_TOP_HIGH_5_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_5; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_5_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_5; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_5_b; + }; + __IM uint8_t RESERVED7[8]; + union + { + __IM uint32_t REGION_BASE_LOW_6; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_6_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_6; + struct + { + __IM uint32_t BAH : 7; + uint32_t : 25; + } REGION_BASE_HIGH_6_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_6; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_6_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_6; + struct + { + __IM uint32_t TAH : 7; + uint32_t : 25; + } REGION_TOP_HIGH_6_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_6; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_6_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_6; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_6_b; + }; + __IM uint8_t RESERVED8[8]; + union + { + __IM uint32_t REGION_BASE_LOW_7; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_7_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_7; + struct + { + __IM uint32_t BAH : 8; + uint32_t : 24; + } REGION_BASE_HIGH_7_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_7; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_7_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_7; + struct + { + __IM uint32_t TAH : 8; + uint32_t : 24; + } REGION_TOP_HIGH_7_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_7; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_7_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_7; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_7_b; + }; + __IM uint8_t RESERVED9[8]; + union + { + __IM uint32_t REGION_BASE_LOW_8; + struct + { + uint32_t : 12; + __IM uint32_t BAL : 20; + } REGION_BASE_LOW_8_b; + }; + union + { + __IM uint32_t REGION_BASE_HIGH_8; + struct + { + __IM uint32_t BAH : 9; + uint32_t : 23; + } REGION_BASE_HIGH_8_b; + }; + union + { + __IM uint32_t REGION_TOP_LOW_8; + struct + { + uint32_t : 12; + __IM uint32_t TAL : 20; + } REGION_TOP_LOW_8_b; + }; + union + { + __IM uint32_t REGION_TOP_HIGH_8; + struct + { + __IM uint32_t TAH : 9; + uint32_t : 23; + } REGION_TOP_HIGH_8_b; + }; + union + { + __IOM uint32_t REGION_ATTRIBUTES_8; + struct + { + __IOM uint32_t FE : 4; + uint32_t : 26; + __IOM uint32_t SRE : 1; + __IOM uint32_t SWE : 1; + } REGION_ATTRIBUTES_8_b; + }; + union + { + __IOM uint32_t REGION_ID_ACCESS_8; + struct + { + __IOM uint32_t NRE : 16; + __IOM uint32_t NWE : 16; + } REGION_ID_ACCESS_8_b; + }; + __IM uint8_t RESERVED10[3512]; + union + { + __IM uint32_t PID4; + struct + { + __IM uint32_t JEP106 : 4; + __IM uint32_t CNT4KB : 4; + uint32_t : 24; + } PID4_b; + }; + union + { + __IM uint32_t PID5; + struct + { + __IM uint32_t JEP106 : 4; + __IM uint32_t CNT4KB : 4; + uint32_t : 24; + } PID5_b; + }; + union + { + __IM uint32_t PID6; + struct + { + __IM uint32_t JEP106 : 4; + __IM uint32_t CNT4KB : 4; + uint32_t : 24; + } PID6_b; + }; + union + { + __IM uint32_t PID7; + struct + { + __IM uint32_t JEP106 : 4; + __IM uint32_t CNT4KB : 4; + uint32_t : 24; + } PID7_b; + }; + union + { + __IM uint32_t PID0; + struct + { + __IM uint32_t JEP106 : 4; + __IM uint32_t CNT4KB : 4; + uint32_t : 24; + } PID0_b; + }; + union + { + __IM uint32_t PID1; + struct + { + __IM uint32_t JEP106 : 4; + __IM uint32_t CNT4KB : 4; + uint32_t : 24; + } PID1_b; + }; + union + { + __IM uint32_t PID2; + struct + { + __IM uint32_t JEP106 : 4; + __IM uint32_t CNT4KB : 4; + uint32_t : 24; + } PID2_b; + }; + union + { + __IM uint32_t PID3; + struct + { + __IM uint32_t JEP106 : 4; + __IM uint32_t CNT4KB : 4; + uint32_t : 24; + } PID3_b; + }; + union + { + __IM uint32_t CID0; + struct + { + __IM uint32_t CPI0 : 8; + uint32_t : 24; + } CID0_b; + }; + union + { + __IM uint32_t CID1; + struct + { + __IM uint32_t CPI1 : 8; + uint32_t : 24; + } CID1_b; + }; + union + { + __IM uint32_t CID2; + struct + { + __IM uint32_t CPI2 : 8; + uint32_t : 24; + } CID2_b; + }; + union + { + __IM uint32_t CID3; + struct + { + __IM uint32_t CPI3 : 8; + uint32_t : 24; + } CID3_b; + }; +} R_TZC400_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +#define R_TZC_SRAM_ACPU0_BASE 0x41200000 +#define R_TZC_SRAM_ACPU1_BASE 0x41210000 +#define R_TZC_SRAM_MCPU0_BASE 0x41230000 +#define R_TZC_SRAM_MCPU1_BASE 0x41240000 +#define R_TZC_XSPI_BASE 0x41250000 +#define R_TZC_DDR_BASE 0x41260000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_TZC_SRAM_ACPU0 ((R_TZC400_Type *) R_TZC_SRAM_ACPU0_BASE) +#define R_TZC_SRAM_ACPU1 ((R_TZC400_Type *) R_TZC_SRAM_ACPU1_BASE) +#define R_TZC_SRAM_MCPU0 ((R_TZC400_Type *) R_TZC_SRAM_MCPU0_BASE) +#define R_TZC_SRAM_MCPU1 ((R_TZC400_Type *) R_TZC_SRAM_MCPU1_BASE) +#define R_TZC_XSPI ((R_TZC400_Type *) R_TZC_XSPI_BASE) +#define R_TZC_DDR ((R_TZC400_Type *) R_TZC_DDR_BASE) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/wdt_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/wdt_iodefine.h new file mode 100644 index 00000000..d360c529 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/wdt_iodefine.h @@ -0,0 +1,120 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : wdt_iodefine.h + * Version : 1.00 + * Description : IO define file for wdt. + *********************************************************************************************************************/ + +/* ================================================================================================================= */ +/* ================ Device Specific Cluster Section ====== */ +/* ================================================================================================================= */ + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Section ====== */ +/* ================================================================================================================= */ + +#ifndef WDT_IODEFINE_H +#define WDT_IODEFINE_H + +typedef struct +{ + union + { + __IOM uint32_t WDTCNT; + struct + { + __IOM uint32_t WDTEN : 1; + uint32_t : 31; + } WDTCNT_b; + }; + union + { + __IOM uint32_t WDTSET; + struct + { + uint32_t : 20; + __IOM uint32_t WDTTIME : 12; + } WDTSET_b; + }; + union + { + __IOM uint32_t WDTTIM; + struct + { + __IOM uint32_t CRTTIME : 32; + } WDTTIM_b; + }; + union + { + __IOM uint32_t WDTINT; + struct + { + __IOM uint32_t INTDISP : 1; + uint32_t : 31; + } WDTINT_b; + }; + union + { + __IOM uint32_t PECR; + struct + { + __IOM uint32_t PECR : 32; + } PECR_b; + }; + union + { + __IOM uint32_t PEEN; + struct + { + __IOM uint32_t PEEN : 1; + uint32_t : 31; + } PEEN_b; + }; + union + { + __IOM uint32_t PESR; + struct + { + __IOM uint32_t PESR : 32; + } PESR_b; + }; + union + { + __IOM uint32_t PEER; + struct + { + __IOM uint32_t PEER : 32; + } PEER_b; + }; + union + { + __IOM uint32_t PEPO; + struct + { + __IOM uint32_t PEPO : 32; + } PEPO_b; + }; +} R_WDT0_Type; + +/* ================================================================================================================= */ +/* ================ Device Specific Peripheral Address Map ====== */ +/* ================================================================================================================= */ + +#define R_WDT0_BASE 0x42800800 +#define R_WDT1_BASE 0x42800400 +#define R_WDT2_BASE 0x42800000 + +/* ================================================================================================================= */ +/* ================ Peripheral declaration ====== */ +/* ================================================================================================================= */ + +#define R_WDT0 ((R_WDT0_Type *) R_WDT0_BASE) +#define R_WDT1 ((R_WDT0_Type *) R_WDT1_BASE) +#define R_WDT2 ((R_WDT0_Type *) R_WDT2_BASE) + +#endif /* WDT_IODEFINE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/xspi_iodefine.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/xspi_iodefine.h new file mode 100644 index 00000000..481ee438 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/xspi_iodefine.h @@ -0,0 +1,485 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : xspi_iodefine.h + * Version : 1.00 + * Description : IO define file for xspi. + *********************************************************************************************************************/ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#ifndef XSPI_IODEFINE_H +#define XSPI_IODEFINE_H + +/** + * @brief R_XSPI0_CSa [CSa] (xSPI Command Map Configuration Register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; + struct + { + __IOM uint32_t FFMT : 2; + __IOM uint32_t ADDSIZE : 2; + __IOM uint32_t WPBSTMD : 1; + __IOM uint32_t ARYAMD : 1; + uint32_t : 10; + __IOM uint32_t ADDRPEN : 8; + __IOM uint32_t ADDRPCD : 8; + } CMCFG0_b; + }; + union + { + __IOM uint32_t CMCFG1; + struct + { + __IOM uint32_t RDCMD : 16; + __IOM uint32_t RDLATE : 5; + uint32_t : 11; + } CMCFG1_b; + }; + union + { + __IOM uint32_t CMCFG2; + struct + { + __IOM uint32_t WRCMD : 16; + __IOM uint32_t WRLATE : 5; + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CSa_Type; + +/** + * @brief R_XSPI0_BUF [BUF] (xSPI Command Manual Buf [0..3]) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; + struct + { + __IOM uint32_t CMDSIZE : 2; + __IOM uint32_t ADDSIZE : 3; + __IOM uint32_t DATASIZE : 4; + __IOM uint32_t LATE : 5; + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; + __IOM uint32_t CMD : 16; + } CDT_b; + }; + union + { + __IOM uint32_t CDA; + struct + { + __IOM uint32_t ADD : 32; + } CDA_b; + }; + union + { + __IOM uint32_t CDD0; + struct + { + __IOM uint32_t DATA : 32; + } CDD0_b; + }; + union + { + __IOM uint32_t CDD1; + struct + { + __IOM uint32_t DATA : 32; + } CDD1_b; + }; +} R_XSPI0_BUF_Type; + +/** + * @brief R_XSPI0_CSb [CSb] (xSPI Command Calibration Control register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; + struct + { + __IOM uint32_t CAEN : 1; + __IOM uint32_t CANOWR : 1; + uint32_t : 6; + __IOM uint32_t CAITV : 5; + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; + uint32_t : 3; + } CCCTL0_b; + }; + union + { + __IOM uint32_t CCCTL1; + struct + { + __IOM uint32_t CACMDSIZE : 2; + __IOM uint32_t CAADDSIZE : 3; + __IOM uint32_t CADATASIZE : 4; + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; + uint32_t : 3; + } CCCTL1_b; + }; + union + { + __IOM uint32_t CCCTL2; + struct + { + __IOM uint32_t CAWRCMD : 16; + __IOM uint32_t CARDCMD : 16; + } CCCTL2_b; + }; + union + { + __IOM uint32_t CCCTL3; + struct + { + __IOM uint32_t CAADD : 32; + } CCCTL3_b; + }; + union + { + __IOM uint32_t CCCTL4; + struct + { + __IOM uint32_t CADATA : 32; + } CCCTL4_b; + }; + union + { + __IOM uint32_t CCCTL5; + struct + { + __IOM uint32_t CADATA : 32; + } CCCTL5_b; + }; + union + { + __IOM uint32_t CCCTL6; + struct + { + __IOM uint32_t CADATA : 32; + } CCCTL6_b; + }; + union + { + __IOM uint32_t CCCTL7; + struct + { + __IOM uint32_t CADATA : 32; + } CCCTL7_b; + }; +} R_XSPI0_CSb_Type; + +typedef struct +{ + union + { + __IOM uint32_t WRAPCFG; + struct + { + __IOM uint32_t CKSFTCS0 : 5; + uint32_t : 3; + __IOM uint32_t DSSFTCS0 : 5; + uint32_t : 3; + __IOM uint32_t CKSFTCS1 : 5; + uint32_t : 3; + __IOM uint32_t DSSFTCS1 : 5; + uint32_t : 3; + } WRAPCFG_b; + }; + union + { + __IOM uint32_t COMCFG; + struct + { + uint32_t : 16; + __IOM uint32_t OEASTEX : 1; + __IOM uint32_t OENEGEX : 1; + uint32_t : 14; + } COMCFG_b; + }; + union + { + __IOM uint32_t BMCFG; + struct + { + __IOM uint32_t WRMD : 1; + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; + __IOM uint32_t MWRSIZE : 8; + __IOM uint32_t PREEN : 1; + uint32_t : 7; + __IOM uint32_t CMBTIM : 8; + } BMCFG_b; + }; + __IM uint32_t RESERVED1; + __IOM R_XSPI0_CSa_Type CSa[2]; + __IM uint32_t RESERVED2[8]; + union + { + __IOM uint32_t LIOCFGCS[2]; + struct + { + __IOM uint32_t PRTMD : 10; + __IOM uint32_t LATEMD : 1; + __IOM uint32_t WRMSKMD : 1; + uint32_t : 4; + __IOM uint32_t CSMIN : 4; + __IOM uint32_t CSASTEX : 1; + __IOM uint32_t CSNEGEX : 1; + __IOM uint32_t SDRDRV : 1; + __IOM uint32_t SDRSMPMD : 1; + __IOM uint32_t SDRSMPSFT : 4; + __IOM uint32_t DDRSMPEX : 4; + } LIOCFGCS_b[2]; + }; + __IM uint32_t RESERVED3[2]; + union + { + __IOM uint32_t BMCTL0; + struct + { + __IOM uint32_t CS0ACC : 2; + __IOM uint32_t CS1ACC : 2; + uint32_t : 28; + } BMCTL0_b; + }; + union + { + __OM uint32_t BMCTL1; + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSH : 1; + uint32_t : 1; + __OM uint32_t PBUFCLR : 1; + uint32_t : 21; + } BMCTL1_b; + }; + union + { + __IOM uint32_t CMCTL; + struct + { + __IOM uint32_t XIPENCODE : 8; + __IOM uint32_t XIPEXCODE : 8; + __IOM uint32_t XIPEN : 1; + uint32_t : 15; + } CMCTL_b; + }; + __IM uint32_t RESERVED4; + union + { + __IOM uint32_t CDCTL0; + struct + { + __IOM uint32_t TRREQ : 1; + __IOM uint32_t PERMD : 1; + uint32_t : 1; + __IOM uint32_t CSSEL : 1; + __IOM uint32_t TRNUM : 2; + uint32_t : 10; + __IOM uint32_t PERITV : 5; + uint32_t : 3; + __IOM uint32_t PERREP : 4; + uint32_t : 4; + } CDCTL0_b; + }; + union + { + __IOM uint32_t CDCTL1; + struct + { + __IOM uint32_t PEREXP : 32; + } CDCTL1_b; + }; + union + { + __IOM uint32_t CDCTL2; + struct + { + __IOM uint32_t PERMSK : 32; + } CDCTL2_b; + }; + __IM uint32_t RESERVED5; + __IOM R_XSPI0_BUF_Type BUF[4]; + __IM uint32_t RESERVED6[16]; + union + { + __IOM uint32_t LPCTL0; + struct + { + __IOM uint32_t PATREQ : 1; + uint32_t : 2; + __IOM uint32_t CSSEL : 1; + __IOM uint32_t XDPIN : 2; + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; + __IOM uint32_t XD2LEN : 5; + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; + } LPCTL0_b; + }; + union + { + __IOM uint32_t LPCTL1; + struct + { + __IOM uint32_t PATREQ : 2; + uint32_t : 1; + __IOM uint32_t CSSEL : 1; + __IOM uint32_t RSTREP : 2; + uint32_t : 2; + __IOM uint32_t RSTWID : 3; + uint32_t : 1; + __IOM uint32_t RSTSU : 3; + uint32_t : 17; + } LPCTL1_b; + }; + union + { + __IOM uint32_t LIOCTL; + struct + { + __IOM uint32_t WPCS0 : 1; + __IOM uint32_t WPCS1 : 1; + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; + __IOM uint32_t RSTCS1 : 1; + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED7[9]; + __IOM R_XSPI0_CSb_Type CSb[2]; + __IM uint32_t RESERVED8[4]; + union + { + __IM uint32_t VERSTT; + struct + { + __IM uint32_t VER : 32; + } VERSTT_b; + }; + union + { + __IM uint32_t COMSTT; + struct + { + __IM uint32_t MEMACC : 1; + uint32_t : 3; + __IM uint32_t PBUFNE : 1; + uint32_t : 1; + __IM uint32_t WRBUFNE : 1; + uint32_t : 25; + } COMSTT_b; + }; + union + { + __IM uint32_t CASTTCS[2]; + struct + { + __IM uint32_t CASUC : 32; + } CASTTCS_b[2]; + }; + union + { + __IM uint32_t INTS; + struct + { + __IM uint32_t CMDCMP : 1; + __IM uint32_t PATCMP : 1; + __IM uint32_t INICMP : 1; + __IM uint32_t PERTO : 1; + __IM uint32_t DSTOCS0 : 1; + __IM uint32_t DSTOCS1 : 1; + uint32_t : 14; + __IM uint32_t BUSERR : 1; + uint32_t : 7; + __IM uint32_t CAFAILCS0 : 1; + __IM uint32_t CAFAILCS1 : 1; + __IM uint32_t CASUCCS0 : 1; + __IM uint32_t CASUCCS1 : 1; + } INTS_b; + }; + union + { + __OM uint32_t INTC; + struct + { + __OM uint32_t CMDCMPC : 1; + __OM uint32_t PATCMPC : 1; + __OM uint32_t INICMPC : 1; + __OM uint32_t PERTOC : 1; + __OM uint32_t DSTOCS0C : 1; + __OM uint32_t DSTOCS1C : 1; + uint32_t : 14; + __OM uint32_t BUSERRC : 1; + uint32_t : 7; + __OM uint32_t CAFAILCS0C : 1; + __OM uint32_t CAFAILCS1C : 1; + __OM uint32_t CASUCCS0C : 1; + __OM uint32_t CASUCCS1C : 1; + } INTC_b; + }; + union + { + __IOM uint32_t INTE; + struct + { + __IOM uint32_t CMDCMPE : 1; + __IOM uint32_t PATCMPE : 1; + __IOM uint32_t INICMPE : 1; + __IOM uint32_t PERTOE : 1; + __IOM uint32_t DSTOCS0E : 1; + __IOM uint32_t DSTOCS1E : 1; + uint32_t : 14; + __IOM uint32_t BUSERRE : 1; + uint32_t : 7; + __IOM uint32_t CAFAILCS0E : 1; + __IOM uint32_t CAFAILCS1E : 1; + __IOM uint32_t CASUCCS0E : 1; + __IOM uint32_t CASUCCS1E : 1; + } INTE_b; + }; +} R_XSPI0_Type; + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define R_XSPI0_BASE 0x40060000 + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +#define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/renesas.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 00000000..2501b06b --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,81 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup RZG + * @{ + */ + +#ifndef RZG_H + #define RZG_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include "cmsis_compiler.h" + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is provided in bsp_arm_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if BSP_MCU_GROUP_RZG2L + #include "R9A07G044L.h" + #elif BSP_MCU_GROUP_RZG2UL + #include "R9A07G043U.h" + #elif BSP_MCU_GROUP_RZG3S + #include "R9A08G045S.h" + #else + #if __has_include("renesas_internal.h") + #include "renesas_internal.h" + #else + #warning "Unsupported MCU" + #endif + #endif + + #if __ARM_ARCH_7EM__ + #define RENESAS_CORTEX_M4 + #elif __ARM_ARCH_6M__ + #define RENESAS_CORTEX_M0PLUS + #elif __ARM_ARCH_8M_BASE__ + #define RENESAS_CORTEX_M23 + #elif __ARM_ARCH_8M_MAIN__ + #define RENESAS_CORTEX_M33 + #elif __ARM_ARCH_8_1M_MAIN__ + #define RENESAS_CORTEX_M85 + #else + #warning Unsupported Architecture + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* RZG_H */ + +/** @} */ /* End of group RZG */ + +/** @} */ /* End of group Renesas */ diff --git a/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/system.h b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 00000000..e7b27d2f --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system(Secure). + * Initialize the System. + */ +extern void SystemInit_S(void); + +/** + * Warm reset + * + * @param none + * @return none + * + * @brief Warm reset(Secure). + * + */ +__attribute__((naked)) extern void Warm_Reset_S(void); + +/** + * Entry function + * + * @param none + * @return none + * + * @brief Entry function for debugger(Secure). + * + */ +__attribute__((naked)) extern void Entry_Function_S(void); + +/** + * XSPI boot entry + * + * @param none + * @return none + * + * @brief Entry functon of XSPI boot mode(Secure). + * + */ +__attribute__((naked)) extern void XSPI_Boot_Entry(void); + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif /* SYSTEM_RENESAS_ARM_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_address_convert.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_address_convert.c new file mode 100644 index 00000000..e93400b5 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_address_convert.c @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_address_convert.c + * Version : 1.00 + * Description : bsp_address_convert source code + *********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_address_convert.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_PRV_ADDRESS_TABLE_END (0xFFFFFFFF) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct bsp_address_convert_table +{ + uint32_t original_address; ///< Base address of CPU Address space + uint32_t converted_address; ///< Base address of Bus-master's Address space + uint32_t size; ///< size of region (byte) +} r_bsp_address_convert_table_t; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +r_bsp_address_convert_table_t g_address_convert_table_array[] = +{ + BSP_ADDRESS_CONVERT_TABLE_BODY, + {BSP_PRV_ADDRESS_TABLE_END, BSP_PRV_ADDRESS_TABLE_END,BSP_PRV_ADDRESS_TABLE_END} +}; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Converts the cpu address specified in the argument to the bus address. + * If an address that does not exist in the external-bus is specified, it will not be converted. + * + * @param[in] original_address Address that CPU access to slave. + * + * @retval converted_address Address that Bus-master device access to slave. + **********************************************************************************************************************/ +uint32_t R_BSP_SlaveAddressConversion (uint32_t original_address) +{ + uint32_t converted_address = original_address; // Set unconverted address as initial value. + r_bsp_address_convert_table_t * p_convert_table = &g_address_convert_table_array[0]; + + for ( ; BSP_PRV_ADDRESS_TABLE_END != p_convert_table->original_address; p_convert_table++) + { + uint32_t region_base = p_convert_table->original_address; + if ((region_base <= original_address) && (original_address < (region_base + p_convert_table->size))) + { + /* find region: convert address */ + converted_address = (original_address & BSP_ADDRESS_OFFSET_MASK) | p_convert_table->converted_address; + + /* exit loop */ + break; + } + } + + return converted_address; +} diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_address_convert.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_address_convert.h new file mode 100644 index 00000000..6b68fadb --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_address_convert.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ADDRESS_CONVERT_H +#define BSP_ADDRESS_CONVERT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ + FSP_FOOTER + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.c new file mode 100644 index 00000000..cf47af66 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.c @@ -0,0 +1,957 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clocks.h" + +#if BSP_TZ_NONSECURE_BUILD + #include "bsp_guard.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of clocks is used to size the g_clock_freq array. */ +#define BSP_PRV_NUM_CLOCKS (FSP_PRIV_CLOCK_NUM) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +static void bsp_prv_clock_pre_setting(fsp_priv_clock_t clock); +static void bsp_prv_clock_post_setting(fsp_priv_clock_t clock); +void bsp_prv_clock_selector_set(fsp_priv_clock_t clock, uint32_t clock_sel); +void bsp_prv_clock_divider_set(fsp_priv_clock_t clock, uint32_t clock_div); + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* This array stores the clock frequency of each bus clock. This section of RAM should not be initialized by the C + * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime + * environment is initialized. */ +static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS] BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +/*******************************************************************************************************************//** + * Update SystemCoreClock variable based on current clock settings. + **********************************************************************************************************************/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = g_clock_freq[FSP_PRIV_CLOCK_I2CLK]; +} + +/*******************************************************************************************************************//** + * Initializes variable to store system clock frequencies. + **********************************************************************************************************************/ +#if BSP_TZ_CFG_INIT_SECURE_ONLY +void bsp_clock_freq_var_init (void) +#else +static void bsp_clock_freq_var_init (void) +#endif +{ +#if defined(BSP_CFG_CLOCK_ICLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_ICLK] = BSP_CFG_CLOCK_ICLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_I2CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_I2CLK] = BSP_CFG_CLOCK_I2CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_GCLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_GCLK] = BSP_CFG_CLOCK_GCLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_S0CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_S0CLK] = BSP_CFG_CLOCK_S0CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_SPI0CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_SPI0CLK] = BSP_CFG_CLOCK_SPI0CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_SPI1CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_SPI1CLK] = BSP_CFG_CLOCK_SPI1CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_SD0CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_SD0CLK] = BSP_CFG_CLOCK_SD0CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_SD1CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_SD1CLK] = BSP_CFG_CLOCK_SD1CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_M0CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_M0CLK] = BSP_CFG_CLOCK_M0CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_M1CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_M1CLK] = BSP_CFG_CLOCK_M1CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_M2CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_M2CLK] = BSP_CFG_CLOCK_M2CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_M3CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_M3CLK] = BSP_CFG_CLOCK_M3CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_M4CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_M4CLK] = BSP_CFG_CLOCK_M4CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_HPCLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_HPCLK] = BSP_CFG_CLOCK_HPCLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_TSUCLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_TSUCLK] = BSP_CFG_CLOCK_TSUCLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_ZTCLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_ZTCLK] = BSP_CFG_CLOCK_ZTCLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_P0CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_P0CLK] = BSP_CFG_CLOCK_P0CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_P1CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_P1CLK] = BSP_CFG_CLOCK_P1CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_P2CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_P2CLK] = BSP_CFG_CLOCK_P2CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_ATCLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_ATCLK] = BSP_CFG_CLOCK_ATCLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_OSCCLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_OSCCLK] = BSP_CFG_CLOCK_OSCCLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_I3CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_I3CLK] = BSP_CFG_CLOCK_I3CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_P3CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_P3CLK] = BSP_CFG_CLOCK_P3CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_P4CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_P4CLK] = BSP_CFG_CLOCK_P4CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_P5CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_P5CLK] = BSP_CFG_CLOCK_P5CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_SD2CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_SD2CLK] = BSP_CFG_CLOCK_SD2CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_OC0CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_OC0CLK] = BSP_CFG_CLOCK_OC0CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_OC1CLK_HZ) + g_clock_freq[FSP_PRIV_CLOCK_OC1CLK] = BSP_CFG_CLOCK_OC1CLK_HZ; +#endif +#if defined(BSP_CFG_CLOCK_OSCCLK2_HZ) + g_clock_freq[FSP_PRIV_CLOCK_OSCCLK2] = BSP_CFG_CLOCK_OSCCLK2_HZ; +#endif + + /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */ + SystemCoreClockUpdate(); +} + +/*******************************************************************************************************************//** + * Initializes system clocks. Makes no assumptions about current register settings. + **********************************************************************************************************************/ +void bsp_clock_init (void) +{ + bsp_clock_freq_var_init(); +} + +/*******************************************************************************************************************//** + * Clock frequency configuration. According to the information specified in the Clocks tab, the divider and clock selector are initialized. + **********************************************************************************************************************/ +void bsp_clock_freq_init_cfg (void) +{ +#if BSP_FEATURE_BSP_CLOCK_FREQ_INIT_CFG_SUPPORT + uint32_t setting_value = 0; + + /* Set CPG_PL1_DDIV to configure the frequency of ICLK. */ + setting_value = (uint32_t) (BSP_CFG_DIVPL1_SET_DIV << R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Pos); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk & R_CPG->CPG_CLKDIVSTATUS), 0U); + R_CPG->CPG_PL1_DDIV = + (uint32_t) (R_CPG_CPG_PL1_DDIV_DIV_PLL1SET_WEN_Msk | (R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Msk & setting_value)); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk & R_CPG->CPG_CLKDIVSTATUS), 0U); + + /* Set CPG_PL2_DDIV to configure the frequency of P0CLK. */ + setting_value = (uint32_t) (BSP_CFG_DIVPL2B_SET_DIV << R_CPG_CPG_PL2_DDIV_DIVPL2B_SET_Pos); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL2B_STS_Msk & R_CPG->CPG_CLKDIVSTATUS), 0U); + R_CPG->CPG_PL2_DDIV = + (uint32_t) (R_CPG_CPG_PL2_DDIV_DIV_PLL2_B_WEN_Msk | (R_CPG_CPG_PL2_DDIV_DIVPL2B_SET_Msk & setting_value)); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL2B_STS_Msk & R_CPG->CPG_CLKDIVSTATUS), 0U); + + /* Set CPG_PL3_DDIV to configure the frequency of P1CLK, P2CLK and P3CLK. */ + setting_value = (uint32_t) ((BSP_CFG_DIVPL3A_SET_DIV << R_CPG_CPG_PL3_DDIV_DIVPL3A_SET_Pos) | + (BSP_CFG_DIVPL3B_SET_DIV << R_CPG_CPG_PL3_DDIV_DIVPL3B_SET_Pos) | + (BSP_CFG_DIVPL3C_SET_DIV << R_CPG_CPG_PL3_DDIV_DIVPL3C_SET_Pos)); + FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVPL3A_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVPL3B_STS_Msk | + R_CPG_CPG_CLKDIVSTATUS_DIVPL3C_STS_Msk) & + R_CPG->CPG_CLKDIVSTATUS), + 0U); + R_CPG->CPG_PL3_DDIV = + (uint32_t) ((R_CPG_CPG_PL3_DDIV_DIV_PLL3_A_WEN_Msk | R_CPG_CPG_PL3_DDIV_DIV_PLL3_B_WEN_Msk | + R_CPG_CPG_PL3_DDIV_DIV_PLL3_C_WEN_Msk) | + ((R_CPG_CPG_PL3_DDIV_DIVPL3A_SET_Msk | R_CPG_CPG_PL3_DDIV_DIVPL3B_SET_Msk | + R_CPG_CPG_PL3_DDIV_DIVPL3C_SET_Msk) & + setting_value)); + FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVPL3A_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVPL3B_STS_Msk | + R_CPG_CPG_CLKDIVSTATUS_DIVPL3C_STS_Msk) & + R_CPG->CPG_CLKDIVSTATUS), + 0U); + + /* Set CPG_PL6_DDIV to configure the frequency of I2CLK and I3CLK. */ + setting_value = (uint32_t) ((BSP_CFG_DIVPL6A_SET_DIV << R_CPG_CPG_PL6_DDIV_DIVPL6A_SET_Pos) | + (BSP_CFG_DIVPL6B_SET_DIV << R_CPG_CPG_PL6_DDIV_DIVPL6B_SET_Pos)); + FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVPL6A_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVPL6B_STS_Msk) & + R_CPG->CPG_CLKDIVSTATUS), + 0U); + R_CPG->CPG_PL6_DDIV = + (uint32_t) ((R_CPG_CPG_PL6_DDIV_DIV_PLL6_A_WEN_Msk | R_CPG_CPG_PL6_DDIV_DIV_PLL6_B_WEN_Msk) | + ((R_CPG_CPG_PL6_DDIV_DIVPL6A_SET_Msk | R_CPG_CPG_PL6_DDIV_DIVPL6B_SET_Msk) & + setting_value)); + FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVPL6A_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVPL6B_STS_Msk) & + R_CPG->CPG_CLKDIVSTATUS), + 0U); + + /* Set CPG_SDHI_DDIV and CPG_SDHI_DSEL to configure the frequency of SD0CLK, SD1CLK and SD2CLK. */ + setting_value = (uint32_t) ((BSP_CFG_DIVSDHI0_SET_DIV << R_CPG_CPG_SDHI_DDIV_DIVSDHI0_SET_Pos) | + (BSP_CFG_DIVSDHI1_SET_DIV << R_CPG_CPG_SDHI_DDIV_DIVSDHI1_SET_Pos) | + (BSP_CFG_DIVSDHI2_SET_DIV << R_CPG_CPG_SDHI_DDIV_DIVSDHI2_SET_Pos)); + FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVSDHI0_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVSDHI1_STS_Msk | + R_CPG_CPG_CLKDIVSTATUS_DIVSDHI2_STS_Msk) & + R_CPG->CPG_CLKDIVSTATUS), + 0U); + R_CPG->CPG_SDHI_DDIV = + (uint32_t) ((R_CPG_CPG_SDHI_DDIV_DIVSDHI0_WEN_Msk | R_CPG_CPG_SDHI_DDIV_DIVSDHI1_WEN_Msk | + R_CPG_CPG_SDHI_DDIV_DIVSDHI2_WEN_Msk) | + ((R_CPG_CPG_SDHI_DDIV_DIVSDHI0_SET_Msk | R_CPG_CPG_SDHI_DDIV_DIVSDHI1_SET_Msk | + R_CPG_CPG_SDHI_DDIV_DIVSDHI2_SET_Msk) & + setting_value)); + FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVSDHI0_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVSDHI1_STS_Msk | + R_CPG_CPG_CLKDIVSTATUS_DIVSDHI2_STS_Msk) & + R_CPG->CPG_CLKDIVSTATUS), + 0U); + + setting_value = (uint32_t) ((BSP_CFG_SEL_SDHI0_SET_SOURCE << R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Pos) | + (BSP_CFG_SEL_SDHI1_SET_SOURCE << R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Pos) | + (BSP_CFG_SEL_SDHI2_SET_SOURCE << R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Pos)); + FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk | R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk | + R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk) & + R_CPG->CPG_CLKSELSTATUS), + 0U); + R_CPG->CPG_SDHI_DSEL = + (uint32_t) ((R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_WEN_Msk | R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_WEN_Msk | + R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_WEN_Msk) | + ((R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Msk | R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Msk | + R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Msk) & + setting_value)); + FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk | R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk | + R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk) & + R_CPG->CPG_CLKSELSTATUS), + 0U); + + /* Set CPG_PLL_DSEL to configure the frequency of S0CLK. */ + setting_value = (uint32_t) (BSP_CFG_SELPL4_SET_SOURCE << R_CPG_CPG_PLL_DSEL_SELPL4_SET_Pos); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELPL4_STS_Msk & R_CPG->CPG_CLKSELSTATUS), 0U); + R_CPG->CPG_PLL_DSEL = + (uint32_t) (R_CPG_CPG_PLL_DSEL_SELPL4_WEN_Msk | (R_CPG_CPG_PLL_DSEL_SELPL4_SET_Msk & setting_value)); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELPL4_STS_Msk & R_CPG->CPG_CLKSELSTATUS), 0U); +#endif +} + +/*******************************************************************************************************************//** + * Perform any necessary processing before changing the frequency. + * + * @param[in] clock Desired clock + **********************************************************************************************************************/ +static void bsp_prv_clock_pre_setting (fsp_priv_clock_t clock) +{ + FSP_PARAMETER_NOT_USED(clock); +} + +/*******************************************************************************************************************//** + * Perform any necessary processing after changing the frequency. + * + * @param[in] clock Desired clock + **********************************************************************************************************************/ +static void bsp_prv_clock_post_setting (fsp_priv_clock_t clock) +{ + FSP_PARAMETER_NOT_USED(clock); +} + +/*******************************************************************************************************************//** + * Set the Source Clock Setting register to change the frequency. + * + * @param[in] clock Element number of the array that defines the frequency of each clock. + * @param[in] clock_sel Value to set in Source Clock Setting register. + **********************************************************************************************************************/ +void bsp_prv_clock_selector_set (fsp_priv_clock_t clock, uint32_t clock_sel) +{ + uint32_t clock_freq = g_clock_freq[clock]; + + switch (clock) + { +#if defined(BSP_CFG_SEL_SDHI0_SET_SOURCE) + + /* Source Clock setting for SDHI0. */ + case FSP_PRIV_CLOCK_SD0CLK: + { + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >> + R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Pos, + 0U); + + R_CPG->CPG_SDHI_DSEL = (uint32_t) (R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_WEN_Msk | + (R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Msk & + (clock_sel << R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Pos))); + + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >> + R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Pos, + 0U); + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_800 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ >> 1; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_500 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ / 6; + } + else + { + /* If this condition is met, prohibited value was set in the register. */ + ; + } + + break; + } +#endif /* BSP_CFG_SEL_SDHI0_SET_SOURCE */ + +#if defined(BSP_CFG_SEL_SDHI1_SET_SOURCE) + + /* Source Clock setting for SDHI1. */ + case FSP_PRIV_CLOCK_SD1CLK: + { + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >> + R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Pos, + 0U); + + R_CPG->CPG_SDHI_DSEL = (uint32_t) (R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_WEN_Msk | + (R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Msk & + (clock_sel << R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Pos))); + + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >> + R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Pos, + 0U); + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_800 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ >> 1; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_500 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ / 6; + } + else + { + /* If this condition is met, prohibited value was set in the register. */ + ; + } + + break; + } +#endif /* BSP_CFG_SEL_SDHI1_SET_SOURCE */ + +#if defined(BSP_CFG_SEL_SDHI2_SET_SOURCE) + + /* Source Clock setting for SDHI2. */ + case FSP_PRIV_CLOCK_SD2CLK: + { + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >> + R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Pos, + 0U); + + R_CPG->CPG_SDHI_DSEL = (uint32_t) (R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_WEN_Msk | + (R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Msk & + (clock_sel << R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Pos))); + + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >> + R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Pos, + 0U); + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_800 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ >> 1; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_500 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ / 6; + } + else + { + /* If this condition is met, prohibited value was set in the register. */ + ; + } + + break; + } +#endif /* BSP_CFG_SEL_SDHI2_SET_SOURCE */ + +#if defined(BSP_CFG_SELSPI_SET_SOURCE) + + /* Source Clock setting for SPI0. */ + case FSP_PRIV_CLOCK_SPI0CLK: + { + uint32_t clock_mon = (uint32_t) ((R_CPG_CPG_CLKMON_SPI_CLK3_MON_Msk & R_CPG->CPG_CLKMON_SPI) >> + R_CPG_CPG_CLKMON_SPI_CLK3_MON_Pos); + + /* If SPI_CLKX2 is supplied, the clock stops before setting the Source Clock Setting Register. */ + if (clock_mon) + { + R_CPG->CPG_CLKON_SPI = R_CPG_CPG_CLKON_SPI_CLK3_ONWEN_Msk; + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_SPI_CLK3_MON_Msk & R_CPG->CPG_CLKMON_SPI) >> + R_CPG_CPG_CLKMON_SPI_CLK3_MON_Pos, + 0U); + } + + R_CPG->CPG_SPI_SSEL = (uint32_t) (R_CPG_CPG_SPI_SSEL_SELSPI_WEN_Msk | + (R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk & + (clock_sel << R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos))); + + /* If the clock was stopped before setting the Source Clock Setting Register, the clock supply resumes. */ + if (clock_mon) + { + R_CPG->CPG_CLKON_SPI = (uint32_t) (R_CPG_CPG_CLKON_SPI_CLK3_ONWEN_Msk | + R_CPG_CPG_CLKON_SPI_CLK3_ON_Msk); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_SPI_CLK3_MON_Msk & R_CPG->CPG_CLKMON_SPI) >> + R_CPG_CPG_CLKMON_SPI_CLK3_MON_Pos, + 1U); + } + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1; + } + else + { + /* If this condition is met, clock_sel is an invalid value. */ + ; + } + + uint32_t clock_div = (uint32_t) ((R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk & R_CPG->CPG_SPI_DDIV) >> + R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos); + if (BSP_CLOCKS_SPI_DIV_32 == clock_div) + { + clock_div++; + } + + clock_freq = clock_freq >> (clock_div + 1); + + /* Changing settings for the SPI0 clock related register, SPI1 clock frequency changes at the same time. + * So it is updated the variable that stored SPI1 clock frequency. */ + g_clock_freq[FSP_PRIV_CLOCK_SPI1CLK] = clock_freq >> 1; + break; + } + + /* Source Clock setting for SPI1. */ + case FSP_PRIV_CLOCK_SPI1CLK: + { + uint32_t clock_mon = (uint32_t) ((R_CPG_CPG_CLKMON_SPI_CLK2_MON_Msk & R_CPG->CPG_CLKMON_SPI) >> + R_CPG_CPG_CLKMON_SPI_CLK2_MON_Pos); + + /* If SPI_CLK is supplied, the clock stops before setting the Source Clock Setting Register. */ + if (clock_mon) + { + R_CPG->CPG_CLKON_SPI = R_CPG_CPG_CLKON_SPI_CLK2_ONWEN_Msk; + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_SPI_CLK2_MON_Msk & R_CPG->CPG_CLKMON_SPI) >> + R_CPG_CPG_CLKMON_SPI_CLK2_MON_Pos, + 0U); + } + + R_CPG->CPG_SPI_SSEL = (uint32_t) (R_CPG_CPG_SPI_SSEL_SELSPI_WEN_Msk | + (R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk & + (clock_sel << R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos))); + + /* If the clock was stopped before setting the Source Clock Setting Register, the clock supply resumes. */ + if (clock_mon) + { + R_CPG->CPG_CLKON_SPI = (uint32_t) (R_CPG_CPG_CLKON_SPI_CLK2_ONWEN_Msk | + R_CPG_CPG_CLKON_SPI_CLK2_ON_Msk); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_SPI_CLK2_MON_Msk & R_CPG->CPG_CLKMON_SPI) >> + R_CPG_CPG_CLKMON_SPI_CLK2_MON_Pos, + 1U); + } + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1; + } + else + { + /* If this condition is met, clock_sel is an invalid value. */ + ; + } + + uint32_t clock_div = (uint32_t) ((R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk & R_CPG->CPG_SPI_DDIV) >> + R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos); + if (BSP_CLOCKS_SPI_DIV_32 == clock_div) + { + clock_div++; + } + + clock_freq = clock_freq >> (clock_div + 2); + + /* Changing settings for the SPI1 clock related register, SPI0 clock frequency changes at the same time. + * So it is updated the variable that stored SPI0 clock frequency. */ + g_clock_freq[FSP_PRIV_CLOCK_SPI0CLK] = clock_freq << 1; + break; + } +#endif /* BSP_CFG_SELSPI_SET_SOURCE */ + +#if defined(BSP_CFG_SELOCTA_SET_SOURCE) + + /* Source Clock setting for OC0. */ + case FSP_PRIV_CLOCK_OC0CLK: + { + uint32_t clock_mon = (uint32_t) ((R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >> + R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Pos); + + /* If OCTA_MCLK is supplied, the clock stops before setting the Source Clock Setting Register. */ + if (clock_mon) + { + R_CPG->CPG_CLKON_OCTA = R_CPG_CPG_CLKON_OCTA_CLK1_ONWEN_Msk; + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >> + R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Pos, + 0U); + } + + R_CPG->CPG_OCTA_SSEL = (uint32_t) (R_CPG_CPG_OCTA_SSEL_SELOCTA_WEN_Msk | + (R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk & + (clock_sel << R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos))); + + /* If the clock was stopped before setting the Source Clock Setting Register, the clock supply resumes. */ + if (clock_mon) + { + R_CPG->CPG_CLKON_OCTA = (uint32_t) (R_CPG_CPG_CLKON_OCTA_CLK1_ONWEN_Msk | + R_CPG_CPG_CLKON_OCTA_CLK1_ON_Msk); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >> + R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Pos, + 1U); + } + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1; + } + else + { + /* If this condition is met, clock_sel is an invalid value. */ + ; + } + + uint32_t clock_div = (uint32_t) ((R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk & R_CPG->CPG_OCTA_DDIV) >> + R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos); + if (BSP_CLOCKS_OCTA_DIV_32 == clock_div) + { + clock_div++; + } + + clock_freq = clock_freq >> (clock_div + 1); + + /* Changing settings for the OC0 clock related register, OC1 clock frequency changes at the same time. + * So it is updated the variable that stored OC1 clock frequency. */ + g_clock_freq[FSP_PRIV_CLOCK_OC1CLK] = clock_freq >> 1; + break; + } + + /* Source Clock setting for OC1. */ + case FSP_PRIV_CLOCK_OC1CLK: + { + uint32_t clock_mon = (uint32_t) ((R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >> + R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Pos); + + /* If OCTA_ACLK is supplied, the clock stops before setting the Source Clock Setting Register. */ + if (clock_mon) + { + R_CPG->CPG_CLKON_OCTA = R_CPG_CPG_CLKON_OCTA_CLK0_ONWEN_Msk; + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >> + R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Pos, + 0U); + } + + R_CPG->CPG_OCTA_SSEL = (uint32_t) (R_CPG_CPG_OCTA_SSEL_SELOCTA_WEN_Msk | + (R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk & + (clock_sel << R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos))); + + /* If the clock was stopped before setting the Source Clock Setting Register, the clock supply resumes. */ + if (clock_mon) + { + R_CPG->CPG_CLKON_OCTA = (uint32_t) (R_CPG_CPG_CLKON_OCTA_CLK0_ONWEN_Msk | + R_CPG_CPG_CLKON_OCTA_CLK0_ON_Msk); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >> + R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Pos, + 1U); + } + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_sel) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1; + } + else + { + /* If this condition is met, clock_sel is an invalid value. */ + ; + } + + uint32_t clock_div = (uint32_t) ((R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk & R_CPG->CPG_OCTA_DDIV) >> + R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos); + if (BSP_CLOCKS_OCTA_DIV_32 == clock_div) + { + clock_div++; + } + + clock_freq = clock_freq >> (clock_div + 2); + + /* Changing settings for the OC1 clock related register, OC0 clock frequency changes at the same time. + * So it is updated the variable that stored OC0 clock frequency. */ + g_clock_freq[FSP_PRIV_CLOCK_OC0CLK] = clock_freq << 1; + break; + } +#endif /* BSP_CFG_SELOCTA_SET_SOURCE */ + + default: + { + FSP_PARAMETER_NOT_USED(clock_sel); + break; + } + } + + g_clock_freq[clock] = clock_freq; +} + +/*******************************************************************************************************************//** + * Set the Division Ratio Setting register to change the frequency. + * + * @param[in] clock Element number of the array that defines the frequency of each clock. + * @param[in] clock_div Value to set in Division Ratio Setting register. + **********************************************************************************************************************/ +void bsp_prv_clock_divider_set (fsp_priv_clock_t clock, uint32_t clock_div) +{ + uint32_t clock_freq = g_clock_freq[clock]; + + switch (clock) + { +#if defined(BSP_CFG_DIVPL1_SET_DIV) + + /* ICLK division ratio setting. */ + case FSP_PRIV_CLOCK_ICLK: + { + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Pos, + 0U); + R_CPG->CPG_PL1_DDIV = (uint32_t) (R_CPG_CPG_PL1_DDIV_DIV_PLL1SET_WEN_Msk | + (R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Msk & + (clock_div << R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Pos))); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Pos, + 0U); + clock_freq = BSP_CFG_CLOCK_PLL1_HZ >> clock_div; + break; + } +#endif + +#if defined(BSP_CFG_DIVSPI_SET_DIV) + + /* SPI0CLK division ratio setting. */ + case FSP_PRIV_CLOCK_SPI0CLK: + { + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos, + 0U); + R_CPG->CPG_SPI_DDIV = (uint32_t) (R_CPG_CPG_SPI_DDIV_DIVSPI_WEN_Msk | + (R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk & + (clock_div << R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos))); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos, + 0U); + + uint32_t clock_source = (R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk & R_CPG->CPG_SPI_SSEL) >> + R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos; + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1; + } + else + { + /* If this condition is met, prohibited value was set in the register. */ + ; + } + + if (BSP_CLOCKS_SPI_DIV_32 == clock_div) + { + clock_div++; + } + + clock_freq = clock_freq >> clock_div; + + /* Changing settings for the SPI0 clock related register, SPI1 clock frequency changes at the same time. + * So it is updated the variable that stored SPI1 clock frequency. */ + g_clock_freq[FSP_PRIV_CLOCK_SPI1CLK] = clock_freq >> 1; + break; + } +#endif + +#if defined(BSP_CFG_DIVSPI_SET_DIV) + + /* SPI1CLK division ratio setting. */ + case FSP_PRIV_CLOCK_SPI1CLK: + { + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos, + 0U); + R_CPG->CPG_SPI_DDIV = (uint32_t) (R_CPG_CPG_SPI_DDIV_DIVSPI_WEN_Msk | + (R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk & + (clock_div << R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos))); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos, + 0U); + + uint32_t clock_source = (R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk & R_CPG->CPG_SPI_SSEL) >> + R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos; + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1; + } + else + { + /* If this condition is met, prohibited value was set in the register. */ + ; + } + + if (BSP_CLOCKS_SPI_DIV_32 == clock_div) + { + clock_div++; + } + + clock_freq = clock_freq >> (clock_div + 1); + + /* Changing settings for the SPI1 clock related register, SPI0 clock frequency changes at the same time. + * So it is updated the variable that stored SPI0 clock frequency. */ + g_clock_freq[FSP_PRIV_CLOCK_SPI0CLK] = clock_freq << 1; + break; + } +#endif + +#if defined(BSP_CFG_DIVOCTA_SET_DIV) + + /* OC0CLK division ratio setting. */ + case FSP_PRIV_CLOCK_OC0CLK: + { + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos, + 0U); + R_CPG->CPG_OCTA_DDIV = (uint32_t) (R_CPG_CPG_OCTA_DDIV_DIVOCTA_WEN_Msk | + (R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk & + (clock_div << R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos))); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos, + 0U); + + uint32_t clock_source = (R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk & R_CPG->CPG_OCTA_SSEL) >> + R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos; + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1; + } + else + { + /* If this condition is met, prohibited value was set in the register. */ + ; + } + + if (BSP_CLOCKS_OCTA_DIV_32 == clock_div) + { + clock_div++; + } + + clock_freq = clock_freq >> clock_div; + + /* Changing settings for the OC0 clock related register, OC1 clock frequency changes at the same time. + * So it is updated the variable that stored OC1 clock frequency. */ + g_clock_freq[FSP_PRIV_CLOCK_OC1CLK] = clock_freq >> 1; + break; + } +#endif + +#if defined(BSP_CFG_DIVOCTA_SET_DIV) + + /* OC1CLK division ratio setting. */ + case FSP_PRIV_CLOCK_OC1CLK: + { + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos, + 0U); + R_CPG->CPG_OCTA_DDIV = (uint32_t) (R_CPG_CPG_OCTA_DDIV_DIVOCTA_WEN_Msk | + (R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk & + (clock_div << R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos))); + FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >> + R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos, + 0U); + + uint32_t clock_source = (R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk & R_CPG->CPG_OCTA_SSEL) >> + R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos; + + if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6; + } + else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_source) + { + clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1; + } + else + { + /* If this condition is met, prohibited value was set in the register. */ + ; + } + + if (BSP_CLOCKS_OCTA_DIV_32 == clock_div) + { + clock_div++; + } + + clock_freq = clock_freq >> (clock_div + 1); + + /* Changing settings for the OC1 clock related register, OC0 clock frequency changes at the same time. + * So it is updated the variable that stored OC0 clock frequency. */ + g_clock_freq[FSP_PRIV_CLOCK_OC0CLK] = clock_freq << 1; + break; + } +#endif + + default: + { + FSP_PARAMETER_NOT_USED(clock_div); + break; + } + } + + g_clock_freq[clock] = clock_freq; +} + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the system clock frequency. + * + * @param[in] clock Element number of the array that defines the frequency of the bus clock. + * + * @retval g_clock_freq[clock] System clock frequency. + **********************************************************************************************************************/ +uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) +{ + return g_clock_freq[clock]; +} + +/*******************************************************************************************************************//** + * Set a clock frequency. + * + * @param[in] clock Element number of the array that defines the frequency of each clock. + * @param[in] clock_sel Value to set in Source Clock Setting register. + * @param[in] clock_div Value to set in Division Ratio Setting register. + **********************************************************************************************************************/ +void R_FSP_SystemClockHzSet (fsp_priv_clock_t clock, uint32_t clock_sel, uint32_t clock_div) +{ + bsp_prv_clock_pre_setting(clock); + bsp_prv_clock_selector_set(clock, clock_sel); + bsp_prv_clock_divider_set(clock, clock_div); + bsp_prv_clock_post_setting(clock); +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.h new file mode 100644 index 00000000..fcb832c2 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_clocks.h @@ -0,0 +1,464 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CLOCKS_H +#define BSP_CLOCKS_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_clock_cfg.h" +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Start clock supply + * + * @param ip fsp_ip_t enum value for the unit to which the clock is supplied. + * @param channel The channel. Use ch 0 for units without channels. Only single bit can be set. + **********************************************************************************************************************/ +#define R_BSP_MODULE_CLKON(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_CLKON_REG_ ## ip(channel) = 0x00000000U \ + | (BSP_CLKON_BIT_ ## ip(channel) << \ + 16U) \ + | (BSP_CLKON_BIT_ ## ip(channel)); \ + while ((BSP_CLKMON_REG_ ## ip(channel) & \ + BSP_CLKMON_BIT_ ## ip(channel)) == 0U) \ + { /* wait */}; \ + FSP_CRITICAL_SECTION_EXIT;} + +/*********************************************************************************************************************** + * Stop clock supply + * + * @param ip fsp_ip_t enum value for the unit to stop clock. + * @param channel The channel. Use ch 0 for units without channels. Only single bit can be set. + **********************************************************************************************************************/ +#define R_BSP_MODULE_CLKOFF(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_CLKON_REG_ ## ip(channel) = 0x00000000U \ + | (BSP_CLKON_BIT_ ## ip(channel) << \ + 16U); \ + while ((BSP_CLKMON_REG_ ## ip(channel) & \ + BSP_CLKMON_BIT_ ## ip(channel)) != 0U) \ + { /* wait */}; \ + FSP_CRITICAL_SECTION_EXIT;} + +/*********************************************************************************************************************** + * Reset assertion + * + * @param ip fsp_ip_t enum value for the unit to be reset. + * @param channel The channel. Use ch 0 for units without channels. Only single bit can be set. + **********************************************************************************************************************/ +#define R_BSP_MODULE_RSTON(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_RST_REG_ ## ip(channel) = 0x00000000U \ + | (BSP_RST_BIT_ ## ip(channel) << 16U); \ + FSP_CRITICAL_SECTION_EXIT;} + +/*********************************************************************************************************************** + * Reset deassertion + * + * @param ip fsp_ip_t enum value for the unit to release from reset state. + * @param channel The channel. Use ch 0 for units without channels. Only single bit can be set. + **********************************************************************************************************************/ +#define R_BSP_MODULE_RSTOFF(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_RST_REG_ ## ip(channel) = 0x00000000U \ + | (BSP_RST_BIT_ ## ip(channel) << 16U) \ + | (BSP_RST_BIT_ ## ip(channel)); \ + while ((BSP_RSTMON_REG_ ## ip(channel) & \ + BSP_RSTMON_BIT_ ## ip(channel)) != 0U) \ + { /* wait */}; \ + FSP_CRITICAL_SECTION_EXIT;} + +/*********************************************************************************************************************** + * Definition of macros to control GTM clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#ifndef BSP_CLKON_REG_FSP_IP_GTM + #define BSP_CLKON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_CLKON_GTM) +#endif +#ifndef BSP_CLKON_BIT_FSP_IP_GTM + #define BSP_CLKON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_CLKON_GTM_CLK0_ON_Pos + (channel))) +#endif + +#ifndef BSP_CLKMON_REG_FSP_IP_GTM + #define BSP_CLKMON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_CLKMON_GTM) +#endif +#ifndef BSP_CLKMON_BIT_FSP_IP_GTM + #define BSP_CLKMON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_CLKMON_GTM_CLK0_MON_Pos + (channel))) +#endif + +#ifndef BSP_RST_REG_FSP_IP_GTM + #define BSP_RST_REG_FSP_IP_GTM(channel) (R_CPG->CPG_RST_GTM) +#endif +#ifndef BSP_RST_BIT_FSP_IP_GTM + #define BSP_RST_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_RST_GTM_UNIT0_RSTB_Pos + (channel))) +#endif + +#ifndef BSP_RSTMON_REG_FSP_IP_GTM + #define BSP_RSTMON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_RSTMON_GTM) +#endif +#ifndef BSP_RSTMON_BIT_FSP_IP_GTM + #define BSP_RSTMON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_RSTMON_GTM_RST0_MON_Pos + (channel))) +#endif + +/*********************************************************************************************************************** + * Definition of macros to control GPT clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_GPT(channel) (R_CPG->CPG_CLKON_GPT) +#define BSP_CLKON_BIT_FSP_IP_GPT(channel) (1U << (R_CPG_CPG_CLKON_GPT_CLK0_ON_Pos)) + +#define BSP_CLKMON_REG_FSP_IP_GPT(channel) (R_CPG->CPG_CLKMON_GPT) +#define BSP_CLKMON_BIT_FSP_IP_GPT(channel) (1U << (R_CPG_CPG_CLKMON_GPT_CLK0_MON_Pos)) + +#define BSP_RST_REG_FSP_IP_GPT(channel) (R_CPG->CPG_RST_GPT) +#define BSP_RST_BIT_FSP_IP_GPT(channel) (1U << (R_CPG_CPG_RST_GPT_UNIT0_RSTB_Pos)) + +#define BSP_RSTMON_REG_FSP_IP_GPT(channel) (R_CPG->CPG_RSTMON_GPT) +#define BSP_RSTMON_BIT_FSP_IP_GPT(channel) (1U << (R_CPG_CPG_RSTMON_GPT_RST0_MON_Pos)) + +/*********************************************************************************************************************** + * Definition of macros to control POEG clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_POEG(channel) (R_CPG->CPG_CLKON_POEG) +#define BSP_CLKON_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_CLKON_POEG_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_POEG(channel) (R_CPG->CPG_CLKMON_POEG) +#define BSP_CLKMON_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_CLKMON_POEG_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_POEG(channel) (R_CPG->CPG_RST_POEG) +#define BSP_RST_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_RST_POEG_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_POEG(channel) (R_CPG->CPG_RSTMON_POEG) +#define BSP_RSTMON_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_RSTMON_POEG_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control IM33 clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_IM33(channel) (R_CPG->CPG_CLKON_IM33) +#define BSP_CLKON_BIT_FSP_IP_IM33(channel) (1U << (R_CPG_CPG_CLKON_IM33_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_IM33(channel) (R_CPG->CPG_CLKMON_IM33) +#define BSP_CLKMON_BIT_FSP_IP_IM33(channel) (1U << (R_CPG_CPG_CLKMON_IM33_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_IM33(channel) (R_CPG->CPG_RST_IM33) +#define BSP_RST_BIT_FSP_IP_IM33(channel) (1U << (R_CPG_CPG_RST_IM33_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_IM33(channel) (R_CPG->CPG_RSTMON_IM33) +#define BSP_RSTMON_BIT_FSP_IP_IM33(channel) (1U << (R_CPG_CPG_RSTMON_IM33_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control SCIF clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_SCIF(channel) (R_CPG->CPG_CLKON_SCIF) +#define BSP_CLKON_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_CLKON_SCIF_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_SCIF(channel) (R_CPG->CPG_CLKMON_SCIF) +#define BSP_CLKMON_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_CLKMON_SCIF_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_SCIF(channel) (R_CPG->CPG_RST_SCIF) +#define BSP_RST_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_RST_SCIF_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_SCIF(channel) (R_CPG->CPG_RSTMON_SCIF) +#define BSP_RSTMON_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_RSTMON_SCIF_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control RIIC clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_RIIC(channel) (R_CPG->CPG_CLKON_I2C) +#define BSP_CLKON_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_CLKON_I2C_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_RIIC(channel) (R_CPG->CPG_CLKMON_I2C) +#define BSP_CLKMON_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_CLKMON_I2C_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_RIIC(channel) (R_CPG->CPG_RST_I2C) +#define BSP_RST_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_RST_I2C_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_RIIC(channel) (R_CPG->CPG_RSTMON_I2C) +#define BSP_RSTMON_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_RSTMON_I2C_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control RSPI clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_RSPI(channel) (R_CPG->CPG_CLKON_RSPI) +#define BSP_CLKON_BIT_FSP_IP_RSPI(channel) (1U << (R_CPG_CPG_CLKON_RSPI_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_RSPI(channel) (R_CPG->CPG_CLKMON_RSPI) +#define BSP_CLKMON_BIT_FSP_IP_RSPI(channel) (1U << (R_CPG_CPG_CLKMON_RSPI_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_RSPI(channel) (R_CPG->CPG_RST_RSPI) +#define BSP_RST_BIT_FSP_IP_RSPI(channel) (1U << (R_CPG_CPG_RST_RSPI_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_RSPI(channel) (R_CPG->CPG_RSTMON_RSPI) +#define BSP_RSTMON_BIT_FSP_IP_RSPI(channel) (1U << (R_CPG_CPG_RSTMON_RSPI_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control MHU clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_MHU(channel) (R_CPG->CPG_CLKON_MHU) +#define BSP_CLKON_BIT_FSP_IP_MHU(channel) (1U << (R_CPG_CPG_CLKON_MHU_CLK0_ON_Pos)) + +#define BSP_CLKMON_REG_FSP_IP_MHU(channel) (R_CPG->CPG_CLKMON_MHU) +#define BSP_CLKMON_BIT_FSP_IP_MHU(channel) (1U << (R_CPG_CPG_CLKMON_MHU_CLK0_MON_Pos)) + +#define BSP_RST_REG_FSP_IP_MHU(channel) (R_CPG->CPG_RST_MHU) +#define BSP_RST_BIT_FSP_IP_MHU(channel) (1U << (R_CPG_CPG_RST_MHU_UNIT0_RSTB_Pos)) + +#define BSP_RSTMON_REG_FSP_IP_MHU(channel) (R_CPG->CPG_RSTMON_MHU) +#define BSP_RSTMON_BIT_FSP_IP_MHU(channel) (1U << (R_CPG_CPG_RSTMON_MHU_RST0_MON_Pos)) + +/*********************************************************************************************************************** + * Definition of macros to control DMAC clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_DMAC(channel) (R_CPG->CPG_CLKON_DMAC_REG) +#define BSP_CLKON_BIT_FSP_IP_DMAC(channel) (3U << (R_CPG_CPG_CLKON_DMAC_REG_CLK0_ON_Pos)) + +#define BSP_CLKMON_REG_FSP_IP_DMAC(channel) (R_CPG->CPG_CLKMON_DMAC_REG) +#define BSP_CLKMON_BIT_FSP_IP_DMAC(channel) (3U << (R_CPG_CPG_CLKMON_DMAC_REG_CLK0_MON_Pos)) + +#define BSP_RST_REG_FSP_IP_DMAC(channel) (R_CPG->CPG_RST_DMAC) +#define BSP_RST_BIT_FSP_IP_DMAC(channel) (3U << (R_CPG_CPG_RST_DMAC_UNIT0_RSTB_Pos)) + +#define BSP_RSTMON_REG_FSP_IP_DMAC(channel) (R_CPG->CPG_RSTMON_DMAC) +#define BSP_RSTMON_BIT_FSP_IP_DMAC(channel) (3U << (R_CPG_CPG_RSTMON_DMAC_RST0_MON_Pos)) + +#define BSP_CLKON_REG_FSP_IP_DMAC_s(channel) BSP_CLKON_REG_FSP_IP_DMAC(channel) +#define BSP_CLKON_BIT_FSP_IP_DMAC_s(channel) BSP_CLKON_BIT_FSP_IP_DMAC(channel) + +#define BSP_CLKMON_REG_FSP_IP_DMAC_s(channel) BSP_CLKMON_REG_FSP_IP_DMAC(channel) +#define BSP_CLKMON_BIT_FSP_IP_DMAC_s(channel) BSP_CLKMON_BIT_FSP_IP_DMAC(channel) + +#define BSP_RST_REG_FSP_IP_DMAC_s(channel) BSP_RST_REG_FSP_IP_DMAC(channel) +#define BSP_RST_BIT_FSP_IP_DMAC_s(channel) BSP_RST_BIT_FSP_IP_DMAC(channel) + +#define BSP_RSTMON_REG_FSP_IP_DMAC_s(channel) BSP_RSTMON_REG_FSP_IP_DMAC(channel) +#define BSP_RSTMON_BIT_FSP_IP_DMAC_s(channel) BSP_RSTMON_BIT_FSP_IP_DMAC(channel) + +/*********************************************************************************************************************** + * Definition of macros to control SSI clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_SSI(channel) (R_CPG->CPG_CLKON_SSI) +#define BSP_CLKON_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_CLKON_SSI_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_SSI(channel) (R_CPG->CPG_CLKMON_SSI) +#define BSP_CLKMON_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_CLKMON_SSI_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_SSI(channel) (R_CPG->CPG_RST_SSIF) +#define BSP_RST_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_RST_SSIF_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_SSI(channel) (R_CPG->CPG_RSTMON_SSIF) +#define BSP_RSTMON_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_RSTMON_SSIF_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control CANFD clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_CANFD(channel) (R_CPG->CPG_CLKON_CANFD) +#define BSP_CLKON_BIT_FSP_IP_CANFD(channel) (1U << (R_CPG_CPG_CLKON_CANFD_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_CANFD(channel) (R_CPG->CPG_CLKMON_CANFD) +#define BSP_CLKMON_BIT_FSP_IP_CANFD(channel) (1U << (R_CPG_CPG_CLKMON_CANFD_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_CANFD(channel) (R_CPG->CPG_RST_CANFD) +#define BSP_RST_BIT_FSP_IP_CANFD(channel) (1U << (R_CPG_CPG_RST_CANFD_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_CANFD(channel) (R_CPG->CPG_RSTMON_CANFD) +#define BSP_RSTMON_BIT_FSP_IP_CANFD(channel) (1U << (R_CPG_CPG_RSTMON_CANFD_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control ADC clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_ADC(channel) (R_CPG->CPG_CLKON_ADC) +#define BSP_CLKON_BIT_FSP_IP_ADC(channel) (3U << R_CPG_CPG_CLKON_ADC_CLK0_ON_Pos) + +#define BSP_CLKMON_REG_FSP_IP_ADC(channel) (R_CPG->CPG_CLKMON_ADC) +#define BSP_CLKMON_BIT_FSP_IP_ADC(channel) (3U << R_CPG_CPG_CLKMON_ADC_CLK0_MON_Pos) + +#define BSP_RST_REG_FSP_IP_ADC(channel) (R_CPG->CPG_RST_ADC) +#define BSP_RST_BIT_FSP_IP_ADC(channel) (3U << R_CPG_CPG_RST_ADC_UNIT0_RSTB_Pos) + +#define BSP_RSTMON_REG_FSP_IP_ADC(channel) (R_CPG->CPG_RSTMON_ADC) +#define BSP_RSTMON_BIT_FSP_IP_ADC(channel) (3U << R_CPG_CPG_RSTMON_ADC_RST0_MON_Pos) + +/*********************************************************************************************************************** + * Definition of macros to control TSU clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_TSU(channel) (R_CPG->CPG_CLKON_TSU) +#define BSP_CLKON_BIT_FSP_IP_TSU(channel) (1U << (R_CPG_CPG_CLKON_TSU_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_TSU(channel) (R_CPG->CPG_CLKMON_TSU) +#define BSP_CLKMON_BIT_FSP_IP_TSU(channel) (1U << (R_CPG_CPG_CLKMON_TSU_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_TSU(channel) (R_CPG->CPG_RST_TSU) +#define BSP_RST_BIT_FSP_IP_TSU(channel) (1U << (R_CPG_CPG_RST_TSU_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_TSU(channel) (R_CPG->CPG_RSTMON_TSU) +#define BSP_RSTMON_BIT_FSP_IP_TSU(channel) (1U << (R_CPG_CPG_RSTMON_TSU_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control WDT clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_WDT(channel) (R_CPG->CPG_CLKON_WDT) +#define BSP_CLKON_BIT_FSP_IP_WDT(channel) (3U << (R_CPG_CPG_CLKON_WDT_CLK0_ON_Pos + 2U * (channel))) + +#define BSP_CLKMON_REG_FSP_IP_WDT(channel) (R_CPG->CPG_CLKMON_WDT) +#define BSP_CLKMON_BIT_FSP_IP_WDT(channel) (3U << (R_CPG_CPG_CLKMON_WDT_CLK0_MON_Pos + 2U * (channel))) + +#define BSP_RST_REG_FSP_IP_WDT(channel) (R_CPG->CPG_RST_WDT) +#define BSP_RST_BIT_FSP_IP_WDT(channel) (1U << (R_CPG_CPG_RST_WDT_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_WDT(channel) (R_CPG->CPG_RSTMON_WDT) +#define BSP_RSTMON_BIT_FSP_IP_WDT(channel) (1U << (R_CPG_CPG_RSTMON_WDT_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control SCI clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_SCI(channel) (R_CPG->CPG_CLKON_SCI) +#define BSP_CLKON_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_CLKON_SCI_CLK0_ON_Pos + (channel))) + +#define BSP_CLKMON_REG_FSP_IP_SCI(channel) (R_CPG->CPG_CLKMON_SCI) +#define BSP_CLKMON_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_CLKMON_SCI_CLK0_MON_Pos + (channel))) + +#define BSP_RST_REG_FSP_IP_SCI(channel) (R_CPG->CPG_RST_SCI) +#define BSP_RST_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_RST_SCI_UNIT0_RSTB_Pos + (channel))) + +#define BSP_RSTMON_REG_FSP_IP_SCI(channel) (R_CPG->CPG_RSTMON_SCI) +#define BSP_RSTMON_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_RSTMON_SCI_RST0_MON_Pos + (channel))) + +/*********************************************************************************************************************** + * Definition of macros to control TSU clock ON/OFF and reset ON/OFF + **********************************************************************************************************************/ +#define BSP_CLKON_REG_FSP_IP_MTU3(channel) (R_CPG->CPG_CLKON_MTU) +#define BSP_CLKON_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_CLKON_MTU_CLK0_ON_Pos)) + +#define BSP_CLKMON_REG_FSP_IP_MTU3(channel) (R_CPG->CPG_CLKMON_MTU) +#define BSP_CLKMON_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_CLKMON_MTU_CLK0_MON_Pos)) + +#define BSP_RST_REG_FSP_IP_MTU3(channel) (R_CPG->CPG_RST_MTU) +#define BSP_RST_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_RST_MTU_UNIT0_RSTB_Pos)) + +#define BSP_RSTMON_REG_FSP_IP_MTU3(channel) (R_CPG->CPG_RSTMON_MTU) +#define BSP_RSTMON_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_RSTMON_MTU_RST0_MON_Pos)) + +/* CPG_PL1_DDIV.DIVPL1_SET options. */ +#define BSP_CLOCKS_PL1_DIV_1 (0) // Divide ICLK source clock by 1 +#define BSP_CLOCKS_PL1_DIV_2 (1) // Divide ICLK source clock by 2 +#define BSP_CLOCKS_PL1_DIV_4 (2) // Divide ICLK source clock by 4 +#define BSP_CLOCKS_PL1_DIV_8 (3) // Divide ICLK source clock by 8 + +/* CPG_PL2_DDIV.DIVPL2B_SET options. */ +#define BSP_CLOCKS_PL2B_DIV_1 (0) // Divide P0CLK source clock by 1 +#define BSP_CLOCKS_PL2B_DIV_2 (1) // Divide P0CLK source clock by 2 +#define BSP_CLOCKS_PL2B_DIV_4 (2) // Divide P0CLK source clock by 4 +#define BSP_CLOCKS_PL2B_DIV_8 (3) // Divide P0CLK source clock by 8 +#define BSP_CLOCKS_PL2B_DIV_32 (4) // Divide P0CLK source clock by 32 + +/* CPG_PL3_DDIV.DIVPL3C_SET options. */ +#define BSP_CLOCKS_PL3C_DIV_1 (0) // Divide SPI0CLK source clock by 1 +#define BSP_CLOCKS_PL3C_DIV_2 (1) // Divide SPI0CLK source clock by 2 +#define BSP_CLOCKS_PL3C_DIV_4 (2) // Divide SPI0CLK source clock by 4 +#define BSP_CLOCKS_PL3C_DIV_8 (3) // Divide SPI0CLK source clock by 8 +#define BSP_CLOCKS_PL3C_DIV_32 (4) // Divide SPI0CLK source clock by 32 + +/* CPG_PL3_DDIV.DIVPL3B_SET options. */ +#define BSP_CLOCKS_PL3B_DIV_1 (0) // Divide P1CLK source clock by 1 +#define BSP_CLOCKS_PL3B_DIV_2 (1) // Divide P1CLK source clock by 2 +#define BSP_CLOCKS_PL3B_DIV_4 (2) // Divide P1CLK source clock by 4 +#define BSP_CLOCKS_PL3B_DIV_8 (3) // Divide P1CLK source clock by 8 +#define BSP_CLOCKS_PL3B_DIV_32 (4) // Divide P1CLK source clock by 32 + +/* CPG_PL3_DDIV.DIVPL3A_SET options. */ +#define BSP_CLOCKS_PL3A_DIV_1 (0) // Divide P2CLK source clock by 1 +#define BSP_CLOCKS_PL3A_DIV_2 (1) // Divide P2CLK source clock by 2 +#define BSP_CLOCKS_PL3A_DIV_4 (2) // Divide P2CLK source clock by 4 +#define BSP_CLOCKS_PL3A_DIV_8 (3) // Divide P2CLK source clock by 8 +#define BSP_CLOCKS_PL3A_DIV_32 (4) // Divide P2CLK source clock by 32 + +/* CPG_PL6_DDIV.DIVPL6B_SET options. */ +#define BSP_CLOCKS_PL6B_DIV_1 (0) // Divide I3CLK source clock by 1 +#define BSP_CLOCKS_PL6B_DIV_2 (1) // Divide I3CLK source clock by 2 +#define BSP_CLOCKS_PL6B_DIV_4 (2) // Divide I3CLK source clock by 4 +#define BSP_CLOCKS_PL6B_DIV_8 (3) // Divide I3CLK source clock by 8 +#define BSP_CLOCKS_PL6B_DIV_32 (4) // Divide I3CLK source clock by 32 + +/* CPG_PL6_DDIV.DIVPL6A_SET options. */ +#define BSP_CLOCKS_PL6A_DIV_1 (0) // Divide I2CLK source clock by 1 +#define BSP_CLOCKS_PL6A_DIV_2 (1) // Divide I2CLK source clock by 2 +#define BSP_CLOCKS_PL6A_DIV_4 (2) // Divide I2CLK source clock by 4 +#define BSP_CLOCKS_PL6A_DIV_8 (3) // Divide I2CLK source clock by 8 +#define BSP_CLOCKS_PL6A_DIV_32 (4) // Divide I2CLK source clock by 32 + +/* CPG_SDHI_DDIV.DIVSDHI2_SET options. */ +#define BSP_CLOCKS_SDHI2_DIV_1 (0) // Divide SD2CLK source clock by 1 +#define BSP_CLOCKS_SDHI2_DIV_2 (1) // Divide SD2CLK source clock by 2 + +/* CPG_SDHI_DDIV.DIVSDHI1_SET options. */ +#define BSP_CLOCKS_SDHI1_DIV_1 (0) // Divide SD1CLK source clock by 1 +#define BSP_CLOCKS_SDHI1_DIV_2 (1) // Divide SD1CLK source clock by 2 + +/* CPG_SDHI_DDIV.DIVSDHI0_SET options. */ +#define BSP_CLOCKS_SDHI0_DIV_1 (0) // Divide SD0CLK source clock by 1 +#define BSP_CLOCKS_SDHI0_DIV_2 (1) // Divide SD0CLK source clock by 2 + +/* CPG_OCTA_DDIV.DIVOCTA_SET options. */ +#define BSP_CLOCKS_OCTA_DIV_1 (0) // Divide OCCLK source clock by 1 +#define BSP_CLOCKS_OCTA_DIV_2 (1) // Divide OCCLK source clock by 2 +#define BSP_CLOCKS_OCTA_DIV_4 (2) // Divide OCCLK source clock by 4 +#define BSP_CLOCKS_OCTA_DIV_8 (3) // Divide OCCLK source clock by 8 +#define BSP_CLOCKS_OCTA_DIV_32 (4) // Divide OCCLK source clock by 32 + +/* CPG_SPI_DDIV.DIVSPI_SET options. */ +#define BSP_CLOCKS_SPI_DIV_1 (0) // Divide SPICLK source clock by 1 +#define BSP_CLOCKS_SPI_DIV_2 (1) // Divide SPICLK source clock by 2 +#define BSP_CLOCKS_SPI_DIV_4 (2) // Divide SPICLK source clock by 4 +#define BSP_CLOCKS_SPI_DIV_8 (3) // Divide SPICLK source clock by 8 +#define BSP_CLOCKS_SPI_DIV_32 (4) // Divide SPICLK source clock by 32 + +/* CPG_PLL_DSEL options. */ +#define BSP_CLOCKS_SOURCE_CLOCK_OSC_0024 (0) // Select OSC/1000 clock +#define BSP_CLOCKS_SOURCE_CLOCK_PLL4 (1) // Select PLL4 clock + +/* CPG_SDHI_DSEL options. */ +#define BSP_CLOCKS_SOURCE_CLOCK_PLL2_800 (0) // Select 800MHz +#define BSP_CLOCKS_SOURCE_CLOCK_PLL6_500 (2) // Select 500MHz +#define BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 (3) // Select 266MHz + +/* CPG_OCTA_SSEL and CPG_SPI_SSEL options. */ +#define BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 (0) // Select 400MHz +#define BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 (2) // Select 266MHz +#define BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 (3) // Select 250MHz + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp_clocks.c */ +void bsp_clock_init(void); // Used internally by BSP +void bsp_clock_freq_init_cfg(void); // Used internally by BSP + +#if BSP_TZ_CFG_INIT_SECURE_ONLY +void bsp_clock_freq_var_init(void); // Used internally by BSP + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_common.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_common.c new file mode 100644 index 00000000..4953441b --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_common.c @@ -0,0 +1,188 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #define WEAK_ERROR_ATTRIBUTE + #define WEAK_INIT_ATTRIBUTE + #pragma weak fsp_error_log = fsp_error_log_internal + #pragma weak bsp_init = bsp_init_internal +#elif defined(__GNUC__) + + #define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal"))) + + #define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal"))) +#endif + +#define FSP_SECTION_VERSION ".version" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/** Prototype of initialization function called before main. This prototype sets the weak association of this + * function to an internal example implementation. If this function is defined in the application code, the + * application code version is used. */ + +void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE; + +void bsp_init_internal(void * p_args); /// Default initialization function + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1. This + * prototype sets the weak association of this function to an internal example implementation. */ + +void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE; + +void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function + +#endif + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* BSP version structure. */ +const fsp_version_t g_bsp_version = +{ + .api_version_minor = BSP_API_VERSION_MINOR, + .api_version_major = BSP_API_VERSION_MAJOR, + .code_version_major = BSP_CODE_VERSION_MAJOR, + .code_version_minor = BSP_CODE_VERSION_MINOR +}; + +/* FSP pack version structure. */ +static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) = +{ + .minor = FSP_VERSION_MINOR, + .major = FSP_VERSION_MAJOR, + .build = FSP_VERSION_BUILD, + .patch = FSP_VERSION_PATCH +}; + +/* Public FSP version name. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_STRING; + +/* Unique FSP version ID. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_BUILD_STRING; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the BSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_BSP_VersionGet (fsp_version_t * p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + p_version->api_version_major = BSP_API_VERSION_MAJOR; + p_version->api_version_minor = BSP_API_VERSION_MINOR; + p_version->code_version_major = BSP_CODE_VERSION_MAJOR; + p_version->code_version_minor = BSP_CODE_VERSION_MINOR; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get the FSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + *p_version = g_fsp_version; + + return FSP_SUCCESS; +} + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/*******************************************************************************************************************//** + * Default error logger function, used only if fsp_error_log is not defined in the user application. + * + * @param[in] err The error code encountered. + * @param[in] file The file name in which the error code was encountered. + * @param[in] line The line number at which the error code was encountered. + **********************************************************************************************************************/ +void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line) +{ + /** Do nothing. Do not generate any 'unused' warnings. */ + FSP_PARAMETER_NOT_USED(err); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Default initialization function, used only if bsp_init is not defined in the user application. + **********************************************************************************************************************/ +void bsp_init_internal (void * p_args) +{ + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(p_args); +} + +#if defined(__ARMCC_VERSION) + +/*******************************************************************************************************************//** + * Default implementation of assert for AC6. + **********************************************************************************************************************/ +__attribute__((weak, noreturn)) +void __aeabi_assert (const char * expr, const char * file, int line) { + FSP_PARAMETER_NOT_USED(expr); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_compiler_support.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_compiler_support.h new file mode 100644 index 00000000..769bc366 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_compiler_support.h @@ -0,0 +1,92 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_COMPILER_SUPPORT_H +#define BSP_COMPILER_SUPPORT_H + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #include "arm_cmse.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) /* AC6 compiler */ + +/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load + * memory (ROM) is reserved unnecessarily. */ + #define BSP_UNINIT_SECTION_PREFIX ".bss" + #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) +#elif defined(__GNUC__) /* GCC compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_SECTION_HEAP ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) +#elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_SECTION_HEAP "HEAP" + #define BSP_DONT_REMOVE __root + #define BSP_ATTRIBUTE_STACKLESS __stackless + #define BSP_FORCE_INLINE _Pragma("inline=forced") +#endif + +#define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" +#define BSP_SECTION_SECURE_STACK BSP_UNINIT_SECTION_PREFIX ".s_stack" +#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" +#define BSP_SECTION_FIXED_SECURE_VECTORS ".fixed_secure_vectors" +#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" +#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" +#define BSP_SECTION_ID_CODE ".id_code" + +/* Compiler neutral macros. */ +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + +#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) + +#define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED + +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ +#define BSP_STACK_ALIGNMENT (8) + +/*********************************************************************************************************************** + * TrustZone definitions + **********************************************************************************************************************/ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) + #if defined(__ICCARM__) /* IAR compiler */ + #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call + #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry + #else + #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) + #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) + #endif +#else + #define BSP_CMSE_NONSECURE_CALL + #define BSP_CMSE_NONSECURE_ENTRY +#endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end of addtogroup BSP_MCU) */ + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.c new file mode 100644 index 00000000..b051783b --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.c @@ -0,0 +1,144 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_delay.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_DELAY_UNIT_CONV_S_TO_NS (1000000000) +#define BSP_DELAY_UNIT_CONV_US_TO_NS (1000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Delay for at least the specified duration in units and return. This function shouldn't be used to + * generate an accurate delay time. A running time of the function is depending on the region of memory + * where the function is excuted on and a frequency of the CPU clock. + * + * The funcion calls bsp_prv_software_delay_loop() which loops over the requested delay time. + * One loop time through bsp_prv_software_delay_loop() takes roughly 500ns. This value is based on the + * actual measured time in the condition that a frequency of the CPU clock is 200MHz and the code is + * excuted on DDR3L-1333 DRAM(133MHz). + * One loop running time of software_delay_loop() can be modified by redefining BSP_DELAY_LOOP_CYCLES. + * + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are: + * BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n + * For example:@n + * One run through bsp_prv_software_delay_loop() takes roughly 500ns. + * A delay of 100 us therefore requires 100000ns/500ns -> 200 loops. + * + * The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the + * system clock rate. + * @200MHz: ((0xFFFFFFFF loops * 500ns) = 2147 seconds. + * + * Note that requests for very large delays will be affected by rounding in the calculations and the + * actual delay achieved may be slightly off of a setting time. + * + * Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() + * function is not called at all. In this case the requested delay is too small (nanoseconds) to be + * carried out by the loop itself, and the overhead associated with executing the code to just get to this + * point has certainly satisfied the requested delay. + * + * @note This function uses SystemCoreClock and therefore requires that the BSP has already initialized the variable + * (which it does as part of the SystemInit). + * Care should be taken to ensure this remains the case if in the future this function were to be called as part + * of the BSP initialization. + **********************************************************************************************************************/ + +void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) +{ + uint32_t iclk_hz; + uint32_t cycles_requested; + uint32_t us_per_cycle; + uint32_t loops_required = 0; + uint32_t total_us = (delay * units); + uint64_t ns_64bits; + + iclk_hz = SystemCoreClock; + us_per_cycle = BSP_DELAY_UNIT_CONV_S_TO_NS / (iclk_hz / BSP_DELAY_UNIT_CONV_US_TO_NS); + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_UNIT_CONV_US_TO_NS; + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + cycles_requested = (((uint32_t) ns_64bits / us_per_cycle) * BSP_DELAY_UNIT_CONV_US_TO_NS); + loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES; + } + else + { + /* We did overflow. Try dividing down first. */ + total_us = (total_us / ((us_per_cycle * BSP_DELAY_LOOP_CYCLES) / BSP_DELAY_UNIT_CONV_US_TO_NS)); + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_UNIT_CONV_US_TO_NS; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + loops_required = (uint32_t) ns_64bits; + } + else + { + /* We still overflowed, use the max count for cycles */ + loops_required = UINT32_MAX; + } + } + + /** Only delay if the supplied parameters constitute a delay. */ + if (loops_required > (uint32_t) 0) + { + bsp_prv_software_delay_loop(loops_required); + } +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * This assembly language routine takes roughly 500ns per one loop. + * The 'naked' attribute indicates that the specified function does not need prologue/epilogue sequences + * generated by the compiler. + * @param[in] loop_cnt The number of loops to iterate. + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt) +{ + __asm volatile ("sw_delay_loop: \n" + +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) + " subs r0, #1 \n" +#elif defined(__GNUC__) + " sub r0, r0, #1 \n" +#endif + " cmp r0, #0 \n" + + " bne.n sw_delay_loop \n" + + " bx lr \n"); +} diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.h new file mode 100644 index 00000000..82554901 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_delay.h @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DELAY_H +#define BSP_DELAY_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "bsp_compiler_support.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of cycles required per software delay loop. */ +#ifndef BSP_DELAY_LOOP_CYCLES + #define BSP_DELAY_LOOP_CYCLES (100) +#endif + +/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ +typedef enum +{ + BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds + BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds + BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds +} bsp_delay_units_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_group_irq.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_group_irq.c new file mode 100644 index 00000000..07fa7ca0 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_group_irq.c @@ -0,0 +1,56 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Register a callback function for supported interrupts. If NULL is passed for the callback argument then any + * previously registered callbacks are unregistered. + * + * @param[in] irq Interrupt for which to register a callback. + * @param[in] p_callback Pointer to function to call when interrupt occurs. + * + * @retval FSP_ERR_UNSUPPORTED NMI Group IRQ are not supported in this device. + **********************************************************************************************************************/ +fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)) +{ + (void) irq; + (void) p_callback; +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Check pointer for NULL value. */ + FSP_ASSERT(p_callback); +#endif + + return FSP_ERR_UNSUPPORTED; +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_group_irq.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_group_irq.h new file mode 100644 index 00000000..194d276f --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_group_irq.h @@ -0,0 +1,46 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_GROUP_IRQ_H +#define BSP_GROUP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_UNSUPPORTED = 0, ///< NMI Group IRQ are not supported in this device. +} bsp_grp_irq_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.c new file mode 100644 index 00000000..e999cb7d --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.c @@ -0,0 +1,12 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_guard.h" + +/* Only the secure project has nonsecure callable functions. */ +#if BSP_TZ_SECURE_BUILD + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.h new file mode 100644 index 00000000..7c12ee10 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_guard.h @@ -0,0 +1,26 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_GUARD_H +#define BSP_GUARD_H + +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ + FSP_FOOTER + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.c new file mode 100644 index 00000000..ed743017 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +volatile uint32_t g_protect_pfswe_counter; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.h new file mode 100644 index 00000000..df304bb0 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_io.h @@ -0,0 +1,841 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write access to port pins. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_H +#define BSP_IO_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define BSP_IO_PRV_8BIT_MASK (0xFF) +#define BSP_IO_PRV_PIN_MASK (1U) +#define BSP_IO_PRV_PORT_OFFSET (8U) +#define BSP_IO_PRV_PFCWE_MASK (0xFFFFFFBF) +#define BSP_IO_PRV_OENWE_MASK (0xFFFFFFDF) +#define BSP_IO_PRV_SET_OEN_ENABLE (0U) +#define BSP_IO_PRV_SET_SSEL0_SELCTL2 (0x1000U) +#define BSP_IO_PRV_SET_SSEL1_SELCTL0 (0x0100U) +#define BSP_IO_PWPR_B0WI_OFFSET (7U) +#define BSP_IO_PWPR_PFSWE_OFFSET (6U) +#define BSP_IO_PWPR_OENWE_OFFSET (5U) +#define BSP_IO_PM_PM_OUTPUT (3U) + +#define BSP_IO_PRV_P_REG_BASE_SET(base) BSP_IO_PRV_P_REG_BASE(base) +#define BSP_IO_PRV_P_REG_BASE(base) (&R_GPIO->P ## base) +#define BSP_IO_PRV_PM_REG_BASE_SET(base) BSP_IO_PRV_PM_REG_BASE(base) +#define BSP_IO_PRV_PM_REG_BASE(base) (&R_GPIO->PM ## base) +#define BSP_IO_PRV_PIN_REG_BASE_SET(base) BSP_IO_PRV_PIN_REG_BASE(base) +#define BSP_IO_PRV_PIN_REG_BASE(base) (&R_GPIO->PIN ## base) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Levels that can be set and read for individual pins */ +typedef enum e_bsp_io_level +{ + BSP_IO_LEVEL_LOW = 0, ///< Low + BSP_IO_LEVEL_HIGH ///< High +} bsp_io_level_t; + +/** Direction of individual pins */ +typedef enum e_bsp_io_dir +{ + BSP_IO_DIRECTION_HIZ = 0x0, ///< Hi-Z + BSP_IO_DIRECTION_INPUT = 0x4, ///< Input + BSP_IO_DIRECTION_OUTPUT = 0x8, ///< Output (Input disable) + BSP_IO_DIRECTION_OUTPUT_WITH_INPUT_ENABLE = 0xC ///< Output (Input enable) +} bsp_io_direction_t; + +#ifndef BSP_OVERRIDE_BSP_PORT_T + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x0000, ///< IO port 0 + BSP_IO_PORT_01 = 0x0100, ///< IO port 1 + BSP_IO_PORT_02 = 0x0200, ///< IO port 2 + BSP_IO_PORT_03 = 0x0300, ///< IO port 3 + BSP_IO_PORT_04 = 0x0400, ///< IO port 4 + BSP_IO_PORT_05 = 0x0500, ///< IO port 5 + BSP_IO_PORT_06 = 0x0600, ///< IO port 6 + BSP_IO_PORT_07 = 0x0700, ///< IO port 7 + BSP_IO_PORT_08 = 0x0800, ///< IO port 8 + BSP_IO_PORT_09 = 0x0900, ///< IO port 9 + BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 + BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 + BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 + BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 + BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 + BSP_IO_PORT_15 = 0x0F00, ///< IO port 15 + BSP_IO_PORT_16 = 0x1000, ///< IO port 16 + BSP_IO_PORT_17 = 0x1100, ///< IO port 17 + BSP_IO_PORT_18 = 0x1200, ///< IO port 18 + BSP_IO_PORT_19 = 0x1300, ///< IO port 19 + BSP_IO_PORT_20 = 0x1400, ///< IO port 20 + BSP_IO_PORT_21 = 0x1500, ///< IO port 21 + BSP_IO_PORT_22 = 0x1600, ///< IO port 22 + BSP_IO_PORT_23 = 0x1700, ///< IO port 23 + BSP_IO_PORT_24 = 0x1800, ///< IO port 24 + BSP_IO_PORT_25 = 0x1900, ///< IO port 25 + BSP_IO_PORT_26 = 0x1A00, ///< IO port 26 + BSP_IO_PORT_27 = 0x1B00, ///< IO port 27 + BSP_IO_PORT_28 = 0x1C00, ///< IO port 28 + BSP_IO_PORT_29 = 0x1D00, ///< IO port 29 + BSP_IO_PORT_30 = 0x1E00, ///< IO port 30 + BSP_IO_PORT_31 = 0x1F00, ///< IO port 31 + BSP_IO_PORT_32 = 0x2000, ///< IO port 32 + BSP_IO_PORT_33 = 0x2100, ///< IO port 33 + BSP_IO_PORT_34 = 0x2200, ///< IO port 34 + BSP_IO_PORT_35 = 0x2300, ///< IO port 35 + BSP_IO_PORT_36 = 0x2400, ///< IO port 36 + BSP_IO_PORT_37 = 0x2500, ///< IO port 37 + BSP_IO_PORT_38 = 0x2600, ///< IO port 38 + BSP_IO_PORT_39 = 0x2700, ///< IO port 39 + BSP_IO_PORT_40 = 0x2800, ///< IO port 40 + BSP_IO_PORT_41 = 0x2900, ///< IO port 41 + BSP_IO_PORT_42 = 0x2A00, ///< IO port 42 + BSP_IO_PORT_43 = 0x2B00, ///< IO port 43 + BSP_IO_PORT_44 = 0x2C00, ///< IO port 44 + BSP_IO_PORT_45 = 0x2D00, ///< IO port 45 + BSP_IO_PORT_46 = 0x2E00, ///< IO port 46 + BSP_IO_PORT_47 = 0x2F00, ///< IO port 47 + BSP_IO_PORT_48 = 0x3000, ///< IO port 48 +} bsp_io_port_t; + +#endif + +#ifndef BSP_OVERRIDE_BSP_PIN_T + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin_t +{ + BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + + BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + + BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + + BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + + BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + + BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + + BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + + BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + + BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + + BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + + BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + + BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + + BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 + BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 + + BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 + BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 + BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 + + BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 + BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 + + BSP_IO_PORT_15_PIN_00 = 0x0F00, ///< IO port 15 pin 0 + BSP_IO_PORT_15_PIN_01 = 0x0F01, ///< IO port 15 pin 1 + + BSP_IO_PORT_16_PIN_00 = 0x1000, ///< IO port 16 pin 0 + BSP_IO_PORT_16_PIN_01 = 0x1001, ///< IO port 16 pin 1 + + BSP_IO_PORT_17_PIN_00 = 0x1100, ///< IO port 17 pin 0 + BSP_IO_PORT_17_PIN_01 = 0x1101, ///< IO port 17 pin 1 + BSP_IO_PORT_17_PIN_02 = 0x1102, ///< IO port 17 pin 2 + + BSP_IO_PORT_18_PIN_00 = 0x1200, ///< IO port 18 pin 0 + BSP_IO_PORT_18_PIN_01 = 0x1201, ///< IO port 18 pin 1 + + BSP_IO_PORT_19_PIN_00 = 0x1300, ///< IO port 19 pin 0 + BSP_IO_PORT_19_PIN_01 = 0x1301, ///< IO port 19 pin 1 + + BSP_IO_PORT_20_PIN_00 = 0x1400, ///< IO port 20 pin 0 + BSP_IO_PORT_20_PIN_01 = 0x1401, ///< IO port 20 pin 1 + BSP_IO_PORT_20_PIN_02 = 0x1402, ///< IO port 20 pin 2 + + BSP_IO_PORT_21_PIN_00 = 0x1500, ///< IO port 21 pin 0 + BSP_IO_PORT_21_PIN_01 = 0x1501, ///< IO port 21 pin 1 + + BSP_IO_PORT_22_PIN_00 = 0x1600, ///< IO port 22 pin 0 + BSP_IO_PORT_22_PIN_01 = 0x1601, ///< IO port 22 pin 1 + + BSP_IO_PORT_23_PIN_00 = 0x1700, ///< IO port 23 pin 0 + BSP_IO_PORT_23_PIN_01 = 0x1701, ///< IO port 23 pin 1 + + BSP_IO_PORT_24_PIN_00 = 0x1800, ///< IO port 24 pin 0 + BSP_IO_PORT_24_PIN_01 = 0x1801, ///< IO port 24 pin 1 + + BSP_IO_PORT_25_PIN_00 = 0x1900, ///< IO port 25 pin 0 + BSP_IO_PORT_25_PIN_01 = 0x1901, ///< IO port 25 pin 1 + + BSP_IO_PORT_26_PIN_00 = 0x1A00, ///< IO port 26 pin 0 + BSP_IO_PORT_26_PIN_01 = 0x1A01, ///< IO port 26 pin 1 + + BSP_IO_PORT_27_PIN_00 = 0x1B00, ///< IO port 27 pin 0 + BSP_IO_PORT_27_PIN_01 = 0x1B01, ///< IO port 27 pin 1 + + BSP_IO_PORT_28_PIN_00 = 0x1C00, ///< IO port 28 pin 0 + BSP_IO_PORT_28_PIN_01 = 0x1C01, ///< IO port 28 pin 1 + + BSP_IO_PORT_29_PIN_00 = 0x1D00, ///< IO port 29 pin 0 + BSP_IO_PORT_29_PIN_01 = 0x1D01, ///< IO port 29 pin 1 + + BSP_IO_PORT_30_PIN_00 = 0x1E00, ///< IO port 30 pin 0 + BSP_IO_PORT_30_PIN_01 = 0x1E01, ///< IO port 30 pin 1 + + BSP_IO_PORT_31_PIN_00 = 0x1F00, ///< IO port 31 pin 0 + BSP_IO_PORT_31_PIN_01 = 0x1F01, ///< IO port 31 pin 1 + + BSP_IO_PORT_32_PIN_00 = 0x2000, ///< IO port 32 pin 0 + BSP_IO_PORT_32_PIN_01 = 0x2001, ///< IO port 32 pin 1 + + BSP_IO_PORT_33_PIN_00 = 0x2100, ///< IO port 33 pin 0 + BSP_IO_PORT_33_PIN_01 = 0x2101, ///< IO port 33 pin 1 + + BSP_IO_PORT_34_PIN_00 = 0x2200, ///< IO port 34 pin 0 + BSP_IO_PORT_34_PIN_01 = 0x2201, ///< IO port 34 pin 1 + + BSP_IO_PORT_35_PIN_00 = 0x2300, ///< IO port 35 pin 0 + BSP_IO_PORT_35_PIN_01 = 0x2301, ///< IO port 35 pin 1 + + BSP_IO_PORT_36_PIN_00 = 0x2400, ///< IO port 36 pin 0 + BSP_IO_PORT_36_PIN_01 = 0x2401, ///< IO port 36 pin 1 + + BSP_IO_PORT_37_PIN_00 = 0x2500, ///< IO port 37 pin 0 + BSP_IO_PORT_37_PIN_01 = 0x2501, ///< IO port 37 pin 1 + BSP_IO_PORT_37_PIN_02 = 0x2502, ///< IO port 37 pin 2 + + BSP_IO_PORT_38_PIN_00 = 0x2600, ///< IO port 38 pin 0 + BSP_IO_PORT_38_PIN_01 = 0x2601, ///< IO port 38 pin 1 + + BSP_IO_PORT_39_PIN_00 = 0x2700, ///< IO port 39 pin 0 + BSP_IO_PORT_39_PIN_01 = 0x2701, ///< IO port 39 pin 1 + BSP_IO_PORT_39_PIN_02 = 0x2702, ///< IO port 39 pin 2 + + BSP_IO_PORT_40_PIN_00 = 0x2800, ///< IO port 40 pin 0 + BSP_IO_PORT_40_PIN_01 = 0x2801, ///< IO port 40 pin 1 + BSP_IO_PORT_40_PIN_02 = 0x2802, ///< IO port 40 pin 2 + + BSP_IO_PORT_41_PIN_00 = 0x2900, ///< IO port 41 pin 0 + BSP_IO_PORT_41_PIN_01 = 0x2901, ///< IO port 41 pin 1 + + BSP_IO_PORT_42_PIN_00 = 0x2A00, ///< IO port 42 pin 0 + BSP_IO_PORT_42_PIN_01 = 0x2A01, ///< IO port 42 pin 1 + BSP_IO_PORT_42_PIN_02 = 0x2A02, ///< IO port 42 pin 2 + BSP_IO_PORT_42_PIN_03 = 0x2A03, ///< IO port 42 pin 3 + BSP_IO_PORT_42_PIN_04 = 0x2A04, ///< IO port 42 pin 4 + + BSP_IO_PORT_43_PIN_00 = 0x2B00, ///< IO port 43 pin 0 + BSP_IO_PORT_43_PIN_01 = 0x2B01, ///< IO port 43 pin 1 + BSP_IO_PORT_43_PIN_02 = 0x2B02, ///< IO port 43 pin 2 + BSP_IO_PORT_43_PIN_03 = 0x2B03, ///< IO port 43 pin 3 + + BSP_IO_PORT_44_PIN_00 = 0x2C00, ///< IO port 44 pin 0 + BSP_IO_PORT_44_PIN_01 = 0x2C01, ///< IO port 44 pin 1 + BSP_IO_PORT_44_PIN_02 = 0x2C02, ///< IO port 44 pin 2 + BSP_IO_PORT_44_PIN_03 = 0x2C03, ///< IO port 44 pin 3 + + BSP_IO_PORT_45_PIN_00 = 0x2D00, ///< IO port 45 pin 0 + BSP_IO_PORT_45_PIN_01 = 0x2D01, ///< IO port 45 pin 1 + BSP_IO_PORT_45_PIN_02 = 0x2D02, ///< IO port 45 pin 2 + BSP_IO_PORT_45_PIN_03 = 0x2D03, ///< IO port 45 pin 3 + + BSP_IO_PORT_46_PIN_00 = 0x2E00, ///< IO port 46 pin 0 + BSP_IO_PORT_46_PIN_01 = 0x2E01, ///< IO port 46 pin 1 + BSP_IO_PORT_46_PIN_02 = 0x2E02, ///< IO port 46 pin 2 + BSP_IO_PORT_46_PIN_03 = 0x2E03, ///< IO port 46 pin 3 + + BSP_IO_PORT_47_PIN_00 = 0x2F00, ///< IO port 47 pin 0 + BSP_IO_PORT_47_PIN_01 = 0x2F01, ///< IO port 47 pin 1 + BSP_IO_PORT_47_PIN_02 = 0x2F02, ///< IO port 47 pin 2 + BSP_IO_PORT_47_PIN_03 = 0x2F03, ///< IO port 47 pin 3 + + BSP_IO_PORT_48_PIN_00 = 0x3000, ///< IO port 48 pin 0 + BSP_IO_PORT_48_PIN_01 = 0x3001, ///< IO port 48 pin 1 + BSP_IO_PORT_48_PIN_02 = 0x3002, ///< IO port 48 pin 2 + BSP_IO_PORT_48_PIN_03 = 0x3003, ///< IO port 48 pin 3 + BSP_IO_PORT_48_PIN_04 = 0x3004, ///< IO port 48 pin 4 + + /* Special purpose port */ + BSP_IO_NMI = 0xFFFF0100, ///< NMI + + BSP_IO_TMS_SWDIO = 0xFFFF0200, ///< TMS_SWDIO + + BSP_IO_TDO = 0xFFFF0300, ///< TDO + + BSP_IO_AUDIO_CLK1 = 0xFFFF0400, ///< AUDIO_CLK1 + BSP_IO_AUDIO_CLK2 = 0xFFFF0401, ///< AUDIO_CLK2 + + BSP_IO_SD0_CLK = 0xFFFF0600, ///< CD0_CLK + BSP_IO_SD0_CMD = 0xFFFF0601, ///< CD0_CMD + BSP_IO_SD0_RST_N = 0xFFFF0602, ///< CD0_RST_N + + BSP_IO_SD0_DATA0 = 0xFFFF0700, ///< SD0_DATA0 + BSP_IO_SD0_DATA1 = 0xFFFF0701, ///< SD0_DATA1 + BSP_IO_SD0_DATA2 = 0xFFFF0702, ///< SD0_DATA2 + BSP_IO_SD0_DATA3 = 0xFFFF0703, ///< SD0_DATA3 + BSP_IO_SD0_DATA4 = 0xFFFF0704, ///< SD0_DATA4 + BSP_IO_SD0_DATA5 = 0xFFFF0705, ///< SD0_DATA5 + BSP_IO_SD0_DATA6 = 0xFFFF0706, ///< SD0_DATA6 + BSP_IO_SD0_DATA7 = 0xFFFF0707, ///< SD0_DATA7 + + BSP_IO_SD1_CLK = 0xFFFF0800, ///< SD1_CLK + BSP_IO_SD1_CMD = 0xFFFF0801, ///< SD1_CMD + + BSP_IO_SD1_DATA0 = 0xFFFF0900, ///< SD1_DATA0 + BSP_IO_SD1_DATA1 = 0xFFFF0901, ///< SD1_DATA1 + BSP_IO_SD1_DATA2 = 0xFFFF0902, ///< SD1_DATA2 + BSP_IO_SD1_DATA3 = 0xFFFF0903, ///< SD1_DATA3 + + BSP_IO_QSPI0_SPCLK = 0xFFFF0A00, ///< QSPI0_SPCLK + BSP_IO_QSPI0_IO0 = 0xFFFF0A01, ///< QSPI0_IO0 + BSP_IO_QSPI0_IO1 = 0xFFFF0A02, ///< QSPI0_IO1 + BSP_IO_QSPI0_IO2 = 0xFFFF0A03, ///< QSPI0_IO2 + BSP_IO_QSPI0_IO3 = 0xFFFF0A04, ///< QSPI0_IO3 + BSP_IO_QSPI0_SSL = 0xFFFF0A05, ///< QSPI0_SSL + + BSP_IO_QSPI1_SPCLK = 0xFFFF0B00, ///< QSPI1_SPCLK + BSP_IO_QSPI1_IO0 = 0xFFFF0B01, ///< QSPI1_IO0 + BSP_IO_QSPI1_IO1 = 0xFFFF0B02, ///< QSPI1_IO1 + BSP_IO_QSPI1_IO2 = 0xFFFF0B03, ///< QSPI1_IO2 + BSP_IO_QSPI1_IO3 = 0xFFFF0B04, ///< QSPI1_IO3 + BSP_IO_QSPI1_SSL = 0xFFFF0B05, ///< QSPI1_SSL + + BSP_IO_QSPI_RESET_N = 0xFFFF0C00, ///< QSPI_RESET_N + BSP_IO_QSPI_WP_N = 0xFFFF0C01, ///< QSPI_WP_N + BSP_IO_QSPI_INT_N = 0xFFFF0C02, ///< QSPI_INT_N + + BSP_IO_WDTOVF_PERROUT_N = 0xFFFF0D00, ///< WDTOVF_PERROUT_N + + BSP_IO_RIIC0_SDA = 0xFFFF0E00, ///< RIIC0_SDA + BSP_IO_RIIC0_SCL = 0xFFFF0E01, ///< RIIC0_SCL + BSP_IO_RIIC1_SDA = 0xFFFF0E02, ///< RIIC1_SDA + BSP_IO_RIIC1_SCL = 0xFFFF0E03, ///< RIIC1_SCL +} bsp_io_port_pin_t; + +#endif + +/** Superset of SD channels. */ +typedef enum e_bsp_sd_ch +{ + BSP_SD_CHANNEL_0 = 0x00, ///< Used to select SD channel 0 + BSP_SD_CHANNEL_1 = 0x01, ///< Used to select SD channel 1 +} bsp_sd_channel_t; + +/** Superset of Ethernet channels. */ +typedef enum e_bsp_eth_ch +{ + BSP_ETHERNET_CHANNEL_0 = 0x00, ///< Used to select Ethernet channel 0 + BSP_ETHERNET_CHANNEL_1 = 0x01, ///< Used to select Ethernet channel 1 +} bsp_ethernet_channel_t; + +/** Superset of SD voltages. */ +typedef enum e_bsp_sd_voltage +{ + BSP_SD_VOLTAGE_33 = 0x00, ///< SD voltage set to 3.3V + BSP_SD_VOLTAGE_18 = 0x01, ///< SD voltage set to 1.8V +} bsp_sd_voltage_t; + +/** Superset of QSPI voltages. */ +typedef enum e_bsp_qspi_voltage +{ + BSP_QSPI_VOLTAGE_33 = 0x00, ///< QSPI voltage set to 3.3V + BSP_QSPI_VOLTAGE_18 = 0x01, ///< QSPI voltage set to 1.8V +} bsp_qspi_voltage_t; + +/** Superset of XSPI voltages. */ +typedef enum e_bsp_xspi_voltage +{ + BSP_XSPI_VOLTAGE_33 = 0x00, ///< XSPI voltage set to 3.3V + BSP_XSPI_VOLTAGE_18 = 0x01, ///< XSPI voltage set to 1.8V + BSP_XSPI_VOLTAGE_25 = 0x02, ///< XSPI voltage set to 2.5V +} bsp_xspi_voltage_t; + +/** Superset of Ethernet voltages. */ +typedef enum e_bsp_eth_voltage +{ + BSP_ETHERNET_VOLTAGE_33 = 0x00, ///< Ethernet voltage set to 3.3V + BSP_ETHERNET_VOLTAGE_18 = 0x01, ///< Ethernet voltage set to 1.8V + BSP_ETHERNET_VOLTAGE_25 = 0x02, ///< Ethernet voltage set to 2.5V +} bsp_ethernet_voltage_t; + +/** Superset of I3C voltages. */ +typedef enum e_bsp_i3c_voltage +{ + BSP_I3C_VOLTAGE_18 = 0x00, ///< I3C voltage set to 1.8V + BSP_I3C_VOLTAGE_12 = 0x01, ///< I3C voltage set to 1.2V +} bsp_i3c_voltage_t; + +/** Superset of Ethernet PHY modes. */ +typedef enum e_bsp_eth_mode +{ + BSP_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to RMII + BSP_ETHERNET_MODE_MII = 0x01, ///< Ethernet PHY mode set to MII +} bsp_ethernet_mode_t; + +/** Superset of Standby modes for I3C. */ +typedef enum e_bsp_i3c_mode +{ + BSP_I3C_MODE_STB = 0x00, ///< Standby mode set to Standby mode + BSP_I3C_MODE_NOR = 0x01, ///< Standby mode set to Normal mode +} bsp_i3c_mode_t; + +/** Superset of oscillator for bypass mode. */ +typedef enum e_bsp_bypass_oscillator +{ + BSP_BYPASS_OSCILLATOR_RTC = 0x00, ///< Oscillator set to RTC + BSP_BYPASS_OSCILLATOR_AUDIO = 0x01, ///< Oscillator set to Audio + BSP_BYPASS_OSCILLATOR_EMCLK = 0x02, ///< Oscillator set to EMCLK +} bsp_bypass_oscillator_t; + +/** Superset of bypass modes. */ +typedef enum e_bsp_bypass_mode +{ + BSP_BYPASS_MODE_CRYSTAL_OSC = 0x00, ///< Bypass mode set to Crystal oscillator + BSP_BYPASS_MODE_EXTERNAL_CLK = 0x01, ///< Bypass mode set to External clock receive + BSP_BYPASS_MODE_POWER_DOWN = 0x02, ///< Bypass mode set to Power-down +} bsp_bypass_mode_t; + +/** Superset of frequency range for bypass mode. */ +typedef enum e_bsp_bypass_freq_range +{ + BSP_BYPASS_FREQ_RANGE_1MHZ = 0x00, ///< Frequency range set to 32KHz to 1MHz + BSP_BYPASS_FREQ_RANGE_12MHZ = 0x02, ///< Frequency range set to 1.1MHz to 12MHz + BSP_BYPASS_FREQ_RANGE_24MHZ = 0x01, ///< Frequency range set to 12.1MHz to 24MHz + BSP_BYPASS_FREQ_RANGE_48MHZ = 0x03, ///< Frequency range set to 24.1MHz to 48MHz +} bsp_bypass_freq_range_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern volatile uint32_t g_protect_pfswe_counter; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Read the current input level of the pin. + * + * @param[in] pin The pin + * + * @retval Current input level + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) +{ + /* Read pin level. */ + volatile const uint8_t * p_pin; + + p_pin = BSP_IO_PRV_PIN_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_pin = &p_pin[pin >> BSP_IO_PRV_PORT_OFFSET]; + + return (uint32_t) ((*p_pin) >> (pin & BSP_IO_PRV_8BIT_MASK)) & BSP_IO_PRV_PIN_MASK; +} + +/*******************************************************************************************************************//** + * Set a pin to output and set the output level to the level provided + * + * @param[in] pin The pin + * @param[in] level The level + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) +{ + /* Set output level and pin direction to output. */ + volatile uint16_t * p_pm; + volatile uint8_t * p_p; + uint16_t reg_value_pm; + uint8_t reg_value_p; + uint16_t mask_pm; + uint8_t mask_p; + uint16_t write_value_pm; + uint8_t write_value_p; + + p_pm = BSP_IO_PRV_PM_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_p = BSP_IO_PRV_P_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + + reg_value_pm = p_pm[pin >> BSP_IO_PRV_PORT_OFFSET]; + reg_value_p = p_p[pin >> BSP_IO_PRV_PORT_OFFSET]; + + mask_pm = (uint16_t) (~(BSP_IO_PM_PM_OUTPUT << ((pin & BSP_IO_PRV_8BIT_MASK) * 2))); + mask_p = (uint8_t) (~(1 << (pin & BSP_IO_PRV_8BIT_MASK))); + + write_value_pm = (uint16_t) (BSP_IO_PM_PM_OUTPUT << ((pin & BSP_IO_PRV_8BIT_MASK) * 2)); + write_value_p = (uint8_t) (level << (pin & BSP_IO_PRV_8BIT_MASK)); + + p_pm[pin >> BSP_IO_PRV_PORT_OFFSET] = ((reg_value_pm & mask_pm) | write_value_pm); + p_p[pin >> BSP_IO_PRV_PORT_OFFSET] = ((reg_value_p & mask_p) | write_value_p); +} + +/*******************************************************************************************************************//** + * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur + * via multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessEnable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** If this is first entry then allow writing of PFS. */ + if (0 == g_protect_pfswe_counter) + { + #if BSP_FEATURE_BSP_SUPPORT_PFCWE_PROTECT + R_GPIO->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_GPIO->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #else + R_GPIO->PWPR = (uint32_t) ((BSP_IO_PRV_PFCWE_MASK & R_GPIO->PWPR) | (1U << BSP_IO_PWPR_PFSWE_OFFSET)); + #endif + } + + /** Increment the protect counter */ + g_protect_pfswe_counter++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via + * multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessDisable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** Is it safe to disable PFS register? */ + if (0 != g_protect_pfswe_counter) + { + /* Decrement the protect counter */ + g_protect_pfswe_counter--; + } + + /** Is it safe to disable writing of PFS? */ + if (0 == g_protect_pfswe_counter) + { + #if BSP_FEATURE_BSP_SUPPORT_PFCWE_PROTECT + R_GPIO->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled + R_GPIO->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled + #else + R_GPIO->PWPR = (uint32_t) (BSP_IO_PRV_PFCWE_MASK & R_GPIO->PWPR); + #endif + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Enable access to the OEN registers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_OENAccessEnable (void) +{ +#if BSP_FEATURE_BSP_SUPPORT_OEN_PROTECT + #if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + R_GPIO->PWPR = (uint32_t) ((BSP_IO_PRV_OENWE_MASK & R_GPIO->PWPR) | (1U << BSP_IO_PWPR_OENWE_OFFSET)); + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; + #endif +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the OEN registers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_OENAccessDisable (void) +{ +#if BSP_FEATURE_BSP_SUPPORT_OEN_PROTECT + #if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + R_GPIO->PWPR = (uint32_t) (BSP_IO_PRV_OENWE_MASK & R_GPIO->PWPR); + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; + #endif +#endif +} + +/*******************************************************************************************************************//** + * Configures Ethernet channel PHY mode. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_EthernetModeCfg (bsp_ethernet_channel_t channel, bsp_ethernet_mode_t mode) +{ +#if BSP_FEATURE_BSP_SUPPORT_ETHER_MODE + #if BSP_FEATURE_BSP_HAS_PFC_OEN_REG + if (mode == BSP_ETHERNET_MODE_RMII) + { + if (channel == BSP_ETHERNET_CHANNEL_0) + { + R_CPG->CPG_SSEL0 |= BSP_IO_PRV_SET_SSEL0_SELCTL2; + } + else + { + R_CPG->CPG_SSEL1 |= BSP_IO_PRV_SET_SSEL1_SELCTL0; + } + } + + R_BSP_OENAccessEnable(); + + if (BSP_ETHERNET_CHANNEL_0 == channel) + { + R_GPIO->PFC_OEN_b.OEN0 = mode; + } + else if (BSP_ETHERNET_CHANNEL_1 == channel) + { + R_GPIO->PFC_OEN_b.OEN1 = mode; + } + + R_BSP_OENAccessDisable(); + #elif BSP_FEATURE_BSP_HAS_ETHER_MODE_REG + uint32_t reg_value = R_GPIO->ETH_MODE; + + reg_value = (uint32_t) ((reg_value & (uint32_t) (~(1 << channel))) | (mode << channel)); + + R_GPIO->ETH_MODE = reg_value; + #else + uint8_t reg_value = R_GPIO->ETH_MII_RGMII; + + reg_value = (uint8_t) ((reg_value & (uint8_t) (~(1 << channel))) | (mode << channel)); + + R_GPIO->ETH_MII_RGMII = reg_value; + #endif +#else + FSP_PARAMETER_NOT_USED(channel); + FSP_PARAMETER_NOT_USED(mode); +#endif +} + +/*******************************************************************************************************************//** + * Configures SD channel voltage mode. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_SDVoltageModeCfg (bsp_sd_channel_t channel, bsp_sd_voltage_t voltage) +{ +#if BSP_FEATURE_BSP_SUPPORT_SD_VOLT + if (BSP_SD_CHANNEL_0 == channel) + { + #if BSP_FEATURE_BSP_HAS_SD_CH_POC_REG + R_GPIO->SD_CH0_POC = voltage; + #else + R_GPIO->SD_ch0 = voltage; + #endif + } + else if (BSP_SD_CHANNEL_1 == channel) + { + #if BSP_FEATURE_BSP_HAS_SD_CH_POC_REG + R_GPIO->SD_CH1_POC = voltage; + #else + R_GPIO->SD_ch1 = voltage; + #endif + } + else + { + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(voltage); + } + +#else + FSP_PARAMETER_NOT_USED(channel); + FSP_PARAMETER_NOT_USED(voltage); +#endif +} + +/*******************************************************************************************************************//** + * Configures QSPI channel voltage mode. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_QSPIVoltageModeCfg (bsp_qspi_voltage_t voltage) +{ +#if BSP_FEATURE_BSP_SUPPORT_QSPI_VOLT + R_GPIO->QSPI = voltage; +#else + FSP_PARAMETER_NOT_USED(voltage); +#endif +} + +/*******************************************************************************************************************//** + * Configures XSPI channel voltage mode. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_XSPIVoltageModeCfg (bsp_xspi_voltage_t voltage) +{ +#if BSP_FEATURE_BSP_SUPPORT_XSPI_VOLT + R_GPIO->XSPI_POC = voltage; +#else + FSP_PARAMETER_NOT_USED(voltage); +#endif +} + +/*******************************************************************************************************************//** + * Configures Ethernet channel voltage mode. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_EthernetVoltageModeCfg (bsp_ethernet_channel_t channel, bsp_ethernet_voltage_t voltage) +{ +#if BSP_FEATURE_BSP_SUPPORT_ETHER_VOLT + if (BSP_ETHERNET_CHANNEL_0 == channel) + { + #if BSP_FEATURE_BSP_HAS_ETH_POC_REG + R_GPIO->ETH0_POC = voltage; + #else + R_GPIO->ETH_ch0 = voltage; + #endif + } + else if (BSP_ETHERNET_CHANNEL_1 == channel) + { + #if BSP_FEATURE_BSP_HAS_ETH_POC_REG + R_GPIO->ETH1_POC = voltage; + #else + R_GPIO->ETH_ch1 = voltage; + #endif + } + else + { + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(voltage); + } + +#else + FSP_PARAMETER_NOT_USED(channel); + FSP_PARAMETER_NOT_USED(voltage); +#endif +} + +/*******************************************************************************************************************//** + * Configures I3C control. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_I3CControlCfg (bsp_i3c_voltage_t voltage, bsp_i3c_mode_t mode) +{ +#if BSP_FEATURE_BSP_SUPPORT_I3C + R_GPIO->I3C_SET_b.POC = voltage; + R_GPIO->I3C_SET_b.STBN = mode; +#else + FSP_PARAMETER_NOT_USED(voltage); + FSP_PARAMETER_NOT_USED(mode); +#endif +} + +/*******************************************************************************************************************//** + * Configures bypass mode for RTC, Audio and EMCLK oscillator. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_BypassModeCfg (bsp_bypass_oscillator_t oscillator, + bsp_bypass_mode_t mode, + bsp_bypass_freq_range_t freq_range) +{ +#if BSP_FEATURE_BSP_SUPPORT_BYPASS + switch (oscillator) + { + case BSP_BYPASS_OSCILLATOR_AUDIO: + { + R_GPIO->PFC_OSCBYPS_b.OSCBYPS1 = mode & 1U; + R_GPIO->PFC_OSCBYPS_b.OSCPW1 = ((mode >> 1U) & 1U); + R_GPIO->PFC_OSCBYPS_b.OSCSF1 = freq_range; + break; + } + + case BSP_BYPASS_OSCILLATOR_EMCLK: + { + R_GPIO->PFC_OSCBYPS_b.OSCBYPS2 = mode & 1U; + R_GPIO->PFC_OSCBYPS_b.OSCPW2 = ((mode >> 1U) & 1U); + R_GPIO->PFC_OSCBYPS_b.OSCSF2 = freq_range; + break; + } + + case BSP_BYPASS_OSCILLATOR_RTC: + { + R_GPIO->PFC_OSCBYPS_b.OSCBYPS0 = mode & 1U; + R_GPIO->PFC_OSCBYPS_b.OSCPW0 = ((mode >> 1U) & 1U); + FSP_PARAMETER_NOT_USED(freq_range); + break; + } + + default: + + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(mode); + FSP_PARAMETER_NOT_USED(freq_range); + } + +#else + FSP_PARAMETER_NOT_USED(oscillator); + FSP_PARAMETER_NOT_USED(mode); + FSP_PARAMETER_NOT_USED(freq_range); +#endif +} + +/*******************************************************************************************************************//** + * Configures XSPI output Enable. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_XSPIOutputEnableCfg (void) +{ +#if BSP_FEATURE_BSP_SUPPORT_XSPI_OUTPUT + R_BSP_OENAccessEnable(); + R_GPIO->PFC_OEN_b.OEN2 = BSP_IO_PRV_SET_OEN_ENABLE; + R_GPIO->PFC_OEN_b.OEN3 = BSP_IO_PRV_SET_OEN_ENABLE; + R_GPIO->PFC_OEN_b.OEN4 = BSP_IO_PRV_SET_OEN_ENABLE; + R_GPIO->PFC_OEN_b.OEN5 = BSP_IO_PRV_SET_OEN_ENABLE; + R_BSP_OENAccessDisable(); +#endif +} + +/** @} (end addtogroup BSP_IO) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irq.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irq.c new file mode 100644 index 00000000..993705a5 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irq.c @@ -0,0 +1,46 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* This table is used to store the context in the ISR. */ +void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * In this device, this function does nothing. This function is written to share code with other devices. + **********************************************************************************************************************/ +void bsp_irq_cfg (void) +{ + /* Currently does nothing */ + __NOP(); +} diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.c new file mode 100644 index 00000000..a51be8f3 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.c @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_irqs.c + * Version : 1.00 + * Description : bsp_irq (secure) source code + *********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_irq.h" +#include "bsp_irqs.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_PRV_BITS_PER_WORD (32) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * This function provides clock to DMA Controller (see section 'Precaution when use the peripheral modules + * which can initiate DMA Controller.' in the user's manual for detail) and enables IM33. + * It also enables any interrupt in a non-secure state. + **********************************************************************************************************************/ +void bsp_irq_cfg_s (void) +{ + R_BSP_MODULE_CLKON(FSP_IP_DMAC, 0); + R_BSP_MODULE_RSTOFF(FSP_IP_DMAC, 0); + R_BSP_MODULE_CLKON(FSP_IP_DMAC, 1); + R_BSP_MODULE_RSTOFF(FSP_IP_DMAC, 1); + R_BSP_IM33_ENABLE(); + +#if BSP_NONSECURE_TRANSITION + #if FSP_PRIV_TZ_USE_SECURE_REGS + + /* Place all vectors in non-secure state. */ + for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD); i++) + { + NVIC->ITNS[i] = UINT32_MAX; + } + #endif +#endif +} diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.h new file mode 100644 index 00000000..c8a5d03c --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_irqs.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_irqs.h + * Version : 1.00 + * Description : bsp_irq (secure) header + *********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IRQS_H +#define BSP_IRQS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg_s(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* BSP_IRQS_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_mcu_api.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_mcu_api.h new file mode 100644 index 00000000..42e3e9c4 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_mcu_api.h @@ -0,0 +1,20 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MCU_API_H +#define BSP_MCU_API_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER +fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); +void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); +fsp_err_t R_BSP_VersionGet(fsp_version_t * p_version); +uint32_t R_BSP_SlaveAddressConversion(uint32_t original_address); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_module_stop.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_module_stop.h new file mode 100644 index 00000000..65e67d21 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_module_stop.h @@ -0,0 +1,131 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MODULE_H +#define BSP_MODULE_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be started. + * @param channel The channel. Use ch 0 for modules without channels. + *********************************************************************************************************************/ +#define R_BSP_MSTP_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) = 0x00000000U \ + | (BSP_MSTP_BIT_ ## ip(channel) << 16U); \ + BSP_MSTP_REG_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped. + * @param channel The channel. Use ch 0 for modules without channels. + *********************************************************************************************************************/ +#define R_BSP_MSTP_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) = 0x0000FFFFU \ + | (BSP_MSTP_BIT_ ## ip(channel) << 16U); \ + BSP_MSTP_REG_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/** @} (end addtogroup BSP_MCU) */ +#define BSP_MSTP_REG_FSP_IP_GTM(channel) R_CPG->CPG_BUS_REG0_MSTOP +#define BSP_MSTP_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_BUS_REG0_MSTOP_MSTOP4_ON_Pos + channel)) + +#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_CPG->CPG_BUS_MCPU1_MSTOP +#define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP4_ON_Pos) + +#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_CPG->CPG_BUS_MCPU1_MSTOP +#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP5_ON_Pos + channel)) + +#define BSP_MSTP_REG_FSP_IP_PORT(channel) R_CPG->CPG_BUS_PERI_CPU_MSTOP +#define BSP_MSTP_BIT_FSP_IP_PORT(channel) (1U << R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP6_ON_Pos) + +#define BSP_MSTP_REG_FSP_IP_IM33(channel) R_CPG->CPG_BUS_PERI_CPU_MSTOP +#define BSP_MSTP_BIT_FSP_IP_IM33(channel) (1U << R_CPG_CPG_BUS_PERI_CPU_MSTOP_MSTOP14_ON_Pos) + +#ifndef BSP_MSTP_REG_FSP_IP_SCIF + #define BSP_MSTP_REG_FSP_IP_SCIF(channel) R_CPG->CPG_BUS_MCPU2_MSTOP +#endif +#ifndef BSP_MSTP_BIT_FSP_IP_SCIF + #define BSP_MSTP_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP1_ON_Pos + channel)) +#endif + +#define BSP_MSTP_REG_FSP_IP_RIIC(channel) R_CPG->CPG_BUS_MCPU2_MSTOP +#define BSP_MSTP_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP10_ON_Pos + channel)) + +#ifndef BSP_MSTP_REG_FSP_IP_RSPI + #define BSP_MSTP_REG_FSP_IP_RSPI(channel) *((1U >= \ + channel) ? &R_CPG->CPG_BUS_MCPU1_MSTOP : &R_CPG->CPG_BUS_MCPU2_MSTOP) +#endif +#ifndef BSP_MSTP_BIT_FSP_IP_RSPI + #define BSP_MSTP_BIT_FSP_IP_RSPI(channel) ((1U >= \ + channel) ? (1U << (R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP14_ON_Pos + channel)) \ + : (1U << R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP0_ON_Pos)) +#endif + +#define BSP_MSTP_REG_FSP_IP_MHU(channel) R_CPG->CPG_MHU_MSTOP +#define BSP_MSTP_BIT_FSP_IP_MHU(channel) (1U << R_CPG_CPG_MHU_MSTOP_MSTOP0_ON_Pos) + +#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_CPG->CPG_BUS_REG1_MSTOP +#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (3U << \ + (R_CPG_CPG_BUS_REG1_MSTOP_MSTOP0_ON_Pos + \ + (channel * R_CPG_CPG_BUS_REG1_MSTOP_MSTOP2_ON_Pos))) +#define BSP_MSTP_REG_FSP_IP_DMAC_s(channel) BSP_MSTP_REG_FSP_IP_DMAC(channel) +#define BSP_MSTP_BIT_FSP_IP_DMAC_s(channel) BSP_MSTP_BIT_FSP_IP_DMAC(channel) + +#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_CPG->CPG_BUS_MCPU1_MSTOP +#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP10_ON_Pos + channel)) + +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_CPG->CPG_BUS_MCPU2_MSTOP +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP9_ON_Pos) + +#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_CPG->CPG_BUS_MCPU2_MSTOP +#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP14_ON_Pos) + +#define BSP_MSTP_REG_FSP_IP_TSU(channel) R_CPG->CPG_BUS_MCPU2_MSTOP +#define BSP_MSTP_BIT_FSP_IP_TSU(channel) (1U << R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP15_ON_Pos) + +#define BSP_MSTP_REG_FSP_IP_WDT(channel) R_CPG->CPG_BUS_REG0_MSTOP +#define BSP_MSTP_BIT_FSP_IP_WDT(channel) ((2U == (channel)) ? (1U << R_CPG_CPG_BUS_REG0_MSTOP_MSTOP1_ON_Pos) \ + : (1U << (R_CPG_CPG_BUS_REG0_MSTOP_MSTOP2_ON_Pos + channel))) + +#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_CPG->CPG_BUS_MCPU2_MSTOP +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP7_ON_Pos + channel)) + +#define BSP_MSTP_REG_FSP_IP_MTU3(channel) R_CPG->CPG_BUS_MCPU1_MSTOP +#define BSP_MSTP_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP2_ON_Pos)) + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif /* BSP_MODULE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_sbrk.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_sbrk.c new file mode 100644 index 00000000..2ba0a1f1 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_sbrk.c @@ -0,0 +1,92 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#include "bsp_api.h" +#include +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +caddr_t _sbrk(int incr); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * FSP implementation of the standard library _sbrk() function. + * @param[in] inc The number of bytes being asked for by malloc(). + * + * @note This function overrides the _sbrk version that exists in the newlib library that is linked with. + * That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and + * worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc() + * only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by + * malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc(). + * @retval Address of allocated area if successful, -1 otherwise. + **********************************************************************************************************************/ + +caddr_t _sbrk (int incr) +{ + extern char _Heap_Begin __asm("__HeapBase"); ///< Defined by the linker. + + extern char _Heap_Limit __asm("__HeapLimit"); ///< Defined by the linker. + + uint32_t bytes = (uint32_t) incr; + static char * current_heap_end = 0; + char * current_block_address; + + if (current_heap_end == 0) + { + current_heap_end = &_Heap_Begin; + } + + current_block_address = current_heap_end; + + /* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support + * unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple + * of 4. */ + bytes = (bytes + 3U) & (~3U); + if ((current_heap_end + bytes) > &_Heap_Limit) + { + /** Heap has overflowed */ + errno = ENOMEM; + + return (caddr_t) -1; + } + + current_heap_end += bytes; + + return (caddr_t) current_block_address; +} + +#endif /* defined__GNUC__ && !defined__ARMCC_VERSION */ + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + *********************************************************************************************************************/ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_security.c b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_security.c new file mode 100644 index 00000000..8c18aa33 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_security.c @@ -0,0 +1,160 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U) +#define FSP_NOT_DEFINED (0) + +#define BSP_PRV_CLEAR_THUMB_INSTRUCTION (0xFFFFFFFEUL) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_SecurityInit(void); +void R_BSP_PinCfgSecurityInit(void); + +/*********************************************************************************************************************** + * External symbols + **********************************************************************************************************************/ +extern fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES]; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * bsp_nonsecure_func_t)(void); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void); +#endif + +#if defined(__IAR_SYSTEMS_ICC__) + #pragma section=".tz_vector_ns_start" + +/* &__tz__C is the address of the non-secure callable section. Must assign value to this variable or + * linker will give error. */ + +/* &__tz__N is the start address of the non-secure region. */ +BSP_DONT_REMOVE void const * const __tz_VECTBL_N BSP_ALIGN_VARIABLE(16) @".tz_vector_ns_start"; + +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_vector_table = (uint32_t *) &__tz_VECTBL_N; +#elif defined(__ARMCC_VERSION) +extern const uint32_t Image$$__tz_VECTBL_N$$Base; + + #define __tz_VECTBL_N Image$$__tz_VECTBL_N$$Base + +/* Assign region addresses to pointers so that AC6 includes symbols that can be used to determine the + * start addresses of Secure, Non-secure and Non-secure Callable regions. */ +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_vector_table = &__tz_VECTBL_N; +#elif defined(__GNUC__) +extern const uint32_t __tz_VECTBL_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_vector_table = &__tz_VECTBL_N; +#endif + +#define BSP_PRV_STACK_LIMIT ((uint32_t) &__StackLimit) +extern uint32_t __StackLimit; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enter the non-secure code environment. + * + * This function configures the non-secure MSP and vector table then jumps to the non-secure project's Reset_Handler. + * + * @note This function (and therefore the non-secure code) should not return. + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter (void) +{ + /* The NS vector table is at the start of the NS section in internal ram */ + uint32_t const * p_ns_vector_table = gp_start_of_nonsecure_vector_table; + + /* Set up the NS Reset_Handler to be called */ + uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t)); + uint32_t const ns_reset_address = (uint32_t const) ((*p_ns_reset_address) & + BSP_PRV_CLEAR_THUMB_INSTRUCTION); + + /* Set the NS vector table address */ + SCB_NS->VTOR = (uint32_t) p_ns_vector_table; + + /* Use CM33 stack monitor. */ + __TZ_set_MSPLIM_NS(BSP_PRV_STACK_LIMIT); + + /* Set the NS stack pointer to the first entry in the NS vector table */ + __TZ_set_MSP_NS(p_ns_vector_table[0]); + + /* Jump to the NS Reset_Handler */ + __ASM volatile ("blxns %0" ::"r" (ns_reset_address)); +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Initialize security features for TrustZone. + * + * This function initializes ARM security register for secure projects. + * + * @note IDAU settings must be configured to match project settings. + **********************************************************************************************************************/ +void R_BSP_SecurityInit (void) +{ + /* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the + * system. */ + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + + /* Controls whether the SLEEPDEEP bit is only accessible from the Secure state, and + * Controls whether the processor uses sleep or deep sleep as its low-power mode. */ + SCB->SCR = (SCB->SCR & (~(SCB_SCR_SLEEPDEEPS_Msk | SCB_SCR_SLEEPDEEP_Msk))) | + ((SCB_SCR_SLEEPDEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk) | + ((SCB_SCR_SLEEPDEEP_VAL << SCB_SCR_SLEEPDEEP_Pos) & SCB_SCR_SLEEPDEEP_Msk); + +#if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + + /* Configure whether non-secure projects have access to system reset, whether bus fault, hard fault, and NMI target + * secure or non-secure, and whether non-secure interrupt priorities are reduced to the lowest 8 priority levels. */ + SCB->AIRCR = (SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk))) | + BSP_PRV_AIRCR_VECTKEY | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); +#endif + + SCB->SHCSR = (SCB->SHCSR & (~(SCB_SHCSR_SECUREFAULTENA_Msk))) | + ((SCB_SHCSR_SECUREFAULTENA_VAL << SCB_SHCSR_SECUREFAULTENA_Pos) & SCB_SHCSR_SECUREFAULTENA_Msk); + +#if defined(__FPU_USED) && (__FPU_USED == 1U) && \ + defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + /* Configure whether the FPU can be accessed in the non-secure project. */ + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + /* Configure whether FPU registers are always treated as non-secure (and therefore not preserved on the stack when + * switching from secure to non-secure), and whether the FPU registers should be cleared on exception return. */ + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); +#endif + + /* Initialize security attribution registers for Pins. */ + R_BSP_PinCfgSecurityInit(); +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_PinCfgSecurityInit (void) +{ +} diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_security.h b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_security.h new file mode 100644 index 00000000..1b81cfd9 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/all/bsp_security.h @@ -0,0 +1,268 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_SECURITY_H +#define BSP_SECURITY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * set access control level + * + * @param ip enum value to set access control level. + * @param level access control level(0, 1, 2, 3). + * The processes that can be performed at each access control level are as follows. + * RD: Read is allowed, WR: Write is allowed, None: Both RD and WR are not allowed. + * ******************************************************** + * *level * non secure * secure * + * * * user * privileged * user * privileged * + * ******************************************************** + * * 0 * RD+WR * RD+WR * RD+WR * RD+WR * + * * 1 * None * RD+WR * RD+WR * RD+WR * + * * 2 * None * None * RD+WR * RD+WR * + * * 3 * None * None * None * RD+WR * + *********************************************************************************************************************/ +#define R_BSP_ACCESS_CONTROL_SET(ip, level) {BSP_ACCESS_CONTROL_REG_ ## ip = (BSP_ACCESS_CONTROL_REG_ ## ip \ + & ~((uint32_t) 0x3 << \ + BSP_ACCESS_CONTROL_POS_ ## ip)) \ + | ((level) << \ + BSP_ACCESS_CONTROL_POS_ ## ip); \ +} + +#ifndef BSP_OVERRIDE_BSP_ACCESS_CONTROL + + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM0 (R_SYSC->SYS_SLVACCCTL0) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM0 (R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM1 (R_SYSC->SYS_SLVACCCTL0) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM1 (R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC0 (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC0 (R_SYSC_SYS_SLVACCCTL1_TZC0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC1 (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC1 (R_SYSC_SYS_SLVACCCTL1_TZC1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC2 (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC2 (R_SYSC_SYS_SLVACCCTL1_TZC2_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC3 (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC3 (R_SYSC_SYS_SLVACCCTL1_TZC3_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_CST (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_CST (R_SYSC_SYS_SLVACCCTL1_CST_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_CPG (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_CPG (R_SYSC_SYS_SLVACCCTL1_CPG_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SYSC (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SYSC (R_SYSC_SYS_SLVACCCTL1_SYSC_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SYC (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SYC (R_SYSC_SYS_SLVACCCTL1_SYS_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_GIC (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_GIC (R_SYSC_SYS_SLVACCCTL1_GIC_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_IA55_IM33 (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_IA55_IM33 (R_SYSC_SYS_SLVACCCTL1_IA55_IM33_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_GPIO (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_GPIO (R_SYSC_SYS_SLVACCCTL1_GPIO_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_MHU (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_MHU (R_SYSC_SYS_SLVACCCTL1_MHU_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_DMAC0 (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_DMAC0 (R_SYSC_SYS_SLVACCCTL1_DMAC0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_DMAC1 (R_SYSC->SYS_SLVACCCTL1) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_DMAC1 (R_SYSC_SYS_SLVACCCTL1_DMAC1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM0 (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM0 (R_SYSC_SYS_SLVACCCTL2_OSTM0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM1 (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM1 (R_SYSC_SYS_SLVACCCTL2_OSTM1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM2 (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM2 (R_SYSC_SYS_SLVACCCTL2_OSTM2_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT0 (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT0 (R_SYSC_SYS_SLVACCCTL2_WDT0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT1 (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT1 (R_SYSC_SYS_SLVACCCTL2_WDT1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT2 (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT2 (R_SYSC_SYS_SLVACCCTL2_WDT2_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_MTU3A (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_MTU3A (R_SYSC_SYS_SLVACCCTL2_MTU3A_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_POE3 (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_POE3 (R_SYSC_SYS_SLVACCCTL2_POE3_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_GPT (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_GPT (R_SYSC_SYS_SLVACCCTL2_GPT_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_POEG (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_POEG (R_SYSC_SYS_SLVACCCTL2_POEG_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_DDR (R_SYSC->SYS_SLVACCCTL2) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_DDR (R_SYSC_SYS_SLVACCCTL2_DDR_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_GPU (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_GPU (R_SYSC_SYS_SLVACCCTL3_GPU_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_H264 (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_H264 (R_SYSC_SYS_SLVACCCTL3_H264_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_CRU (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_CRU (R_SYSC_SYS_SLVACCCTL3_CRU_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_ISU (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_ISU (R_SYSC_SYS_SLVACCCTL3_ISU_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_DSIPHY (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_DSIPHY (R_SYSC_SYS_SLVACCCTL3_DSIPHY_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_DSILINK (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_DSILINK (R_SYSC_SYS_SLVACCCTL3_DSILINK_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_LCDC (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_LCDC (R_SYSC_SYS_SLVACCCTL3_LCDC_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_USBT (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_USBT (R_SYSC_SYS_SLVACCCTL3_USBT_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_USB20 (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_USB20 (R_SYSC_SYS_SLVACCCTL3_USB20_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_USB21 (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_USB21 (R_SYSC_SYS_SLVACCCTL3_USB21_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SDHI0 (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SDHI0 (R_SYSC_SYS_SLVACCCTL3_SDHI0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SDHI1 (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SDHI1 (R_SYSC_SYS_SLVACCCTL3_SDHI1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_ETH0 (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_ETH0 (R_SYSC_SYS_SLVACCCTL3_ETH0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_ETH1 (R_SYSC->SYS_SLVACCCTL3) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_ETH1 (R_SYSC_SYS_SLVACCCTL3_ETH1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C0 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C0 (R_SYSC_SYS_SLVACCCTL4_I2C0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C1 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C1 (R_SYSC_SYS_SLVACCCTL4_I2C1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C2 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C2 (R_SYSC_SYS_SLVACCCTL4_I2C2_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C3 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C3 (R_SYSC_SYS_SLVACCCTL4_I2C3_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_CANFD (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_CANFD (R_SYSC_SYS_SLVACCCTL4_CANFD_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI (R_SYSC_SYS_SLVACCCTL4_RSPI_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF0 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF0 (R_SYSC_SYS_SLVACCCTL4_SCIF0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF1 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF1 (R_SYSC_SYS_SLVACCCTL4_SCIF1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF2 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF2 (R_SYSC_SYS_SLVACCCTL4_SCIF2_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF3 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF3 (R_SYSC_SYS_SLVACCCTL4_SCIF3_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF4 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF4 (R_SYSC_SYS_SLVACCCTL4_SCIF4_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCI0 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCI0 (R_SYSC_SYS_SLVACCCTL4_SCI0_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCI1 (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCI1 (R_SYSC_SYS_SLVACCCTL4_SCI1_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_IRDA (R_SYSC->SYS_SLVACCCTL4) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_IRDA (R_SYSC_SYS_SLVACCCTL4_IRDA_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF (R_SYSC->SYS_SLVACCCTL5) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF (R_SYSC_SYS_SLVACCCTL5_SSIF_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_SRC (R_SYSC->SYS_SLVACCCTL5) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_SRC (R_SYSC_SYS_SLVACCCTL5_SRC_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_ADC (R_SYSC->SYS_SLVACCCTL6) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_ADC (R_SYSC_SYS_SLVACCCTL6_ADC_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_TSU (R_SYSC->SYS_SLVACCCTL6) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_TSU (R_SYSC_SYS_SLVACCCTL6_TSU_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_OTP (R_SYSC->SYS_SLVACCCTL7) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_OTP (R_SYSC_SYS_SLVACCCTL7_OTP_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_CM33 (R_SYSC->SYS_SLVACCCTL8) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_CM33 (R_SYSC_SYS_SLVACCCTL8_CM33_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_CA55 (R_SYSC->SYS_SLVACCCTL8) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_CA55 (R_SYSC_SYS_SLVACCCTL8_CA55_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_LSI (R_SYSC->SYS_SLVACCCTL10) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_LSI (R_SYSC_SYS_SLVACCCTL10_LSI_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_AOF (R_SYSC->SYS_SLVACCCTL12) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_AOF (R_SYSC_SYS_SLVACCCTL12_AOF_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_LP (R_SYSC->SYS_SLVACCCTL13) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_LP (R_SYSC_SYS_SLVACCCTL13_LP_SL_Pos) + #define BSP_ACCESS_CONTROL_REG_ACCCNT_GPREG (R_SYSC->SYS_SLVACCCTL14) + #define BSP_ACCESS_CONTROL_POS_ACCCNT_GPREG (R_SYSC_SYS_SLVACCCTL14_GPREG_SL_Pos) + +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_BSP_ACC_CONTROL_IP_T + +/** access control. */ +typedef enum e_acc_control_ip +{ + ACCCNT_SRAM0 = 0, ///< + ACCCNT_SRAM1, + ACCCNT_TZC0, + ACCCNT_TZC1, + ACCCNT_TZC2, + ACCCNT_TZC3, + ACCCNT_CST, + ACCCNT_CPG, + ACCCNT_SYSC, + ACCCNT_SYC, + ACCCNT_GIC, + ACCCNT_IA55_IM33, + ACCCNT_GPIO, + ACCCNT_MHU, + ACCCNT_DMAC0, + ACCCNT_DMAC1, + ACCCNT_OSTM0, + ACCCNT_OSTM1, + ACCCNT_OSTM2, + ACCCNT_WDT0, + ACCCNT_WDT1, + ACCCNT_WDT2, + ACCCNT_MTU3A, + ACCCNT_POE3, + ACCCNT_GPT, + ACCCNT_POEG, + ACCCNT_DDR, + ACCCNT_GPU, + ACCCNT_H264, + ACCCNT_CRU, + ACCCNT_ISU, + ACCCNT_DSIPHY, + ACCCNT_DSILINK, + ACCCNT_LCDC, + ACCCNT_USBT, + ACCCNT_USB20, + ACCCNT_USB21, + ACCCNT_SDHI0, + ACCCNT_SDHI1, + ACCCNT_ETH0, + ACCCNT_ETH1, + ACCCNT_I2C0, + ACCCNT_I2C1, + ACCCNT_I2C2, + ACCCNT_I2C3, + ACCCNT_CANFD, + ACCCNT_RSPI, + ACCCNT_SCIF0, + ACCCNT_SCIF1, + ACCCNT_SCIF2, + ACCCNT_SCIF3, + ACCCNT_SCIF4, + ACCCNT_SCI0, + ACCCNT_SCI1, + ACCCNT_IRDA, + ACCCNT_SSIF, + ACCCNT_SRC, + ACCCNT_ADC, + ACCCNT_TSU, + ACCCNT_OTP, + ACCCNT_CM33, + ACCCNT_CA55, + ACCCNT_LSI, + ACCCNT_AOF, + ACCCNT_LP, + ACCCNT_GPREG, +} fsp_acc_control_ip_t; + +#endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* BSP_SECURITY_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_dmac.h b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_dmac.h new file mode 100644 index 00000000..bba32ede --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_dmac.h @@ -0,0 +1,563 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_dmac.h + * Version : 1.00 + * Description : bsp_dmac header + *********************************************************************************************************************/ + +#ifndef BSP_DMAC_H +#define BSP_DMAC_H + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * @addtogroup BSP_MPU_RZG3S + * @{ + *********************************************************************************************************************/ + +#define ACK_MODE_LEVEL_MODE (1 << 16) +#define ACK_MODE_BUS_CYCLE_MODE (2 << 16) +#define ACK_MODE_MASK_DACK_OUTPUT (4 << 16) + +#define DETECTION_RISING_EDGE (2 << 24) +#define DETECTION_HIGH_LEVEL (6 << 24) + +#define R_BSP_DMAC_ACTIVATION_SOURCE_ENABLE(unit, channel, activation) {if (0 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS0 &= \ + ~((uint32_t) ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * (channel % 2))); \ + R_DMAC_B0_EX->DMARS0 |= \ + (uint32_t) ((activation \ + & ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ + << \ + (16U * \ + (channel % \ + 2))); \ + R_DMAC_B0->GRP[channel / \ + 8].CH[ \ + channel % \ + 8].CHCFG |= \ + ((((activation >> 16U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ + ((( \ + activation \ + >> \ + 24U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ + } \ + else if (1 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS1 &= \ + ~((uint32_t) ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * (channel % 2))); \ + R_DMAC_B0_EX->DMARS1 |= \ + (uint32_t) ((activation \ + & ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ + << \ + (16U * \ + (channel % \ + 2))); \ + R_DMAC_B0->GRP[channel / \ + 8].CH[ \ + channel % \ + 8].CHCFG |= \ + ((((activation >> 16U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ + ((( \ + activation \ + >> \ + 24U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ + } \ + else if (2 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS2 &= \ + ~((uint32_t) ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * (channel % 2))); \ + R_DMAC_B0_EX->DMARS2 |= \ + (uint32_t) ((activation \ + & ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ + << \ + (16U * \ + (channel % \ + 2))); \ + R_DMAC_B0->GRP[channel / \ + 8].CH[ \ + channel % \ + 8].CHCFG |= \ + ((((activation >> 16U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ + ((( \ + activation \ + >> \ + 24U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ + } \ + else if (3 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS3 &= \ + ~((uint32_t) ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * (channel % 2))); \ + R_DMAC_B0_EX->DMARS3 |= \ + (uint32_t) ((activation \ + & ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ + << \ + (16U * \ + (channel % \ + 2))); \ + R_DMAC_B0->GRP[channel / \ + 8].CH[ \ + channel % \ + 8].CHCFG |= \ + ((((activation >> 16U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ + ((( \ + activation \ + >> \ + 24U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ + } \ + else if (4 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS4 &= \ + ~((uint32_t) ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * (channel % 2))); \ + R_DMAC_B0_EX->DMARS4 |= \ + (uint32_t) ((activation \ + & ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ + << \ + (16U * \ + (channel % \ + 2))); \ + R_DMAC_B0->GRP[channel / \ + 8].CH[ \ + channel % \ + 8].CHCFG |= \ + ((((activation >> 16U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ + ((( \ + activation \ + >> \ + 24U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ + } \ + else if (5 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS5 &= \ + ~((uint32_t) ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * (channel % 2))); \ + R_DMAC_B0_EX->DMARS5 |= \ + (uint32_t) ((activation \ + & ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ + << \ + (16U * \ + (channel % \ + 2))); \ + R_DMAC_B0->GRP[channel / \ + 8].CH[ \ + channel % \ + 8].CHCFG |= \ + ((((activation >> 16U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ + ((( \ + activation \ + >> \ + 24U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ + } \ + else if (6 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS6 &= \ + ~((uint32_t) ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * (channel % 2))); \ + R_DMAC_B0_EX->DMARS6 |= \ + (uint32_t) ((activation \ + & ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ + << \ + (16U * \ + (channel % \ + 2))); \ + R_DMAC_B0->GRP[channel / \ + 8].CH[ \ + channel % \ + 8].CHCFG |= \ + ((((activation >> 16U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ + ((( \ + activation \ + >> \ + 24U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ + } \ + else if (7 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS7 &= \ + ~((uint32_t) ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * (channel % 2))); \ + R_DMAC_B0_EX->DMARS7 |= \ + (uint32_t) ((activation \ + & ( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ + << \ + (16U * \ + (channel % \ + 2))); \ + R_DMAC_B0->GRP[channel / \ + 8].CH[ \ + channel % \ + 8].CHCFG |= \ + ((((activation >> 16U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ + ((( \ + activation \ + >> \ + 24U) & 0x7U) << \ + R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ + } \ + else { /* Do nothing */} \ +} \ + + +#define R_BSP_DMAC_ACTIVATION_SOURCE_DISABLE(unit, channel) {if (0 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS0 &= \ + (uint32_t) ~(( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * \ + (channel % 2))); \ + } \ + else if (1 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS1 &= \ + (uint32_t) ~(( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * \ + (channel % 2))); \ + } \ + else if (2 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS2 &= \ + (uint32_t) ~(( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * \ + (channel % 2))); \ + } \ + else if (3 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS3 &= \ + (uint32_t) ~(( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * \ + (channel % 2))); \ + } \ + else if (4 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS4 &= \ + (uint32_t) ~(( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * \ + (channel % 2))); \ + } \ + else if (5 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS5 &= \ + (uint32_t) ~(( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * \ + (channel % 2))); \ + } \ + else if (6 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS6 &= \ + (uint32_t) ~(( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * \ + (channel % 2))); \ + } \ + else if (7 == (channel / 2)) { \ + R_DMAC_B0_EX->DMARS7 &= \ + (uint32_t) ~(( \ + R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ + | \ + R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ + << (16U * \ + (channel % 2))); \ + } \ + else { /* Do nothing */} \ +} \ + +#define R_BSP_DMAC_DREQ_DETECT_METHOD_SELECT(detection, \ + activation) { /* No configuration required for this device. */; \ +} \ + +#define R_BSP_DMAC_B_TRANSFER_END_DETECT_METHOD_SELECT(unit, channel, \ + dmaint_detect) { /* No configuration required for this device. */; \ +} \ + +#define R_BSP_DMAC_DREQ_STATUS_CLEAR(activation) { /* No clearing required for this device. */; \ +} \ + +typedef enum e_dmac_trigger_event +{ + DMAC_TRIGGER_EVENT_SOFTWARE_TRIGGER = 0, + DMAC_TRIGGER_EVENT_GTM_OSTM0TINT = 35 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GTM_OSTM1TINT = 39 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GTM_OSTM2TINT = 43 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GTM_OSTM3TINT = 47 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GTM_OSTM4TINT = 51 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GTM_OSTM5TINT = 55 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GTM_OSTM6TINT = 59 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GTM_OSTM7TINT = 63 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIA0 = 67 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIB0 = 71 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIC0 = 75 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGID0 = 79 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIA1 = 83 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIB1 = 87 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIA2 = 91 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIB2 = 95 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIA3 = 99 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIB3 = 103 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIC3 = 107 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGID3 = 111 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIA4 = 115 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIB4 = 119 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIC4 = 123 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGID4 = 127 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TCIV4 = 131 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIU5 = 135 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIV5 = 139 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIW5 = 143 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIA6 = 147 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIB6 = 151 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIC6 = 155 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGID6 = 159 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIA7 = 163 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIB7 = 167 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIC7 = 171 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGID7 = 175 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TCIV7 = 179 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIA8 = 183 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIB8 = 187 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGIC8 = 191 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_MTU3_TGID8 = 195 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPA0 = 199 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPB0 = 203 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPC0 = 207 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPD0 = 211 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPE0 = 215 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPF0 = 219 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGA0 = 223 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGB0 = 227 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_OVF0 = 231 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_UNF0 = 235 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPA1 = 251 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPB1 = 255 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPC1 = 259 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPD1 = 263 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPE1 = 267 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPF1 = 271 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGA1 = 275 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGB1 = 279 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_OVF1 = 283 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_UNF1 = 287 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPA2 = 303 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPB2 = 307 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPC2 = 311 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPD2 = 315 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPE2 = 319 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPF2 = 323 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGA2 = 327 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGB2 = 331 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_OVF2 = 335 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_UNF2 = 339 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPA3 = 355 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPB3 = 359 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPC3 = 363 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPD3 = 367 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPE3 = 371 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPF3 = 375 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGA3 = 379 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGB3 = 384 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_OVF3 = 387 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_UNF3 = 391 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPA4 = 407 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPB4 = 411 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPC4 = 415 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPD4 = 419 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPE4 = 423 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPF4 = 427 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGA4 = 431 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGB4 = 435 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_OVF4 = 439 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_UNF4 = 443 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPA5 = 459 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPB5 = 463 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPC5 = 467 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPD5 = 471 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPE5 = 475 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPF5 = 479 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGA5 = 483 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGB5 = 487 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_OVF5 = 491 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_UNF5 = 495 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPA6 = 511 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPB6 = 515 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPC6 = 519 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPD6 = 523 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPE6 = 527 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPF6 = 531 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGA6 = 535 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGB6 = 539 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_OVF6 = 543 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_UNF6 = 547 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPA7 = 563 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CCMPB7 = 567 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPC7 = 571 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPD7 = 575 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPE7 = 579 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_CMPF7 = 583 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGA7 = 587 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_ADTRGB7 = 591 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_OVF7 = 595 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_GPT_UNF7 = 599 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SSIF_DMA_RX0 = 614 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SSIF_DMA_TX0 = 613 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SSIF_DMA_RX1 = 618 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SSIF_DMA_TX1 = 617 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SSIF_DMA_RX2 = 622 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SSIF_DMA_TX2 = 621 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SSIF_DMA_RX3 = 626 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SSIF_DMA_TX3 = 625 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SRC_IDEI = 630 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SRC_ODFI = 629 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I2C_INTRIIC_RI0 = 650 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I2C_INTRIIC_TI0 = 649 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I2C_INTRIIC_RI1 = 654 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I2C_INTRIIC_TI1 = 653 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I2C_INTRIIC_RI2 = 658 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I2C_INTRIIC_TI2 = 657 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I2C_INTRIIC_RI3 = 662 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I2C_INTRIIC_TI3 = 661 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTRESP = 667 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTCMD = 671 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTIBI = 675 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTRX = 678 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTTX = 677 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTRCV = 683 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTHRESP = 687 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTHCMD = 691 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTHRX = 694 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_I3C_INTHTX = 693 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SCIF_RXI0 = 698 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_TXI0 = 697 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_RXI1 = 702 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_TXI1 = 701 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_RXI2 = 706 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_TXI2 = 705 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_RXI3 = 710 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_TXI3 = 709 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_RXI4 = 714 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_TXI4 = 713 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_RXI5 = 718 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIF_TXI5 = 717 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIg_RXI0 = 722 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIg_TXI0 = 721 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIg_RXI1 = 726 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SCIg_TXI1 = 725 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPRI0 = 730 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPTI0 = 729 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPRI1 = 734 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPTI1 = 733 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPRI2 = 738 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPTI2 = 737 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPRI3 = 742 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPTI3 = 741 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPRI4 = 746 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_RSPI_SPTI4 = 745 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_CANFD_RXF_DMA0 = 751 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_RXF_DMA1 = 755 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_RXF_DMA2 = 759 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_RXF_DMA3 = 763 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_RXF_DMA4 = 767 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_RXF_DMA5 = 771 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_RXF_DMA6 = 775 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_RXF_DMA7 = 779 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_COM_DMA0 = 783 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_CANFD_COM_DMA1 = 787 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, + DMAC_TRIGGER_EVENT_SPDIF_RBDMAREQN_TX = 633 | ACK_MODE_LEVEL_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_SPDIF_RBDMAREQN_RX = 634 | ACK_MODE_LEVEL_MODE | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_PDM_INT_PDM_DAT0 = 639 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_PDM_INT_PDM_DAT1 = 643 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, + DMAC_TRIGGER_EVENT_PDM_INT_PDM_DAT2 = 647 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, +} dmac_trigger_event_t; + +/** @} (end addtogroup BSP_MPU_RZG3S) */ + +#endif /* BSP_DMAC_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_feature.h b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_feature.h new file mode 100644 index 00000000..e5c3f05b --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_feature.h @@ -0,0 +1,198 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_feature.h + * Version : 1.00 + * Description : bsp_feature header + *********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/* ADC-Related Definitions */ +#define BSP_FEATURE_ADC_VALID_CHANNEL_MASK (0xFFF) +#define BSP_FEATURE_ADC_NUM_CALIBRATION_DATA (2U) +#define BSP_FEATURE_ADC_NUM_CHANNELS (12U) +#define BSP_FEATURE_ADC_C_VALID_CHANNEL_MASK (0xFFF) +#define BSP_FEATURE_ADC_C_NUM_CHANNELS (12U) +#define BSP_FEATURE_ADC_C_SAMPLE_STATE_COUNT_MIN (79U) +#define BSP_FEATURE_ADC_C_SAMPLE_STATE_COUNT_MAX (255U) +#define BSP_FEATURE_ADC_C_CONVERSION_TIME (29U) +#define BSP_FEATURE_ADC_C_HAS_ADIVC (0U) +#define BSP_FEATURE_ADC_C_TSU_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_C_TSU_ENABLE_STABILIZATION_TIME_US (30U) +#define BSP_FEATURE_ADC_C_TSU_START_STABILIZATION_TIME_MS (1U) + +/* BSP Capabilities Definitions */ +#define BSP_FEATURE_BSP_CLOCK_FREQ_INIT_CFG_SUPPORT (1U) +#define BSP_FEATURE_BSP_HAS_ELC (0U) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0U) +#define BSP_FEATURE_BSP_SLAVE_ADDRESS_CONVERSION_SUPPORT (1U) +#define BSP_FEATURE_BSP_SUPPORT_SD_VOLT (1U) +#define BSP_FEATURE_BSP_SUPPORT_ETHER_VOLT (1U) +#define BSP_FEATURE_BSP_SUPPORT_ETHER_MODE (1U) +#define BSP_FEATURE_BSP_SUPPORT_QSPI_VOLT (0U) +#define BSP_FEATURE_BSP_SUPPORT_XSPI_VOLT (1U) +#define BSP_FEATURE_BSP_SUPPORT_XSPI_OUTPUT (0U) +#define BSP_FEATURE_BSP_SUPPORT_I3C (1U) +#define BSP_FEATURE_BSP_SUPPORT_BYPASS (0U) +#define BSP_FEATURE_BSP_SUPPORT_PFCWE_PROTECT (1U) +#define BSP_FEATURE_BSP_SUPPORT_OEN_PROTECT (0U) +#define BSP_FEATURE_BSP_HAS_PFC_OEN_REG (0U) +#define BSP_FEATURE_BSP_HAS_ETHER_MODE_REG (1U) +#define BSP_FEATURE_BSP_HAS_SD_CH_POC_REG (1U) +#define BSP_FEATURE_BSP_HAS_ETH_POC_REG (1U) + +/* CANFD-Related Definitions */ +#define BSP_FEATURE_CANFD_NUM_CHANNELS (2) +#define BSP_FEATURE_CANFD_FD_SUPPORT (1) +#define BSP_FEATURE_CANFD_LITE (0U) +#define BSP_FEATURE_CANFD_NUM_INSTANCES (1U) +#define BSP_FEATURE_CANFD_HAS_RSCANFD (0U) +#define BSP_FEATURE_CANFD_TXMB_OFFSET (32U) +#define BSP_FEATURE_CANFD_TXMB_CHANNEL_OFFSET (64U) +#define BSP_FEATURE_CANFD_RXMB_MAX (32U) + +/* Cortex-M33 Feature Definitions */ +#define BSP_FEATURE_MCORE_HAS_DSP (0U) +#if BSP_CURRENT_CORE == RZG3S_CORE_CM33 + #define BSP_FEATURE_MCORE_HAS_FPU (0U) + #define BSP_FEATURE_CURRENT_CORE_IS_CM33_FPU (0U) +#elif BSP_CURRENT_CORE == RZG3S_CORE_CM33_FPU + #define BSP_FEATURE_MCORE_HAS_FPU (1U) + #define BSP_FEATURE_CURRENT_CORE_IS_CM33_FPU (1U) +#endif + +/* CPG-Related Definitions */ +#define BSP_FEATURE_CPG_HAS_ICLK (1U) +#define BSP_FEATURE_CPG_HAS_I2CLK (1U) +#define BSP_FEATURE_CPG_HAS_I3CLK (1U) +#define BSP_FEATURE_CPG_HAS_GCLK (0U) +#define BSP_FEATURE_CPG_HAS_S0CLK (1U) +#define BSP_FEATURE_CPG_HAS_OC0CLK (1U) +#define BSP_FEATURE_CPG_HAS_OC1CLK (1U) +#define BSP_FEATURE_CPG_HAS_SPI0CLK (1U) +#define BSP_FEATURE_CPG_HAS_SPI1CLK (1U) +#define BSP_FEATURE_CPG_HAS_SD0CLK (1U) +#define BSP_FEATURE_CPG_HAS_SD1CLK (1U) +#define BSP_FEATURE_CPG_HAS_SD2CLK (1U) +#define BSP_FEATURE_CPG_HAS_M0CLK (1U) +#define BSP_FEATURE_CPG_HAS_M1CLK (0U) +#define BSP_FEATURE_CPG_HAS_M2CLK (0U) +#define BSP_FEATURE_CPG_HAS_M3CLK (0U) +#define BSP_FEATURE_CPG_HAS_M4CLK (0U) +#define BSP_FEATURE_CPG_HAS_HPCLK (1U) +#define BSP_FEATURE_CPG_HAS_TSUCLK (1U) +#define BSP_FEATURE_CPG_HAS_ZTCLK (1U) +#define BSP_FEATURE_CPG_HAS_P0CLK (1U) +#define BSP_FEATURE_CPG_HAS_P1CLK (1U) +#define BSP_FEATURE_CPG_HAS_P2CLK (1U) +#define BSP_FEATURE_CPG_HAS_P3CLK (1U) +#define BSP_FEATURE_CPG_HAS_P4CLK (1U) +#define BSP_FEATURE_CPG_HAS_P5CLK (1U) +#define BSP_FEATURE_CPG_HAS_ATCLK (1U) +#define BSP_FEATURE_CPG_HAS_OSCCLK (1U) +#define BSP_FEATURE_CPG_HAS_OSCCLK2 (1U) + +/* DMAC-Related Definitions */ +#define BSP_FEATURE_DMAC_MAX_CHANNEL (16U) +#define BSP_FEATURE_DMAC_MAX_UNIT (2U) + +/* GPT-Related Definitions */ +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0xFFU) +#define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) + +/* GTM-Related Definitions */ +#define BSP_FEATURE_GTM_VALID_CHANNEL_MASK (0xFFU) + +/* IIC-Related Definitions */ +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x0F) + +/* INTC-Related Definitions */ +#define BSP_FEATURE_INTC_IRQ_VALID_CHANNEL_MASK (0xFFU) + +/* IOPORT-Related Definitions */ +#define BSP_FEATURE_IOPORT_SUPPORT_SR_REG (0U) +#define BSP_FEATURE_IOPORT_GP_REG_BASE_NUM _20 +#define BSP_FEATURE_IOPORT_SP_REG_BASE_NUM 1 +#define BSP_FEATURE_IOPORT_FIL_SP_REG_BASE_NUM _00 +#define BSP_FEATURE_IOPORT_IEN_SP_REG_BASE_NUM _01 +#define BSP_FEATURE_IOPORT_IOLH_SP_REG_BASE_NUM _01 +#define BSP_FEATURE_IOPORT_SR_SP_REG_BASE_NUM 0 + +/* MHU-Related Definitions */ +#if BSP_CURRENT_CORE == RZG3S_CORE_CM33 + #define BSP_FEATURE_MHU_NS_VALID_CHANNEL_MASK (0x3AU) + #define BSP_FEATURE_MHU_NS_SEND_TYPE_RSP_VALID_CHANNEL_MASK (0x0AU) + #define BSP_FEATURE_MHU_NS_SWINT_GET_VALID_CHANNEL_MASK (0x03U) + #define BSP_FEATURE_MHU_NS_SWINT_SET_VALID_CHANNEL_MASK (0x0CU) + #define BSP_FEATURE_MHU_S_VALID_CHANNEL_MASK (0x3AU) + #define BSP_FEATURE_MHU_S_SEND_TYPE_RSP_VALID_CHANNEL_MASK (0x0AU) +#elif BSP_CURRENT_CORE == RZG3S_CORE_CM33_FPU + #define BSP_FEATURE_MHU_NS_VALID_CHANNEL_MASK (0x2DU) + #define BSP_FEATURE_MHU_NS_SEND_TYPE_RSP_VALID_CHANNEL_MASK (0x21U) + #define BSP_FEATURE_MHU_NS_SWINT_GET_VALID_CHANNEL_MASK (0x28U) + #define BSP_FEATURE_MHU_NS_SWINT_SET_VALID_CHANNEL_MASK (0x12U) + #define BSP_FEATURE_MHU_S_VALID_CHANNEL_MASK (0x2DU) + #define BSP_FEATURE_MHU_S_SEND_TYPE_RSP_VALID_CHANNEL_MASK (0x21U) +#endif + +/* POEG-Related Definitions */ +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +/* RSPI-Related Definitions */ +#define BSP_FEATURE_RSPI_VALID_CHANNELS_MASK (0x1FU) +#define BSP_FEATURE_RSPI_CLOCK (FSP_PRIV_CLOCK_P0CLK) +#define BSP_FEATURE_RSPI_CLK_MAX_DIV (4096U) +#define BSP_FEATURE_RSPI_CLK_MIN_DIV (4U) + +/* SCIF-Related Definitions */ +#define BSP_FEATURE_SCIF_CHANNELS (0x3FU) +#define BSP_FEATURE_SCIF_CHANNELS_HAS_RTSCTS (0x07U) +#define BSP_FEATURE_SCIF_CLOCK (FSP_PRIV_CLOCK_P0CLK) + +/* SSI-Related Definitions */ +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0x0FU) + +/* TrustZone-Related Definitions */ +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + +/* WDT-Related Definitions */ +#define BSP_FEATURE_WDT_MAX_CHANNELS (2U) + +#define BSP_FEATURE_XSPI_CHANNELS (0x01U) +#define BSP_FEATURE_XSPI_NUM_CHIP_SELECT (2U) +#define BSP_FEATURE_XSPI_NUM_UNITS (1U) +#define BSP_FEATURE_XSPI_DO_NOT_HAS_CSSCTL (1U) +#define BSP_FEATURE_XSPI_START_ADDRESS (0x80000000) +#define BSP_FEATURE_XSPI_DEVICE_CS0_1_ADDRESS_DELTA (0x08000000) + +#endif /* BSP_FEATURE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_irq_id.h b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_irq_id.h new file mode 100644 index 00000000..8a880d37 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_irq_id.h @@ -0,0 +1,582 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_irq_id.h + * Version : 1.00 + * Description : bsp_irq_id header + *********************************************************************************************************************/ + +#ifndef BSP_IRQ_ID_H +#define BSP_IRQ_ID_H + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ +#define DMAC_B0_DMAINT0_IRQn DMAC_DMAINT0_S_IRQn +#define DMAC_B0_DMAINT1_IRQn DMAC_DMAINT1_S_IRQn +#define DMAC_B0_DMAINT2_IRQn DMAC_DMAINT2_S_IRQn +#define DMAC_B0_DMAINT3_IRQn DMAC_DMAINT3_S_IRQn +#define DMAC_B0_DMAINT4_IRQn DMAC_DMAINT4_S_IRQn +#define DMAC_B0_DMAINT5_IRQn DMAC_DMAINT5_S_IRQn +#define DMAC_B0_DMAINT6_IRQn DMAC_DMAINT6_S_IRQn +#define DMAC_B0_DMAINT7_IRQn DMAC_DMAINT7_S_IRQn +#define DMAC_B0_DMAINT8_IRQn DMAC_DMAINT8_S_IRQn +#define DMAC_B0_DMAINT9_IRQn DMAC_DMAINT9_S_IRQn +#define DMAC_B0_DMAINT10_IRQn DMAC_DMAINT10_S_IRQn +#define DMAC_B0_DMAINT11_IRQn DMAC_DMAINT11_S_IRQn +#define DMAC_B0_DMAINT12_IRQn DMAC_DMAINT12_S_IRQn +#define DMAC_B0_DMAINT13_IRQn DMAC_DMAINT13_S_IRQn +#define DMAC_B0_DMAINT14_IRQn DMAC_DMAINT14_S_IRQn +#define DMAC_B0_DMAINT15_IRQn DMAC_DMAINT15_S_IRQn +#define DMAC_B1_DMAINT0_IRQn DMAC_DMAINT0_NS_IRQn +#define DMAC_B1_DMAINT1_IRQn DMAC_DMAINT1_NS_IRQn +#define DMAC_B1_DMAINT2_IRQn DMAC_DMAINT2_NS_IRQn +#define DMAC_B1_DMAINT3_IRQn DMAC_DMAINT3_NS_IRQn +#define DMAC_B1_DMAINT4_IRQn DMAC_DMAINT4_NS_IRQn +#define DMAC_B1_DMAINT5_IRQn DMAC_DMAINT5_NS_IRQn +#define DMAC_B1_DMAINT6_IRQn DMAC_DMAINT6_NS_IRQn +#define DMAC_B1_DMAINT7_IRQn DMAC_DMAINT7_NS_IRQn +#define DMAC_B1_DMAINT8_IRQn DMAC_DMAINT8_NS_IRQn +#define DMAC_B1_DMAINT9_IRQn DMAC_DMAINT9_NS_IRQn +#define DMAC_B1_DMAINT10_IRQn DMAC_DMAINT10_NS_IRQn +#define DMAC_B1_DMAINT11_IRQn DMAC_DMAINT11_NS_IRQn +#define DMAC_B1_DMAINT12_IRQn DMAC_DMAINT12_NS_IRQn +#define DMAC_B1_DMAINT13_IRQn DMAC_DMAINT13_NS_IRQn +#define DMAC_B1_DMAINT14_IRQn DMAC_DMAINT14_NS_IRQn +#define DMAC_B1_DMAINT15_IRQn DMAC_DMAINT15_NS_IRQn +#define DMAC_B0_DMAERR_IRQn DMAC_DMAERR_S_IRQn +#define DMAC_B1_DMAERR_IRQn DMAC_DMAERR_NS_IRQn + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * @addtogroup BSP_MPU_RZG2UL + * @{ + *********************************************************************************************************************/ + +typedef enum IRQn +{ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + NMI_IRQn = 0, /* IRQ No:0, NMI */ + GPIO_IRQ0_IRQn = 1, /* IRQ No:1, IRQ0 */ + GPIO_IRQ1_IRQn = 2, /* IRQ No:2, IRQ1 */ + GPIO_IRQ2_IRQn = 3, /* IRQ No:3, IRQ2 */ + GPIO_IRQ3_IRQn = 4, /* IRQ No:4, IRQ3 */ + GPIO_IRQ4_IRQn = 5, /* IRQ No:5, IRQ4 */ + GPIO_IRQ5_IRQn = 6, /* IRQ No:6, IRQ5 */ + GPIO_IRQ6_IRQn = 7, /* IRQ No:7, IRQ6 */ + GPIO_IRQ7_IRQn = 8, /* IRQ No:8, IRQ7 */ + CA55_ERRIRQ1_IRQn = 9, /* IRQ No:9, nERRIRQ[1] */ + CA55_ERRIRQ0_IRQn = 10, /* IRQ No:10, nERRIRQ[0] */ + CA55_FAULTIRQ1_IRQn = 11, /* IRQ No:11, nFAULTIRQ[1] */ + CA55_FAULTIRQ0_IRQn = 12, /* IRQ No:12, nFAULTIRQ[0] */ + CA55_COMMIRQ0_IRQn = 13, /* IRQ No:13, nCOMMIRQ[0] */ + CA55_PMUIRQ0_IRQn = 14, /* IRQ No:14, nPMUIRQ[0] */ + CA55_CLUSTERPMUIRQ_IRQn = 15, /* IRQ No:15, nCLUSTERPMUIRQ */ + CM33_CTIIRQ1_IRQn = 16, /* IRQ No:16, CTIIRQ[1] */ + CM33_CTIIRQ0_IRQn = 17, /* IRQ No:17, CTIIRQ[0] */ + CM33FPU_CTIIRQ1_IRQn = 18, /* IRQ No:18, CTIIRQ[1] */ + CM33FPU_CTIIRQ0_IRQn = 19, /* IRQ No:19, CTIIRQ[0] */ + CM33FPU_FPIXC_IRQn = 20, /* IRQ No:20, FPIXC */ + CM33FPU_FPIDC_IRQn = 21, /* IRQ No:21, FPIDC */ + CM33FPU_FPOFC_IRQn = 22, /* IRQ No:22, FPOFC */ + CM33FPU_FPUFC_IRQn = 23, /* IRQ No:23, FPUFC */ + CM33FPU_FPDZC_IRQn = 24, /* IRQ No:24, FPDZC */ + CM33FPU_FPIOC_IRQn = 25, /* IRQ No:25, FPIOC */ + GIC_FAULT_INT_IRQn = 26, /* IRQ No:26, fault_int */ + GIC_ERR_INT_IRQn = 27, /* IRQ No:27, err_int */ + GIC_PMU_INT_IRQn = 28, /* IRQ No:28, pmu_int */ + SYSTEMBUS_BUS_ERR_INT_IRQn = 29, /* IRQ No:29, BUS_ERR_INT */ + /* IRQ No:30, Reserved */ + ECCRAM_EC7TIE1_IRQn = 31, /* IRQ No:31, EC7TIE1_0 */ + ECCRAM_EC7TIE2_IRQn = 32, /* IRQ No:32, EC7TIE2_0 */ + ECCRAM_EC7TIOVF_IRQn = 33, /* IRQ No:33, EC7TIOVF_0 */ + DDR_CONTROLL_INT_IRQn = 34, /* IRQ No:34, controller_int */ + DDR_DWC_DDRPHY_INT_IRQn = 35, /* IRQ No:35, dwc_ddrphy_int_n */ + DDR_SREF_ERROR_INT_IRQn = 36, /* IRQ No:36, sref_error */ + XSPI_SPI_LEVEL_INT_IRQn = 37, /* IRQ No:37, int_spi_level */ + XSPI_SPI_ERR_LEVEL_INT_IRQn = 38, /* IRQ No:38, int_spi_err_level */ + SYSC_LPM_INT_IRQn = 39, /* IRQ No:39, SYS_LPM_INT */ + SYSC_CA55STBYDONE_INT_IRQn = 40, /* IRQ No:40, SYS_CA55STBYDONE_INT */ + SYSC_CM33STBYR_INT_IRQn = 41, /* IRQ No:41, SYS_CM33STBYR_INT */ + SYSC_CA55_DENY_IRQn = 42, /* IRQ No:42, SYS_CA55_DENY */ + VBATTB_TAMPDI_IRQn = 43, /* IRQ No:43, TAMPDI */ + GTM0_OSTM0INT_IRQn = 44, /* IRQ No:44, OSTM0TINT */ + GTM1_OSTM1INT_IRQn = 45, /* IRQ No:45, OSTM1TINT */ + GTM2_OSTM2INT_IRQn = 46, /* IRQ No:46, OSTM2TINT */ + GTM3_OSTM3INT_IRQn = 47, /* IRQ No:47, OSTM3TINT */ + GTM4_OSTM4INT_IRQn = 48, /* IRQ No:48, OSTM4TINT */ + GTM5_OSTM5INT_IRQn = 49, /* IRQ No:49, OSTM5TINT */ + GTM6_OSTM6INT_IRQn = 50, /* IRQ No:50, OSTM6TINT */ + GTM7_OSTM7INT_IRQn = 51, /* IRQ No:51, OSTM7TINT */ + /* IRQ No:52, PERROUT_A0 */ + /* IRQ No:53, WDTINT_A0 */ + WDT1_PERROUT_IRQn = 54, /* IRQ No:54, PERROUT_M0 */ + WDT1_WDTINT_IRQn = 55, /* IRQ No:55, WDTINT_M0 */ + WDT2_PERROUT_IRQn = 56, /* IRQ No:56, PERROUT_M1 */ + WDT2_WDTINT_IRQn = 57, /* IRQ No:57, WDTINT_M1 */ +#if BSP_CURRENT_CORE == RZG3S_CORE_CM33 + MHU1_NS_IRQn = 58, /* IRQ No:58, msg_ch1_ns */ + MHU3_NS_IRQn = 59, /* IRQ No:59, msg_ch3_ns */ + MHU4_NS_IRQn = 60, /* IRQ No:60, rsp_ch4_ns */ + MHU5_NS_IRQn = 61, /* IRQ No:61, rsp_ch5_ns */ + MHU1_S_IRQn = 62, /* IRQ No:62, msg_ch1_s */ + MHU3_S_IRQn = 63, /* IRQ No:63, msg_ch3_s */ + MHU4_S_IRQn = 64, /* IRQ No:64, rsp_ch4_s */ + MHU5_S_IRQn = 65, /* IRQ No:65, rsp_ch5_s */ + MHU_SW_MHU_INT0_IRQn = 66, /* IRQ No:66, swint_ch0_ns */ + MHU_SW_MHU_INT1_IRQn = 67, /* IRQ No:67, swint_ch1_ns */ +#elif BSP_CURRENT_CORE == RZG3S_CORE_CM33_FPU + MHU0_NS_IRQn = 58, /* IRQ No:58, msg_ch0_ns */ + MHU2_NS_IRQn = 59, /* IRQ No:59, rsp_ch2_ns */ + MHU3_NS_IRQn = 60, /* IRQ No:60, rsp_ch3_ns */ + MHU5_NS_IRQn = 61, /* IRQ No:61, msg_ch5_ns */ + MHU0_S_IRQn = 62, /* IRQ No:62, msg_ch0_s */ + MHU2_S_IRQn = 63, /* IRQ No:63, rsp_ch2_s */ + MHU3_S_IRQn = 64, /* IRQ No:64, rsp_ch3_s */ + MHU5_S_IRQn = 65, /* IRQ No:65, msg_ch5_s */ + MHU_SW_MHU_INT3_IRQn = 66, /* IRQ No:66, swint_ch3_ns */ + MHU_SW_MHU_INT5_IRQn = 67, /* IRQ No:67, swint_ch5_ns */ +#endif /* BSP_CURRENT_CORE */ + ETH0_PIF_INT_N_IRQn = 68, /* IRQ No:68, pif_int_n_ch0 */ + ETH0_FIL_INT_N_IRQn = 69, /* IRQ No:69, int_fil_n_ch0 */ + ETH0_ARP_NS_N_IRQn = 70, /* IRQ No:70, int_arp_ns_n_ch0 */ + ETH1_PIF_INT_N_IRQn = 71, /* IRQ No:71, pif_int_n_ch1 */ + ETH1_FIL_INT_N_IRQn = 72, /* IRQ No:72, int_fil_n_ch1 */ + ETH1_ARP_NS_N_IRQn = 73, /* IRQ No:73, int_arp_ns_n_ch1 */ + USB_U2H0_INT_IRQn = 74, /* IRQ No:74, U2H0_INT */ + USB_U2H0_OHCI_INT_IRQn = 75, /* IRQ No:75, U2H0_OHCI_INT */ + USB_U2H0_EHCI_INT_IRQn = 76, /* IRQ No:76, U2H0_EHCI_INT */ + USB_U2H0_WAKEON_INT_IRQn = 77, /* IRQ No:77, U2H0_WAKEON_INT */ + USB_U2H0_OBINT_IRQn = 78, /* IRQ No:78, U2H0_OBINT */ + USB_U2H1_INT_IRQn = 79, /* IRQ No:79, U2H1_INT */ + USB_U2H1_OHCI_INT_IRQn = 80, /* IRQ No:80, U2H1_OHCI_INT */ + USB_U2H1_EHCI_INT_IRQn = 81, /* IRQ No:81, U2H1_EHCI_INT */ + USB_U2H1_WAKEON_INT_IRQn = 82, /* IRQ No:82, U2H1_WAKEON_INT */ + USB_U2H1_OBINT_IRQn = 83, /* IRQ No:83, U2H1_OBINT */ + USB_U2P_INT_DMAERR_IRQn = 84, /* IRQ No:84, U2P_INT_DMAERR */ + USB_U2P_IXL_INT_IRQn = 85, /* IRQ No:85, U2P_IXL_INT */ + USB_U2P_INT_DMA0_IRQn = 86, /* IRQ No:86, U2P_INT_DMA[0] */ + USB_U2P_INT_DMA1_IRQn = 87, /* IRQ No:87, U2P_INT_DMA[1] */ + SDHI_eMMC0_OXMN_IRQn = 88, /* IRQ No:88, OXMNIRQ0 */ + SDHI_eMMC0_OXASIO_IRQn = 89, /* IRQ No:89, OXASIOIRQ0 */ + SDHI_eMMC1_OXMN_IRQn = 90, /* IRQ No:90, OXMNIRQ1 */ + SDHI_eMMC1_OXASIO_IRQn = 91, /* IRQ No:91, OXASIOIRQ1 */ + SDHI_eMMC2_OXMN_IRQn = 92, /* IRQ No:92, OXMNIRQ1 */ + SDHI_eMMC2_OXASIO_IRQn = 93, /* IRQ No:93, OXASIOIRQ1 */ + DMAC_DMAERR_S_IRQn = 94, /* IRQ No:94, DMAERR_S */ + DMAC_DMAINT0_S_IRQn = 95, /* IRQ No:95, DMAINT0_S */ + DMAC_DMAINT1_S_IRQn = 96, /* IRQ No:96, DMAINT1_S */ + DMAC_DMAINT2_S_IRQn = 97, /* IRQ No:97, DMAINT2_S */ + DMAC_DMAINT3_S_IRQn = 98, /* IRQ No:98, DMAINT3_S */ + DMAC_DMAINT4_S_IRQn = 99, /* IRQ No:99, DMAINT4_S */ + DMAC_DMAINT5_S_IRQn = 100, /* IRQ No:100, DMAINT5_S */ + DMAC_DMAINT6_S_IRQn = 101, /* IRQ No:101, DMAINT6_S */ + DMAC_DMAINT7_S_IRQn = 102, /* IRQ No:102, DMAINT7_S */ + DMAC_DMAINT8_S_IRQn = 103, /* IRQ No:103, DMAINT8_S */ + DMAC_DMAINT9_S_IRQn = 104, /* IRQ No:104, DMAINT9_S */ + DMAC_DMAINT10_S_IRQn = 105, /* IRQ No:105, DMAINT10_S */ + DMAC_DMAINT11_S_IRQn = 106, /* IRQ No:106, DMAINT11_S */ + DMAC_DMAINT12_S_IRQn = 107, /* IRQ No:107, DMAINT12_S */ + DMAC_DMAINT13_S_IRQn = 108, /* IRQ No:108, DMAINT13_S */ + DMAC_DMAINT14_S_IRQn = 109, /* IRQ No:109, DMAINT14_S */ + DMAC_DMAINT15_S_IRQn = 110, /* IRQ No:110, DMAINT15_S */ + DMAC_DMAERR_NS_IRQn = 111, /* IRQ No:111, DMAERR_NS */ + DMAC_DMAINT0_NS_IRQn = 112, /* IRQ No:112, DMAINT0_NS */ + DMAC_DMAINT1_NS_IRQn = 113, /* IRQ No:113, DMAINT1_NS */ + DMAC_DMAINT2_NS_IRQn = 114, /* IRQ No:114, DMAINT2_NS */ + DMAC_DMAINT3_NS_IRQn = 115, /* IRQ No:115, DMAINT3_NS */ + DMAC_DMAINT4_NS_IRQn = 116, /* IRQ No:116, DMAINT4_NS */ + DMAC_DMAINT5_NS_IRQn = 117, /* IRQ No:117, DMAINT5_NS */ + DMAC_DMAINT6_NS_IRQn = 118, /* IRQ No:118, DMAINT6_NS */ + DMAC_DMAINT7_NS_IRQn = 119, /* IRQ No:119, DMAINT7_NS */ + DMAC_DMAINT8_NS_IRQn = 120, /* IRQ No:120, DMAINT8_NS */ + DMAC_DMAINT9_NS_IRQn = 121, /* IRQ No:121, DMAINT9_NS */ + DMAC_DMAINT10_NS_IRQn = 122, /* IRQ No:122, DMAINT10_NS */ + DMAC_DMAINT11_NS_IRQn = 123, /* IRQ No:123, DMAINT11_NS */ + DMAC_DMAINT12_NS_IRQn = 124, /* IRQ No:124, DMAINT12_NS */ + DMAC_DMAINT13_NS_IRQn = 125, /* IRQ No:125, DMAINT13_NS */ + DMAC_DMAINT14_NS_IRQn = 126, /* IRQ No:126, DMAINT14_NS */ + DMAC_DMAINT15_NS_IRQn = 127, /* IRQ No:127, DMAINT15_NS */ + GPT0_CCMPA_IRQn = 128, /* IRQ No:128, CCMPA0 */ + GPT0_CCMPB_IRQn = 129, /* IRQ No:129, CCMPB0 */ + GPT0_CMPC_IRQn = 130, /* IRQ No:130, CMPC0 */ + GPT0_CMPD_IRQn = 131, /* IRQ No:131, CMPD0 */ + GPT0_CMPE_IRQn = 132, /* IRQ No:132, CMPE0 */ + GPT0_CMPF_IRQn = 133, /* IRQ No:133, CMPF0 */ + GPT0_ADTRGA_IRQn = 134, /* IRQ No:134, ADTRGA0 */ + GPT0_ADTRGB_IRQn = 135, /* IRQ No:135, ADTRGB0 */ + GPT0_OVF_IRQn = 136, /* IRQ No:136, OVF0 */ + GPT0_UNF_IRQn = 137, /* IRQ No:137, UNF0 */ + /* IRQ No:138, Reserved */ + /* IRQ No:139, Reserved */ + /* IRQ No:140, Reserved */ + GPT1_CCMPA_IRQn = 141, /* IRQ No:141, CCMPA1 */ + GPT1_CCMPB_IRQn = 142, /* IRQ No:142, CCMPB1 */ + GPT1_CMPC_IRQn = 143, /* IRQ No:143, CMPC1 */ + GPT1_CMPD_IRQn = 144, /* IRQ No:144, CMPD1 */ + GPT1_CMPE_IRQn = 145, /* IRQ No:145, CMPE1 */ + GPT1_CMPF_IRQn = 146, /* IRQ No:146, CMPF1 */ + GPT1_ADTRGA_IRQn = 147, /* IRQ No:147, ADTRGA1 */ + GPT1_ADTRGB_IRQn = 148, /* IRQ No:148, ADTRGB1 */ + GPT1_OVF_IRQn = 149, /* IRQ No:149, OVF1 */ + GPT1_UNF_IRQn = 150, /* IRQ No:150, UNF1 */ + /* IRQ No:151, Reserved */ + /* IRQ No:152, Reserved */ + /* IRQ No:153, Reserved */ + GPT2_CCMPA_IRQn = 154, /* IRQ No:154, CCMPA2 */ + GPT2_CCMPB_IRQn = 155, /* IRQ No:155, CCMPB2 */ + GPT2_CMPC_IRQn = 156, /* IRQ No:156, CMPC2 */ + GPT2_CMPD_IRQn = 157, /* IRQ No:157, CMPD2 */ + GPT2_CMPE_IRQn = 158, /* IRQ No:158, CMPE2 */ + GPT2_CMPF_IRQn = 159, /* IRQ No:159, CMPF2 */ + GPT2_ADTRGA_IRQn = 160, /* IRQ No:160, ADTRGA2 */ + GPT2_ADTRGB_IRQn = 161, /* IRQ No:161, ADTRGB2 */ + GPT2_OVF_IRQn = 162, /* IRQ No:162, OVF2 */ + GPT2_UNF_IRQn = 163, /* IRQ No:163, UNF2 */ + /* IRQ No:164, Reserved */ + /* IRQ No:165, Reserved */ + /* IRQ No:166, Reserved */ + GPT3_CCMPA_IRQn = 167, /* IRQ No:167, CCMPA3 */ + GPT3_CCMPB_IRQn = 168, /* IRQ No:168, CCMPB3 */ + GPT3_CMPC_IRQn = 169, /* IRQ No:169, CMPC3 */ + GPT3_CMPD_IRQn = 170, /* IRQ No:170, CMPD3 */ + GPT3_CMPE_IRQn = 171, /* IRQ No:171, CMPE3 */ + GPT3_CMPF_IRQn = 172, /* IRQ No:172, CMPF3 */ + GPT3_ADTRGA_IRQn = 173, /* IRQ No:173, ADTRGA3 */ + GPT3_ADTRGB_IRQn = 174, /* IRQ No:174, ADTRGB3 */ + GPT3_OVF_IRQn = 175, /* IRQ No:175, OVF3 */ + GPT3_UNF_IRQn = 176, /* IRQ No:176, UNF3 */ + /* IRQ No:177, Reserved */ + /* IRQ No:178, Reserved */ + /* IRQ No:179, Reserved */ + GPT4_CCMPA_IRQn = 180, /* IRQ No:180, CCMPA4 */ + GPT4_CCMPB_IRQn = 181, /* IRQ No:181, CCMPB4 */ + GPT4_CMPC_IRQn = 182, /* IRQ No:182, CMPC4 */ + GPT4_CMPD_IRQn = 183, /* IRQ No:183, CMPD4 */ + GPT4_CMPE_IRQn = 184, /* IRQ No:184, CMPE4 */ + GPT4_CMPF_IRQn = 185, /* IRQ No:185, CMPF4 */ + GPT4_ADTRGA_IRQn = 186, /* IRQ No:186, ADTRGA4 */ + GPT4_ADTRGB_IRQn = 187, /* IRQ No:187, ADTRGB4 */ + GPT4_OVF_IRQn = 188, /* IRQ No:188, OVF4 */ + GPT4_UNF_IRQn = 189, /* IRQ No:189, UNF4 */ + /* IRQ No:190, Reserved */ + /* IRQ No:191, Reserved */ + /* IRQ No:192, Reserved */ + GPT5_CCMPA_IRQn = 193, /* IRQ No:193, CCMPA5 */ + GPT5_CCMPB_IRQn = 194, /* IRQ No:194, CCMPB5 */ + GPT5_CMPC_IRQn = 195, /* IRQ No:195, CMPC5 */ + GPT5_CMPD_IRQn = 196, /* IRQ No:196, CMPD5 */ + GPT5_CMPE_IRQn = 197, /* IRQ No:197, CMPE5 */ + GPT5_CMPF_IRQn = 198, /* IRQ No:198, CMPF5 */ + GPT5_ADTRGA_IRQn = 199, /* IRQ No:199, ADTRGA5 */ + GPT5_ADTRGB_IRQn = 200, /* IRQ No:200, ADTRGB5 */ + GPT5_OVF_IRQn = 201, /* IRQ No:201, OVF5 */ + GPT5_UNF_IRQn = 202, /* IRQ No:202, UNF5 */ + /* IRQ No:203, Reserved */ + /* IRQ No:204, Reserved */ + /* IRQ No:205, Reserved */ + GPT6_CCMPA_IRQn = 206, /* IRQ No:206, CCMPA6 */ + GPT6_CCMPB_IRQn = 207, /* IRQ No:207, CCMPB6 */ + GPT6_CMPC_IRQn = 208, /* IRQ No:208, CMPC6 */ + GPT6_CMPD_IRQn = 209, /* IRQ No:209, CMPD6 */ + GPT6_CMPE_IRQn = 210, /* IRQ No:210, CMPE6 */ + GPT6_CMPF_IRQn = 211, /* IRQ No:211, CMPF6 */ + GPT6_ADTRGA_IRQn = 212, /* IRQ No:212, ADTRGA6 */ + GPT6_ADTRGB_IRQn = 213, /* IRQ No:213, ADTRGB6 */ + GPT6_OVF_IRQn = 214, /* IRQ No:214, OVF6 */ + GPT6_UNF_IRQn = 215, /* IRQ No:215, UNF6 */ + /* IRQ No:216, Reserved */ + /* IRQ No:217, Reserved */ + /* IRQ No:218, Reserved */ + GPT7_CCMPA_IRQn = 219, /* IRQ No:219, CCMPA7 */ + GPT7_CCMPB_IRQn = 220, /* IRQ No:220, CCMPB7 */ + GPT7_CMPC_IRQn = 221, /* IRQ No:221, CMPC7 */ + GPT7_CMPD_IRQn = 222, /* IRQ No:222, CMPD7 */ + GPT7_CMPE_IRQn = 223, /* IRQ No:223, CMPE7 */ + GPT7_CMPF_IRQn = 226, /* IRQ No:226, CMPF7 */ + GPT7_ADTRGA_IRQn = 225, /* IRQ No:225, ADTRGA7 */ + GPT7_ADTRGB_IRQn = 226, /* IRQ No:226, ADTRGB7 */ + GPT7_OVF_IRQn = 227, /* IRQ No:227, OVF7 */ + GPT7_UNF_IRQn = 228, /* IRQ No:228, UNF7 */ + /* IRQ No:229, Reserved */ + /* IRQ No:230, Reserved */ + /* IRQ No:231, Reserved */ + POE3_OEI1_IRQn = 232, /* IRQ No:232, OEI1 */ + POE3_OEI2_IRQn = 233, /* IRQ No:233, OEI2 */ + POE3_OEI3_IRQn = 234, /* IRQ No:234, OEI3 */ + POE3_OEI4_IRQn = 235, /* IRQ No:235, OEI4 */ + POEG_GROUP0_IRQn = 236, /* IRQ No:236, POEGA_GROUP0 */ + POEG_GROUP1_IRQn = 237, /* IRQ No:237, POEGB_GROUP1 */ + POEG_GROUP2_IRQn = 238, /* IRQ No:238, POEGC_GROUP2 */ + POEG_GROUP3_IRQn = 239, /* IRQ No:239, POEGD_GROUP3 */ + I2S0_INT_REQ_IRQn = 240, /* IRQ No:240, INT_ssif_int_req_0 */ + I2S0_DMA_RX_IRQn = 241, /* IRQ No:241, INT_ssif_dma_rx_0 */ + I2S0_DMA_TX_IRQn = 242, /* IRQ No:242, INT_ssif_dma_tx_0 */ + I2S1_INT_REQ_IRQn = 243, /* IRQ No:243, INT_ssif_int_req_1 */ + I2S1_DMA_RX_IRQn = 244, /* IRQ No:244, INT_ssif_dma_rx_1 */ + I2S1_DMA_TX_IRQn = 245, /* IRQ No:245, INT_ssif_dma_tx_1 */ + I2S2_INT_REQ_IRQn = 246, /* IRQ No:246, INT_ssif_int_req_2 */ + I2S2_DMA_RX_IRQn = 247, /* IRQ No:247, INT_ssif_dma_rx_1 */ + I2S2_DMA_TX_IRQn = 248, /* IRQ No:248, INT_ssif_dma_tx_1 */ + I2S3_INT_REQ_IRQn = 249, /* IRQ No:249, INT_ssif_int_req_3 */ + I2S3_DMA_RX_IRQn = 250, /* IRQ No:250, INT_ssif_dma_rx_3 */ + I2S3_DMA_TX_IRQn = 251, /* IRQ No:251, INT_ssif_dma_tx_3 */ + SRC_IDEI_IRQn = 252, /* IRQ No:252, SRC_IDEI */ + SRC_ODFI_IRQn = 253, /* IRQ No:253, SRC_ODFI */ + SRC_CEF_IRQn = 254, /* IRQ No:254, SRC_CEF */ + SRC_UDF_IRQn = 255, /* IRQ No:255, SRC_UDF */ + SRC_OVF_IRQn = 256, /* IRQ No:256, SRC_OVF */ + RIIC0_TEI_IRQn = 257, /* IRQ No:257, INTRIICTEI0 */ + RIIC0_NAKI_IRQn = 258, /* IRQ No:258, INTRIICNAKI0 */ + RIIC0_SPI_IRQn = 259, /* IRQ No:259, INTRIICSPI0 */ + RIIC0_STI_IRQn = 260, /* IRQ No:260, INTRIICSTI0 */ + RIIC0_ALI_IRQn = 261, /* IRQ No:261, INTRIICALI0 */ + RIIC0_TMOI_IRQn = 262, /* IRQ No:262, INTRIICTMOI0 */ + RIIC0_RI_IRQn = 263, /* IRQ No:263, INTRIICRI0 */ + RIIC0_TI_IRQn = 264, /* IRQ No:264, INTRIICTI0 */ + RIIC1_TEI_IRQn = 265, /* IRQ No:265, INTRIICTEI0 */ + RIIC1_NAKI_IRQn = 266, /* IRQ No:266, INTRIICNAKI0 */ + RIIC1_SPI_IRQn = 267, /* IRQ No:267, INTRIICSPI0 */ + RIIC1_STI_IRQn = 268, /* IRQ No:268, INTRIICSTI0 */ + RIIC1_ALI_IRQn = 269, /* IRQ No:269, INTRIICALI0 */ + RIIC1_TMOI_IRQn = 270, /* IRQ No:270, INTRIICTMOI0 */ + RIIC1_RI_IRQn = 271, /* IRQ No:271, INTRIICRI0 */ + RIIC1_TI_IRQn = 272, /* IRQ No:272, INTRIICTI0 */ + RIIC2_TEI_IRQn = 273, /* IRQ No:273, INTRIICTEI0 */ + RIIC2_NAKI_IRQn = 274, /* IRQ No:274, INTRIICNAKI0 */ + RIIC2_SPI_IRQn = 275, /* IRQ No:275, INTRIICSPI0 */ + RIIC2_STI_IRQn = 276, /* IRQ No:276, INTRIICSTI0 */ + RIIC2_ALI_IRQn = 277, /* IRQ No:277, INTRIICALI0 */ + RIIC2_TMOI_IRQn = 278, /* IRQ No:278, INTRIICTMOI0 */ + RIIC2_RI_IRQn = 279, /* IRQ No:279, INTRIICRI0 */ + RIIC2_TI_IRQn = 280, /* IRQ No:280, INTRIICTI0 */ + RIIC3_TEI_IRQn = 281, /* IRQ No:281, INTRIICTEI0 */ + RIIC3_NAKI_IRQn = 282, /* IRQ No:282, INTRIICNAKI0 */ + RIIC3_SPI_IRQn = 283, /* IRQ No:283, INTRIICSPI0 */ + RIIC3_STI_IRQn = 284, /* IRQ No:284, INTRIICSTI0 */ + RIIC3_ALI_IRQn = 285, /* IRQ No:285, INTRIICALI0 */ + RIIC3_TMOI_IRQn = 286, /* IRQ No:286, INTRIICTMOI0 */ + RIIC3_RI_IRQn = 287, /* IRQ No:287, INTRIICRI0 */ + RIIC3_TI_IRQn = 288, /* IRQ No:288, INTRIICTI0 */ + RI3C_IERR_IRQn = 289, /* IRQ No:289, INT_ri3c_ierr_n */ + RI3C_TERR_IRQn = 290, /* IRQ No:290, INT_ri3c_terr_n */ + /* IRQ No:291, Reserved */ + /* IRQ No:292, Reserved */ + RI3C_ABORT_IRQn = 293, /* IRQ No:293, INT_ri3c_abort_n */ + RI3C_RESP_IRQn = 294, /* IRQ No:294, INT_ri3c_resp_n */ + RI3C_CMD_IRQn = 295, /* IRQ No:295, INT_ri3c_cmd_n */ + RI3C_IBI_IRQn = 296, /* IRQ No:296, INT_ri3c_ibi_n */ + RI3C_RX_IRQn = 297, /* IRQ No:297, INT_ri3c_rx_n */ + RI3C_TX_IRQn = 298, /* IRQ No:298, INT_ri3c_tx_n */ + RI3C_RCV_IRQn = 299, /* IRQ No:299, INT_ri3c_rcv_n */ + /* IRQ No:300, Reserved */ + /* IRQ No:301, Reserved */ + /* IRQ No:302, Reserved */ + /* IRQ No:303, Reserved */ + RI3C_ST_IRQn = 304, /* IRQ No:304, INT_ri3c_st_n */ + RI3C_SP_IRQn = 305, /* IRQ No:305, INT_ri3c_sp_n */ + RI3C_EXIT_IRQn = 306, /* IRQ No:306, INT_ri3c_exit_n */ + RI3C_TEND_IRQn = 307, /* IRQ No:307, INT_ri3c_tend_n */ + RI3C_NACK_IRQn = 308, /* IRQ No:308, INT_ri3c_nack_n */ + RI3C_AL_IRQn = 309, /* IRQ No:309, INT_ri3c_al_n */ + RI3C_TMO_IRQn = 310, /* IRQ No:310, INT_ri3c_tmo_n */ + RI3C_WU_IRQn = 311, /* IRQ No:311, INT_ri3c_wu_n */ + ADC_INTAD_IRQn = 312, /* IRQ No:312, INTAD */ + /* IRQ No:313, Reserved */ + /* IRQ No:314, Reserved */ + RTC_ALM_IRQn = 315, /* IRQ No:315, INT_intreq_rtc_alm_n */ + RTC_PRD_IRQn = 316, /* IRQ No:316, INT_intreq_rtc_prd_n */ + RTC_CUP_IRQn = 317, /* IRQ No:317, INT_intreq_rtc_cup_n */ + /* IRQ No:318, Reserved */ + /* IRQ No:319, Reserved */ + SCIF0_RERR_IRQn = 320, /* IRQ No:320, ERI0 */ + SCIF0_BRK_IRQn = 321, /* IRQ No:321, BRI0 */ + SCIF0_RXI_IRQn = 322, /* IRQ No:322, RXI0 */ + SCIF0_TXI_IRQn = 323, /* IRQ No:323, TXI0 */ + SCIF0_TEI_DRI_IRQn = 324, /* IRQ No:324, TEI0_DRI0 */ + SCIF1_RERR_IRQn = 325, /* IRQ No:325, ERI1 */ + SCIF1_BRK_IRQn = 326, /* IRQ No:326, BRI1 */ + SCIF1_RXI_IRQn = 327, /* IRQ No:327, RXI1 */ + SCIF1_TXI_IRQn = 328, /* IRQ No:328, TXI1 */ + SCIF1_TEI_DRI_IRQn = 329, /* IRQ No:329, TEI1_DRI1 */ + SCIF2_RERR_IRQn = 330, /* IRQ No:330, ERI2 */ + SCIF2_BRK_IRQn = 331, /* IRQ No:331, BRI2 */ + SCIF2_RXI_IRQn = 332, /* IRQ No:332, RXI2 */ + SCIF2_TXI_IRQn = 333, /* IRQ No:333, TXI2 */ + SCIF2_TEI_DRI_IRQn = 334, /* IRQ No:334, TEI2_DRI2 */ + SCIF3_RERR_IRQn = 335, /* IRQ No:335, ERI3 */ + SCIF3_BRK_IRQn = 336, /* IRQ No:336, BRI3 */ + SCIF3_RXI_IRQn = 337, /* IRQ No:337, RXI3 */ + SCIF3_TXI_IRQn = 338, /* IRQ No:338, TXI3 */ + SCIF3_TEI_DRI_IRQn = 339, /* IRQ No:339, TEI3_DRI3 */ + SCIF4_RERR_IRQn = 340, /* IRQ No:340, ERI4 */ + SCIF4_BRK_IRQn = 341, /* IRQ No:341, BRI4 */ + SCIF4_RXI_IRQn = 342, /* IRQ No:342, RXI4 */ + SCIF4_TXI_IRQn = 343, /* IRQ No:343, TXI4 */ + SCIF4_TEI_DRI_IRQn = 344, /* IRQ No:344, TEI4_DRI4 */ + SCIF5_RERR_IRQn = 345, /* IRQ No:345, ERI5 */ + SCIF5_BRK_IRQn = 346, /* IRQ No:346, BRI5 */ + SCIF5_RXI_IRQn = 347, /* IRQ No:347, RXI5 */ + SCIF5_TXI_IRQn = 348, /* IRQ No:348, TXI5 */ + SCIF5_TEI_DRI_IRQn = 349, /* IRQ No:349, TEI5_DRI5 */ + SCI0_ERI_IRQn = 350, /* IRQ No:350, ERI0 */ + SCI0_RXI_IRQn = 351, /* IRQ No:351, RXI0 */ + SCI0_TXI_IRQn = 352, /* IRQ No:352, TXI0 */ + SCI0_TEI_IRQn = 353, /* IRQ No:353, TEI0 */ + SCI1_ERI_IRQn = 354, /* IRQ No:354, ERI1 */ + SCI1_RXI_IRQn = 355, /* IRQ No:355, RXI1 */ + SCI1_TXI_IRQn = 356, /* IRQ No:356, TXI1 */ + SCI1_TEI_IRQn = 357, /* IRQ No:357, TEI1 */ + RSPI0_ERR_IRQn = 358, /* IRQ No:358, SPEI0 */ + RSPI0_RX_IRQn = 359, /* IRQ No:359, SPRI0 */ + RSPI0_TX_IRQn = 360, /* IRQ No:360, SPTI0 */ + RSPI1_ERR_IRQn = 361, /* IRQ No:361, SPEI1 */ + RSPI1_RX_IRQn = 362, /* IRQ No:362, SPRI1 */ + RSPI1_TX_IRQn = 363, /* IRQ No:363, SPTI1 */ + RSPI2_ERR_IRQn = 364, /* IRQ No:364, SPEI2 */ + RSPI2_RX_IRQn = 365, /* IRQ No:365, SPRI2 */ + RSPI2_TX_IRQn = 366, /* IRQ No:366, SPTI2 */ + RSPI3_ERR_IRQn = 367, /* IRQ No:367, SPEI3 */ + RSPI3_RX_IRQn = 368, /* IRQ No:368, SPRI3 */ + RSPI3_TX_IRQn = 369, /* IRQ No:369, SPTI3 */ + RSPI4_ERR_IRQn = 370, /* IRQ No:370, SPEI4 */ + RSPI4_RX_IRQn = 371, /* IRQ No:371, SPRI4 */ + RSPI4_TX_IRQn = 372, /* IRQ No:372, SPTI4 */ + CANFD_INTRCANGERR_IRQn = 373, /* IRQ No:373, INTRCANGERR */ + CANFD_INTRCANGRECC_IRQn = 374, /* IRQ No:374, INTRCANGRECC */ + CANFD_INTRCAN0REC_IRQn = 375, /* IRQ No:375, INTRCAN0REC */ + CANFD_INTRCAN1REC_IRQn = 376, /* IRQ No:376, INTRCAN1REC */ + CANFD_INTRCAN0ERR_IRQn = 377, /* IRQ No:377, INTRCAN0ERR */ + CANFD_INTRCAN1ERR_IRQn = 378, /* IRQ No:378, INTRCAN1ERR */ + CANFD_INTRCAN0TRX_IRQn = 379, /* IRQ No:379, INTRCAN0TRX */ + CANFD_INTRCAN1TRX_IRQn = 380, /* IRQ No:380, INTRCAN1TRX */ + /* IRQ No:381, Reserved */ + /* IRQ No:382, Reserved */ + /* IRQ No:383, Reserved */ + /* IRQ No:384, Reserved */ + /* IRQ No:385, Reserved */ + /* IRQ No:386, Reserved */ + SPDIF_SPDIF_IRQn = 387, /* IRQ No:387, intreq_spdif */ + PDM_ERR0_IRQn = 388, /* IRQ No:388, INT_PDM_ERR0 */ + PDM_ERR1_IRQn = 389, /* IRQ No:389, INT_PDM_ERR1 */ + PDM_ERR2_IRQn = 390, /* IRQ No:390, INT_PDM_ERR2 */ + PDM_DAT0_IRQn = 391, /* IRQ No:391, INT_PDM_DAT0 */ + PDM_DAT1_IRQn = 392, /* IRQ No:392, INT_PDM_DAT1 */ + PDM_DAT2_IRQn = 393, /* IRQ No:393, INT_PDM_DAT2 */ + PDM_SDET_IRQn = 394, /* IRQ No:394, INT_PDM_SDET */ + PCIE_INT_SERR_IRQn = 395, /* IRQ No:395, INT_SERR */ + PCIE_INT_SERR_COR_IRQn = 396, /* IRQ No:396, INT_SERR_COR */ + PCIE_INT_SERR_NONFATAL_IRQn = 397, /* IRQ No:397, INT_SERR_NONFATAL */ + PCIE_INT_SERR_FATAL_IRQn = 398, /* IRQ No:398, INT_SERR_FATAL */ + PCIE_AXI_ERR_INTIRQn = 399, /* IRQ No:399, AXI_ERR_INT */ + PCIE_INTA_RC_IRQn = 400, /* IRQ No:400, INTA_RC */ + PCIE_INTB_RC_IRQn = 401, /* IRQ No:401, INTB_RC */ + PCIE_INTC_RC_IRQn = 402, /* IRQ No:402, INTC_RC */ + PCIE_INTD_RC_IRQn = 403, /* IRQ No:403, INTD_RC */ + PCIE_INTMSI_RC_IRQn = 404, /* IRQ No:404, INTMSI_RC */ + PCIE_INT_LINK_BANDWIDTH_IRQn = 405, /* IRQ No:405, INT_LINK_BANDWIDTH */ + PCIE_INT_PM_PME_IRQn = 406, /* IRQ No:406, INT_PM_PME */ + PCIE_DMA_INT_IRQn = 407, /* IRQ No:407, DMA_IN */ + PCIE_PCIE_EVT_INT_IRQn = 408, /* IRQ No:408, PCIE_EVT_IN */ + PCIE_MSG_INT_IRQn = 409, /* IRQ No:409, MSG_INT */ + PCIE_INT_ALL_IRQn = 410, /* IRQ No:410, INT_ALL */ + /* IRQ No:411, Reserved */ + /* IRQ No:412, Reserved */ + /* IRQ No:413, Reserved */ + /* IRQ No:414, Reserved */ + /* IRQ No:415, Reserved */ + /* IRQ No:416, Reserved */ + /* IRQ No:417, Reserved */ + /* IRQ No:418, Reserved */ + /* IRQ No:419, Reserved */ + /* IRQ No:420, Reserved */ + /* IRQ No:421, Reserved */ + /* IRQ No:422, Reserved */ + /* IRQ No:423, Reserved */ + /* IRQ No:424, Reserved */ + /* IRQ No:425, Reserved */ + /* IRQ No:426, Reserved */ + /* IRQ No:427, Reserved */ + /* IRQ No:428, Reserved */ + GPIO_TINT0_IRQn = 429, /* IRQ No:429, TINT0 */ + GPIO_TINT1_IRQn = 430, /* IRQ No:430, TINT1 */ + GPIO_TINT2_IRQn = 431, /* IRQ No:431, TINT2 */ + GPIO_TINT3_IRQn = 432, /* IRQ No:432, TINT3 */ + GPIO_TINT4_IRQn = 433, /* IRQ No:433, TINT4 */ + GPIO_TINT5_IRQn = 434, /* IRQ No:434, TINT5 */ + GPIO_TINT6_IRQn = 435, /* IRQ No:435, TINT6 */ + GPIO_TINT7_IRQn = 436, /* IRQ No:436, TINT7 */ + GPIO_TINT8_IRQn = 437, /* IRQ No:437, TINT8 */ + GPIO_TINT9_IRQn = 438, /* IRQ No:438, TINT9 */ + GPIO_TINT10_IRQn = 439, /* IRQ No:439, TINT10 */ + GPIO_TINT11_IRQn = 440, /* IRQ No:440, TINT11 */ + GPIO_TINT12_IRQn = 441, /* IRQ No:441, TINT12 */ + GPIO_TINT13_IRQn = 442, /* IRQ No:442, TINT13 */ + GPIO_TINT14_IRQn = 443, /* IRQ No:443, TINT14 */ + GPIO_TINT15_IRQn = 444, /* IRQ No:444, TINT15 */ + GPIO_TINT16_IRQn = 445, /* IRQ No:445, TINT16 */ + GPIO_TINT17_IRQn = 446, /* IRQ No:446, TINT17 */ + GPIO_TINT18_IRQn = 447, /* IRQ No:447, TINT18 */ + GPIO_TINT19_IRQn = 448, /* IRQ No:448, TINT19 */ + GPIO_TINT20_IRQn = 449, /* IRQ No:449, TINT20 */ + GPIO_TINT21_IRQn = 450, /* IRQ No:450, TINT21 */ + GPIO_TINT22_IRQn = 451, /* IRQ No:451, TINT22 */ + GPIO_TINT23_IRQn = 452, /* IRQ No:452, TINT23 */ + GPIO_TINT24_IRQn = 453, /* IRQ No:453, TINT24 */ + GPIO_TINT25_IRQn = 454, /* IRQ No:454, TINT25 */ + GPIO_TINT26_IRQn = 455, /* IRQ No:455, TINT26 */ + GPIO_TINT27_IRQn = 456, /* IRQ No:456, TINT27 */ + GPIO_TINT28_IRQn = 457, /* IRQ No:457, TINT28 */ + GPIO_TINT29_IRQn = 458, /* IRQ No:458, TINT29 */ + GPIO_TINT30_IRQn = 459, /* IRQ No:459, TINT30 */ + GPIO_TINT31_IRQn = 460, /* IRQ No:460, TINT31 */ + /* IRQ No:461, Reserved */ + /* IRQ No:462, Reserved */ + /* IRQ No:463, Reserved */ + /* IRQ No:464, Reserved */ + /* IRQ No:465, Reserved */ + /* IRQ No:466, Reserved */ + /* IRQ No:467, Reserved */ + /* IRQ No:468, Reserved */ + /* IRQ No:469, Reserved */ + /* IRQ No:470, Reserved */ + /* IRQ No:471, Reserved */ + /* IRQ No:472, Reserved */ + /* IRQ No:473, Reserved */ + /* IRQ No:474, Reserved */ + /* IRQ No:475, Reserved */ + /* IRQ No:476, Reserved */ + /* IRQ No:477, Reserved */ + /* IRQ No:478, Reserved */ + /* IRQ No:479, Reserved */ +} IRQn_Type; + +/** @} (end addtogroup BSP_MPU_RZG2UL) */ + +#endif /* BSP_IRQ_ID_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_mcu_info.h b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_mcu_info.h new file mode 100644 index 00000000..fa505b9b --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_mcu_info.h @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_mcu_info.h + * Version : 1.00 + * Description : bsp_mcu_info header + *********************************************************************************************************************/ + +/******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RZG3S RZG3S + * @includedoc config_bsp_rzg3s_fsp_cm33.html + * @{ + *********************************************************************************************************************/ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_multi_core.h" +#include "bsp_irq_id.h" +#include "bsp_feature.h" +#include "bsp_dmac.h" +#include "bsp_slave_address.h" +#include "bsp_reset.h" + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + *********************************************************************************************************************/ + +#endif /* BSP_MCU_INFO_H */ + +/** @} (end defgroup BSP_MCU_RZG3S) */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_multi_core.h b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_multi_core.h new file mode 100644 index 00000000..e03505b2 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_multi_core.h @@ -0,0 +1,42 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_multi_core.h + * Version : 1.00 + * Description : bsp_multi_core header + *********************************************************************************************************************/ + +#ifndef BSP_MULTI_CORE_H +#define BSP_MULTI_CORE_H + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ +#define RZG3S_CORE_CA55 (0) +#define RZG3S_CORE_CM33 (1) +#define RZG3S_CORE_CM33_FPU (2) + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * @addtogroup BSP_MPU_RZG3S + * @{ + *********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MPU_RZG3S) */ + +#endif /* BSP_MULTI_CORE_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_override.h b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_override.h new file mode 100644 index 00000000..b463c0e2 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_override.h @@ -0,0 +1,761 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RZG3S + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RZG3S) */ + +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MCU. */ +#define BSP_OVERRIDE_ADC_INCLUDE +#define BSP_OVERRIDE_ADC_INFO_T +#define BSP_OVERRIDE_BSP_ACC_CONTROL_IP_T +#define BSP_OVERRIDE_BSP_ACCESS_CONTROL +#define BSP_OVERRIDE_BSP_PIN_T +#define BSP_OVERRIDE_BSP_PORT_T +#define BSP_OVERRIDE_DMAC_B_EXTERNAL_DETECTION_T +#define BSP_OVERRIDE_FSP_IP_T +#define BSP_OVERRIDE_FSP_PRIV_CLOCK_T +#define BSP_OVERRIDE_IOPORT_PERIPHERAL_T +#define BSP_OVERRIDE_TRANSFER_ADDR_MODE_T +#define BSP_OVERRIDE_TRANSFER_INFO_T +#define BSP_OVERRIDE_TRANSFER_MODE_T +#define BSP_OVERRIDE_TRANSFER_SIZE_T + +/* Override definitions. */ + +/*============================================== + * Access Control Level Configuration Macros Overrides + *==============================================*/ + +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM0 (R_SYSC->SYS_SLVACCCTL0) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM0 (R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM1 (R_SYSC->SYS_SLVACCCTL0) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM1 (R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM2 (R_SYSC->SYS_SLVACCCTL0) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM2 (R_SYSC_SYS_SLVACCCTL0_SRAM2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM3 (R_SYSC->SYS_SLVACCCTL0) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM3 (R_SYSC_SYS_SLVACCCTL0_SRAM3_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC0 (R_SYSC->SYS_SLVACCCTL2) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC0 (R_SYSC_SYS_SLVACCCTL2_TZC0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC1 (R_SYSC->SYS_SLVACCCTL2) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC1 (R_SYSC_SYS_SLVACCCTL2_TZC1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC2 (R_SYSC->SYS_SLVACCCTL2) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC2 (R_SYSC_SYS_SLVACCCTL2_TZC2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC3 (R_SYSC->SYS_SLVACCCTL2) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC3 (R_SYSC_SYS_SLVACCCTL2_TZC3_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC5 (R_SYSC->SYS_SLVACCCTL2) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC5 (R_SYSC_SYS_SLVACCCTL2_TZC5_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC6 (R_SYSC->SYS_SLVACCCTL2) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC6 (R_SYSC_SYS_SLVACCCTL2_TZC6_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_CST (R_SYSC->SYS_SLVACCCTL3) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_CST (R_SYSC_SYS_SLVACCCTL3_CST_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_CPG (R_SYSC->SYS_SLVACCCTL3) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_CPG (R_SYSC_SYS_SLVACCCTL3_CPG_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SYSC (R_SYSC->SYS_SLVACCCTL3) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SYSC (R_SYSC_SYS_SLVACCCTL3_SYSC_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SYC (R_SYSC->SYS_SLVACCCTL3) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SYC (R_SYSC_SYS_SLVACCCTL3_SYC_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_GIC (R_SYSC->SYS_SLVACCCTL3) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_GIC (R_SYSC_SYS_SLVACCCTL3_GIC_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_IA55_IM33 (R_SYSC->SYS_SLVACCCTL3) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_IA55_IM33 (R_SYSC_SYS_SLVACCCTL3_IA55_IM33_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_GPIO (R_SYSC->SYS_SLVACCCTL3) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_GPIO (R_SYSC_SYS_SLVACCCTL3_GPIO_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_MHU (R_SYSC->SYS_SLVACCCTL3) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_MHU (R_SYSC_SYS_SLVACCCTL3_MHU_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_DMAC0 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_DMAC0 (R_SYSC_SYS_SLVACCCTL4_DMAC0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_DMAC1 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_DMAC1 (R_SYSC_SYS_SLVACCCTL4_DMAC1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM0 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM0 (R_SYSC_SYS_SLVACCCTL4_OSTM0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM1 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM1 (R_SYSC_SYS_SLVACCCTL4_OSTM1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM2 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM2 (R_SYSC_SYS_SLVACCCTL4_OSTM2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM3 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM3 (R_SYSC_SYS_SLVACCCTL4_OSTM3_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM4 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM4 (R_SYSC_SYS_SLVACCCTL4_OSTM4_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM5 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM5 (R_SYSC_SYS_SLVACCCTL4_OSTM5_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM6 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM6 (R_SYSC_SYS_SLVACCCTL4_OSTM6_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM7 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM7 (R_SYSC_SYS_SLVACCCTL4_OSTM7_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT0 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT0 (R_SYSC_SYS_SLVACCCTL4_WDT0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT1 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT1 (R_SYSC_SYS_SLVACCCTL4_WDT1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT2 (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT2 (R_SYSC_SYS_SLVACCCTL4_WDT2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_RTC (R_SYSC->SYS_SLVACCCTL4) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_RTC (R_SYSC_SYS_SLVACCCTL4_RTC_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_MTU3A (R_SYSC->SYS_SLVACCCTL5) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_MTU3A (R_SYSC_SYS_SLVACCCTL5_MTU3A_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_POE3 (R_SYSC->SYS_SLVACCCTL5) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_POE3 (R_SYSC_SYS_SLVACCCTL5_POE3_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_GPT (R_SYSC->SYS_SLVACCCTL5) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_GPT (R_SYSC_SYS_SLVACCCTL5_GPT_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_POEG (R_SYSC->SYS_SLVACCCTL5) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_POEG (R_SYSC_SYS_SLVACCCTL5_POEG_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_DDR (R_SYSC->SYS_SLVACCCTL5) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_DDR (R_SYSC_SYS_SLVACCCTL5_DDR_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_XSPI (R_SYSC->SYS_SLVACCCTL5) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_XSPI (R_SYSC_SYS_SLVACCCTL5_XSPI_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OCTA (R_SYSC->SYS_SLVACCCTL5) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OCTA (R_SYSC_SYS_SLVACCCTL5_OCTA_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_USBT (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_USBT (R_SYSC_SYS_SLVACCCTL6_USBT_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_USB20 (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_USB20 (R_SYSC_SYS_SLVACCCTL6_USB20_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_USB21 (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_USB21 (R_SYSC_SYS_SLVACCCTL6_USB21_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SDHI0 (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SDHI0 (R_SYSC_SYS_SLVACCCTL6_SDHI0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SDHI1 (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SDHI1 (R_SYSC_SYS_SLVACCCTL6_SDHI1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SDHI2 (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SDHI2 (R_SYSC_SYS_SLVACCCTL6_SDHI2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_ETH0 (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_ETH0 (R_SYSC_SYS_SLVACCCTL6_ETH0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_ETH1 (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_ETH1 (R_SYSC_SYS_SLVACCCTL6_ETH1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_PCIE (R_SYSC->SYS_SLVACCCTL6) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_PCIE (R_SYSC_SYS_SLVACCCTL6_PCIE_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C0 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C0 (R_SYSC_SYS_SLVACCCTL7_I2C0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C1 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C1 (R_SYSC_SYS_SLVACCCTL7_I2C1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C2 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C2 (R_SYSC_SYS_SLVACCCTL7_I2C2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C3 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C3 (R_SYSC_SYS_SLVACCCTL7_I2C3_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_I3C (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_I3C (R_SYSC_SYS_SLVACCCTL7_I3C_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_CANFD (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_CANFD (R_SYSC_SYS_SLVACCCTL7_CANFD_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI0 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI0 (R_SYSC_SYS_SLVACCCTL7_RSPI0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI1 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI1 (R_SYSC_SYS_SLVACCCTL7_RSPI1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI2 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI2 (R_SYSC_SYS_SLVACCCTL7_RSPI2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI3 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI3 (R_SYSC_SYS_SLVACCCTL7_RSPI3_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI4 (R_SYSC->SYS_SLVACCCTL7) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI4 (R_SYSC_SYS_SLVACCCTL7_RSPI4_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF0 (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF0 (R_SYSC_SYS_SLVACCCTL8_SCIF0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF1 (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF1 (R_SYSC_SYS_SLVACCCTL8_SCIF1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF2 (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF2 (R_SYSC_SYS_SLVACCCTL8_SCIF2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF3 (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF3 (R_SYSC_SYS_SLVACCCTL8_SCIF3_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF4 (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF4 (R_SYSC_SYS_SLVACCCTL8_SCIF4_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF5 (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF5 (R_SYSC_SYS_SLVACCCTL8_SCIF5_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SCI0 (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SCI0 (R_SYSC_SYS_SLVACCCTL8_SCI0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SCI1 (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SCI1 (R_SYSC_SYS_SLVACCCTL8_SCI1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_IRDA (R_SYSC->SYS_SLVACCCTL8) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_IRDA (R_SYSC_SYS_SLVACCCTL8_IRDA_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF0 (R_SYSC->SYS_SLVACCCTL9) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF0 (R_SYSC_SYS_SLVACCCTL9_SSIF0_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF1 (R_SYSC->SYS_SLVACCCTL9) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF1 (R_SYSC_SYS_SLVACCCTL9_SSIF1_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF2 (R_SYSC->SYS_SLVACCCTL9) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF2 (R_SYSC_SYS_SLVACCCTL9_SSIF2_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF3 (R_SYSC->SYS_SLVACCCTL9) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF3 (R_SYSC_SYS_SLVACCCTL9_SSIF3_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SRC (R_SYSC->SYS_SLVACCCTL9) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SRC (R_SYSC_SYS_SLVACCCTL9_SRC_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_SPDIF (R_SYSC->SYS_SLVACCCTL9) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_SPDIF (R_SYSC_SYS_SLVACCCTL9_SPDIF_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_PDM (R_SYSC->SYS_SLVACCCTL9) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_PDM (R_SYSC_SYS_SLVACCCTL9_PDM_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_ADC (R_SYSC->SYS_SLVACCCTL10) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_ADC (R_SYSC_SYS_SLVACCCTL10_ADC_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_TSU (R_SYSC->SYS_SLVACCCTL10) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_TSU (R_SYSC_SYS_SLVACCCTL10_TSU_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_OTP (R_SYSC->SYS_SLVACCCTL11) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_OTP (R_SYSC_SYS_SLVACCCTL11_OTP_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_VBATT (R_SYSC->SYS_SLVACCCTL11) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_VBATT (R_SYSC_SYS_SLVACCCTL11_VBATT_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_CA55 (R_SYSC->SYS_SLVACCCTL12) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_CA55 (R_SYSC_SYS_SLVACCCTL12_CA55_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_CM33 (R_SYSC->SYS_SLVACCCTL12) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_CM33 (R_SYSC_SYS_SLVACCCTL12_CM33_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_CM33FPU (R_SYSC->SYS_SLVACCCTL12) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_CM33FPU (R_SYSC_SYS_SLVACCCTL12_CM33FPU_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_LSI (R_SYSC->SYS_SLVACCCTL14) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_LSI (R_SYSC_SYS_SLVACCCTL14_LSI_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_AOF (R_SYSC->SYS_SLVACCCTL16) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_AOF (R_SYSC_SYS_SLVACCCTL16_AOF_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_LP (R_SYSC->SYS_SLVACCCTL17) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_LP (R_SYSC_SYS_SLVACCCTL17_LP_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_GPREG (R_SYSC->SYS_SLVACCCTL18) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_GPREG (R_SYSC_SYS_SLVACCCTL18_GPREG_SL_Pos) +#define BSP_ACCESS_CONTROL_REG_ACCCNT_IPCONT (R_SYSC->SYS_SLVACCCTL20) +#define BSP_ACCESS_CONTROL_POS_ACCCNT_IPCONT (R_SYSC_SYS_SLVACCCTL20_IPCONT_SL_Pos) + +/*============================================== + * CPG control macros Overrides + *==============================================*/ + +#define BSP_CLKON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_CLKON_GTM) +#define BSP_CLKON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_CLKON_GTM_CLK0_ON_Pos + (channel))) +#define BSP_CLKMON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_CLKMON_GTM) +#define BSP_CLKMON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_CLKMON_GTM_CLK0_MON_Pos + (channel))) +#define BSP_RST_REG_FSP_IP_GTM(channel) (R_CPG->CPG_RST_GTM) +#define BSP_RST_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_RST_GTM_UNIT0_RSTB_Pos + (channel))) +#define BSP_RSTMON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_RSTMON_GTM) +#define BSP_RSTMON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_RSTMON_GTM_RST0_MON_Pos + (channel))) + +#define BSP_CLKON_REG_FSP_IP_XSPI(channel) (R_CPG->CPG_CLKON_SPI) +#define BSP_CLKON_BIT_FSP_IP_XSPI(channel) (0xFU << (R_CPG_CPG_CLKON_SPI_CLK0_ON_Pos)) +#define BSP_CLKMON_REG_FSP_IP_XSPI(channel) (R_CPG->CPG_CLKMON_SPI) +#define BSP_CLKMON_BIT_FSP_IP_XSPI(channel) (0xFU << (R_CPG_CPG_CLKMON_SPI_CLK0_MON_Pos)) +#define BSP_RST_REG_FSP_IP_XSPI(channel) (R_CPG->CPG_RST_SPI) +#define BSP_RST_BIT_FSP_IP_XSPI(channel) (3U << (R_CPG_CPG_RST_SPI_UNIT0_RSTB_Pos)) +#define BSP_RSTMON_REG_FSP_IP_XSPI(channel) (R_CPG->CPG_RSTMON_SPI) +#define BSP_RSTMON_BIT_FSP_IP_XSPI(channel) (3U << (R_CPG_CPG_RSTMON_SPI_RST0_MON_Pos)) + +#define BSP_DELAY_LOOP_CYCLES (49) + +#define BSP_MSTP_REG_FSP_IP_SCIF(channel) *((4U >= \ + channel) ? &R_CPG->CPG_BUS_MCPU2_MSTOP : &R_CPG->CPG_BUS_MCPU3_MSTOP) +#define BSP_MSTP_BIT_FSP_IP_SCIF(channel) ((4U >= \ + channel) ? (1U << (R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP1_ON_Pos + channel)) \ + : (1U << R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP4_ON_Pos)) + +#define BSP_MSTP_REG_FSP_IP_XSPI(channel) R_CPG->CPG_BUS_MCPU1_MSTOP +#define BSP_MSTP_BIT_FSP_IP_XSPI(channel) (1U << R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP1_ON_Pos) + +#define BSP_MSTP_REG_FSP_IP_RSPI(channel) *((1U >= channel) ? &R_CPG->CPG_BUS_MCPU1_MSTOP \ + : ((2U == channel) ? &R_CPG->CPG_BUS_MCPU2_MSTOP \ + : &R_CPG->CPG_BUS_MCPU3_MSTOP)) +#define BSP_MSTP_BIT_FSP_IP_RSPI(channel) ((1U >= \ + channel) ? (1U << (R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP14_ON_Pos + channel)) \ + : ((2U == channel) ? (1U << R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP0_ON_Pos) \ + : (1U << \ + (R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP2_ON_Pos + \ + (uint32_t) (channel - 3))))) + +/*============================================== + * IOPORT-Related Macros Overrides + *==============================================*/ + +#define OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET (24) + +/*============================================== + * SYSC-Related Macros Overrides + *==============================================*/ + +#if BSP_CURRENT_CORE == RZG3S_CORE_CM33 + #define R_BSP_IM33_DISABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 | \ + R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk;} + #define R_BSP_IM33_ENABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 & \ + ~R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk;} + #define R_BSP_WAIT_CM33_RESET() {while ((R_SYSC->SYS_LP_CM33CTL0 & \ + R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Msk) == 0U) \ + { /* wait */}; \ +} +#elif BSP_CURRENT_CORE == RZG3S_CORE_CM33_FPU + #define R_BSP_IM33_DISABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 | \ + R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Msk;} + #define R_BSP_IM33_ENABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 & \ + ~R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Msk;} + #define R_BSP_WAIT_CM33_RESET() {while ((R_SYSC->SYS_LP_CM33FPUCTL0 & \ + R_SYSC_SYS_LP_CM33FPUCTL0_SYSRESETREQ_Msk) == 0U) \ + { /* wait */}; \ +} +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*============================================== + * BSP-Related Definitions Overrides + *==============================================*/ + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x0000, /* IO port 0 */ + BSP_IO_PORT_01 = 0x1000, /* IO port 1 */ + BSP_IO_PORT_02 = 0x1100, /* IO port 2 */ + BSP_IO_PORT_03 = 0x1200, /* IO port 3 */ + BSP_IO_PORT_04 = 0x1300, /* IO port 4 */ + BSP_IO_PORT_05 = 0x0100, /* IO port 5 */ + BSP_IO_PORT_06 = 0x0200, /* IO port 6 */ + BSP_IO_PORT_07 = 0x1400, /* IO port 7 */ + BSP_IO_PORT_08 = 0x1500, /* IO port 8 */ + BSP_IO_PORT_09 = 0x1600, /* IO port 9 */ + BSP_IO_PORT_10 = 0x1700, /* IO port 10 */ + BSP_IO_PORT_11 = 0x0300, /* IO port 11 */ + BSP_IO_PORT_12 = 0x0400, /* IO port 12 */ + BSP_IO_PORT_13 = 0x0500, /* IO port 13 */ + BSP_IO_PORT_14 = 0x0600, /* IO port 14 */ + BSP_IO_PORT_15 = 0x0700, /* IO port 15 */ + BSP_IO_PORT_16 = 0x0800, /* IO port 16 */ + BSP_IO_PORT_17 = 0x0900, /* IO port 17 */ + BSP_IO_PORT_18 = 0x0A00, /* IO port 18 */ +} bsp_io_port_t; + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin_t +{ + BSP_IO_PORT_00_PIN_00 = 0x0000, /* IO port 0 pin 0 */ + BSP_IO_PORT_00_PIN_01 = 0x0001, /* IO port 0 pin 1 */ + BSP_IO_PORT_00_PIN_02 = 0x0002, /* IO port 0 pin 2 */ + BSP_IO_PORT_00_PIN_03 = 0x0003, /* IO port 0 pin 3 */ + + BSP_IO_PORT_05_PIN_00 = 0x0100, /* IO port 5 pin 0 */ + BSP_IO_PORT_05_PIN_01 = 0x0101, /* IO port 5 pin 1 */ + BSP_IO_PORT_05_PIN_02 = 0x0102, /* IO port 5 pin 2 */ + BSP_IO_PORT_05_PIN_03 = 0x0103, /* IO port 5 pin 3 */ + BSP_IO_PORT_05_PIN_04 = 0x0104, /* IO port 5 pin 4 */ + + BSP_IO_PORT_06_PIN_00 = 0x0200, /* IO port 6 pin 0 */ + BSP_IO_PORT_06_PIN_01 = 0x0201, /* IO port 6 pin 1 */ + BSP_IO_PORT_06_PIN_02 = 0x0202, /* IO port 6 pin 2 */ + BSP_IO_PORT_06_PIN_03 = 0x0203, /* IO port 6 pin 3 */ + BSP_IO_PORT_06_PIN_04 = 0x0204, /* IO port 6 pin 4 */ + + BSP_IO_PORT_11_PIN_00 = 0x0300, /* IO port 11 pin 0 */ + BSP_IO_PORT_11_PIN_01 = 0x0301, /* IO port 11 pin 1 */ + BSP_IO_PORT_11_PIN_02 = 0x0302, /* IO port 11 pin 2 */ + BSP_IO_PORT_11_PIN_03 = 0x0303, /* IO port 11 pin 3 */ + + BSP_IO_PORT_12_PIN_00 = 0x0400, /* IO port 12 pin 0 */ + BSP_IO_PORT_12_PIN_01 = 0x0401, /* IO port 12 pin 1 */ + + BSP_IO_PORT_13_PIN_00 = 0x0500, /* IO port 13 pin 0 */ + BSP_IO_PORT_13_PIN_01 = 0x0501, /* IO port 13 pin 1 */ + BSP_IO_PORT_13_PIN_02 = 0x0502, /* IO port 13 pin 2 */ + BSP_IO_PORT_13_PIN_03 = 0x0503, /* IO port 13 pin 3 */ + BSP_IO_PORT_13_PIN_04 = 0x0504, /* IO port 13 pin 4 */ + + BSP_IO_PORT_14_PIN_00 = 0x0600, /* IO port 14 pin 0 */ + BSP_IO_PORT_14_PIN_01 = 0x0601, /* IO port 14 pin 1 */ + BSP_IO_PORT_14_PIN_02 = 0x0602, /* IO port 14 pin 2 */ + + BSP_IO_PORT_15_PIN_00 = 0x0700, /* IO port 15 pin 0 */ + BSP_IO_PORT_15_PIN_01 = 0x0701, /* IO port 15 pin 1 */ + BSP_IO_PORT_15_PIN_02 = 0x0702, /* IO port 15 pin 2 */ + BSP_IO_PORT_15_PIN_03 = 0x0703, /* IO port 15 pin 3 */ + + BSP_IO_PORT_16_PIN_00 = 0x0800, /* IO port 16 pin 0 */ + BSP_IO_PORT_16_PIN_01 = 0x0801, /* IO port 16 pin 1 */ + + BSP_IO_PORT_17_PIN_00 = 0x0900, /* IO port 17 pin 0 */ + BSP_IO_PORT_17_PIN_01 = 0x0901, /* IO port 17 pin 1 */ + BSP_IO_PORT_17_PIN_02 = 0x0902, /* IO port 17 pin 2 */ + BSP_IO_PORT_17_PIN_03 = 0x0903, /* IO port 17 pin 3 */ + + BSP_IO_PORT_18_PIN_00 = 0x0A00, /* IO port 18 pin 0 */ + BSP_IO_PORT_18_PIN_01 = 0x0A01, /* IO port 18 pin 1 */ + BSP_IO_PORT_18_PIN_02 = 0x0A02, /* IO port 18 pin 2 */ + BSP_IO_PORT_18_PIN_03 = 0x0A03, /* IO port 18 pin 3 */ + BSP_IO_PORT_18_PIN_04 = 0x0A04, /* IO port 18 pin 4 */ + BSP_IO_PORT_18_PIN_05 = 0x0A05, /* IO port 18 pin 5 */ + + BSP_IO_PORT_01_PIN_00 = 0x1000, /* IO port 1 pin 0 */ + BSP_IO_PORT_01_PIN_01 = 0x1001, /* IO port 1 pin 1 */ + BSP_IO_PORT_01_PIN_02 = 0x1002, /* IO port 1 pin 2 */ + BSP_IO_PORT_01_PIN_03 = 0x1003, /* IO port 1 pin 3 */ + BSP_IO_PORT_01_PIN_04 = 0x1004, /* IO port 1 pin 4 */ + + BSP_IO_PORT_02_PIN_00 = 0x1100, /* IO port 2 pin 0 */ + BSP_IO_PORT_02_PIN_01 = 0x1101, /* IO port 2 pin 1 */ + BSP_IO_PORT_02_PIN_02 = 0x1102, /* IO port 2 pin 2 */ + BSP_IO_PORT_02_PIN_03 = 0x1103, /* IO port 2 pin 3 */ + + BSP_IO_PORT_03_PIN_00 = 0x1200, /* IO port 3 pin 0 */ + BSP_IO_PORT_03_PIN_01 = 0x1201, /* IO port 3 pin 1 */ + BSP_IO_PORT_03_PIN_02 = 0x1202, /* IO port 3 pin 2 */ + BSP_IO_PORT_03_PIN_03 = 0x1203, /* IO port 3 pin 3 */ + + BSP_IO_PORT_04_PIN_00 = 0x1300, /* IO port 4 pin 0 */ + BSP_IO_PORT_04_PIN_01 = 0x1301, /* IO port 4 pin 1 */ + BSP_IO_PORT_04_PIN_02 = 0x1302, /* IO port 4 pin 2 */ + BSP_IO_PORT_04_PIN_03 = 0x1303, /* IO port 4 pin 3 */ + BSP_IO_PORT_04_PIN_04 = 0x1304, /* IO port 4 pin 4 */ + BSP_IO_PORT_04_PIN_05 = 0x1305, /* IO port 4 pin 5 */ + + BSP_IO_PORT_07_PIN_00 = 0x1400, /* IO port 7 pin 0 */ + BSP_IO_PORT_07_PIN_01 = 0x1401, /* IO port 7 pin 1 */ + BSP_IO_PORT_07_PIN_02 = 0x1402, /* IO port 7 pin 2 */ + BSP_IO_PORT_07_PIN_03 = 0x1403, /* IO port 7 pin 3 */ + BSP_IO_PORT_07_PIN_04 = 0x1404, /* IO port 7 pin 4 */ + + BSP_IO_PORT_08_PIN_00 = 0x1500, /* IO port 8 pin 0 */ + BSP_IO_PORT_08_PIN_01 = 0x1501, /* IO port 8 pin 1 */ + BSP_IO_PORT_08_PIN_02 = 0x1502, /* IO port 8 pin 2 */ + BSP_IO_PORT_08_PIN_03 = 0x1503, /* IO port 8 pin 3 */ + BSP_IO_PORT_08_PIN_04 = 0x1504, /* IO port 8 pin 4 */ + + BSP_IO_PORT_09_PIN_00 = 0x1600, /* IO port 9 pin 0 */ + BSP_IO_PORT_09_PIN_01 = 0x1601, /* IO port 9 pin 1 */ + BSP_IO_PORT_09_PIN_02 = 0x1602, /* IO port 9 pin 2 */ + BSP_IO_PORT_09_PIN_03 = 0x1603, /* IO port 9 pin 3 */ + + BSP_IO_PORT_10_PIN_00 = 0x1700, /* IO port 10 pin 0 */ + BSP_IO_PORT_10_PIN_01 = 0x1701, /* IO port 10 pin 1 */ + BSP_IO_PORT_10_PIN_02 = 0x1702, /* IO port 10 pin 2 */ + BSP_IO_PORT_10_PIN_03 = 0x1703, /* IO port 10 pin 3 */ + BSP_IO_PORT_10_PIN_04 = 0x1704, /* IO port 10 pin 4 */ + + /* Special purpose port */ + BSP_IO_NMI = 0xFFFF0000, /* NMI */ + + BSP_IO_TMS_SWDIO = 0xFFFF0100, /* TMS_SWDIO */ + BSP_IO_TDO = 0xFFFF0101, /* TDO */ + + BSP_IO_AUDIO_CLK1 = 0xFFFF0200, /* AUDIO_CLK1 */ + BSP_IO_AUDIO_CLK2 = 0xFFFF0201, /* AUDIO_CLK2 */ + + BSP_IO_XSPI_SPCLK = 0xFFFF0400, /* XSPI_SPCLK */ + BSP_IO_XSPI_RESET_N = 0xFFFF0401, /* XSPI_RESET_N */ + BSP_IO_XSPI_WP_N = 0xFFFF0402, /* XSPI_WP_N */ + BSP_IO_XSPI_DS = 0xFFFF0403, /* XSPI_DS */ + BSP_IO_XSPI_CS0_N = 0xFFFF0404, /* XSPI_CS0_N */ + BSP_IO_XSPI_CS1_N = 0xFFFF0405, /* XSPI_CS1_N */ + + BSP_IO_XSPI_IO0 = 0xFFFF0500, /* XSPI_IO0 */ + BSP_IO_XSPI_IO1 = 0xFFFF0501, /* XSPI_IO1 */ + BSP_IO_XSPI_IO2 = 0xFFFF0502, /* XSPI_IO2 */ + BSP_IO_XSPI_IO3 = 0xFFFF0503, /* XSPI_IO3 */ + BSP_IO_XSPI_IO4 = 0xFFFF0504, /* XSPI_IO4 */ + BSP_IO_XSPI_IO5 = 0xFFFF0505, /* XSPI_IO5 */ + BSP_IO_XSPI_IO6 = 0xFFFF0506, /* XSPI_IO6 */ + BSP_IO_XSPI_IO7 = 0xFFFF0507, /* XSPI_IO7 */ + + BSP_IO_WDTOVF_PERROUT = 0xFFFF0600, /* WDTOVF_PERROUT */ + + BSP_IO_I3C_SDA = 0xFFFF0900, /* I3C_SDA */ + BSP_IO_I3C_SCL = 0xFFFF0901, /* I3C_SCL */ + + BSP_IO_SD0_CLK = 0xFFFF1000, /* CD0_CLK */ + BSP_IO_SD0_CMD = 0xFFFF1001, /* CD0_CMD */ + BSP_IO_SD0_RST_N = 0xFFFF1002, /* CD0_RST_N */ + + BSP_IO_SD0_DATA0 = 0xFFFF1100, /* SD0_DATA0 */ + BSP_IO_SD0_DATA1 = 0xFFFF1101, /* SD0_DATA1 */ + BSP_IO_SD0_DATA2 = 0xFFFF1102, /* SD0_DATA2 */ + BSP_IO_SD0_DATA3 = 0xFFFF1103, /* SD0_DATA3 */ + BSP_IO_SD0_DATA4 = 0xFFFF1104, /* SD0_DATA4 */ + BSP_IO_SD0_DATA5 = 0xFFFF1105, /* SD0_DATA5 */ + BSP_IO_SD0_DATA6 = 0xFFFF1106, /* SD0_DATA6 */ + BSP_IO_SD0_DATA7 = 0xFFFF1107, /* SD0_DATA7 */ + + BSP_IO_SD1_CLK = 0xFFFF1200, /* SD1_CLK */ + BSP_IO_SD1_CMD = 0xFFFF1201, /* SD1_CMD */ + + BSP_IO_SD1_DATA0 = 0xFFFF1300, /* SD1_DATA0 */ + BSP_IO_SD1_DATA1 = 0xFFFF1301, /* SD1_DATA1 */ + BSP_IO_SD1_DATA2 = 0xFFFF1302, /* SD1_DATA2 */ + BSP_IO_SD1_DATA3 = 0xFFFF1303, /* SD1_DATA3 */ +} bsp_io_port_pin_t; + +/*============================================== + * DMAC_B External Detection Overrides + *==============================================*/ + + /** Detection method of the external DMA request signal. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */ +typedef enum e_dmac_b_external_detection +{ + DMAC_B_EXTERNAL_DETECTION_NO_DETECTION = 0, ///< Not using hardware detection. +} dmac_b_external_detection_t; + +/** access control. */ +typedef enum e_acc_control_ip +{ + ACCCNT_SRAM0 = 0, + ACCCNT_SRAM1, + ACCCNT_SRAM2, + ACCCNT_SRAM3, + ACCCNT_TZC0, + ACCCNT_TZC1, + ACCCNT_TZC2, + ACCCNT_TZC3, + ACCCNT_TZC5, + ACCCNT_TZC6, + ACCCNT_CST, + ACCCNT_CPG, + ACCCNT_SYSC, + ACCCNT_SYC, + ACCCNT_GIC, + ACCCNT_IA55_IM33, + ACCCNT_GPIO, + ACCCNT_MHU, + ACCCNT_DMAC0, + ACCCNT_DMAC1, + ACCCNT_OSTM0, + ACCCNT_OSTM1, + ACCCNT_OSTM2, + ACCCNT_OSTM3, + ACCCNT_OSTM4, + ACCCNT_OSTM5, + ACCCNT_OSTM6, + ACCCNT_OSTM7, + ACCCNT_WDT0, + ACCCNT_WDT1, + ACCCNT_WDT2, + ACCCNT_RTC, + ACCCNT_MTU3A, + ACCCNT_POE3, + ACCCNT_GPT, + ACCCNT_POEG, + ACCCNT_DDR, + ACCCNT_XSPI, + ACCCNT_OCTA, + ACCCNT_USBT, + ACCCNT_USB20, + ACCCNT_USB21, + ACCCNT_SDHI0, + ACCCNT_SDHI1, + ACCCNT_SDHI2, + ACCCNT_ETH0, + ACCCNT_ETH1, + ACCCNT_PCIE, + ACCCNT_I2C0, + ACCCNT_I2C1, + ACCCNT_I2C2, + ACCCNT_I2C3, + ACCCNT_I3C, + ACCCNT_CANFD, + ACCCNT_RSPI0, + ACCCNT_RSPI1, + ACCCNT_RSPI2, + ACCCNT_RSPI3, + ACCCNT_RSPI4, + ACCCNT_SCIF0, + ACCCNT_SCIF1, + ACCCNT_SCIF2, + ACCCNT_SCIF3, + ACCCNT_SCIF4, + ACCCNT_SCIF5, + ACCCNT_SCI0, + ACCCNT_SCI1, + ACCCNT_IRDA, + ACCCNT_SSIF0, + ACCCNT_SSIF1, + ACCCNT_SSIF2, + ACCCNT_SSIF3, + ACCCNT_SRC, + ACCCNT_SPDIF, + ACCCNT_PDM, + ACCCNT_ADC, + ACCCNT_TSU, + ACCCNT_OTP, + ACCCNT_VBATT, + ACCCNT_CA55, + ACCCNT_CM33, + ACCCNT_CM33FPU, + ACCCNT_LSI, + ACCCNT_AOF, + ACCCNT_LP, + ACCCNT_GPREG, + ACCCNT_IPCONT, +} fsp_acc_control_ip_t; + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_GTM = 0, ///< General Timer + FSP_IP_GPT = 1, ///< General PWM Timer + FSP_IP_POEG = 2, ///< Port Output Enable for GPT + FSP_IP_PORT = 3, ///< I/O Ports + FSP_IP_IM33 = 4, ///< IM33 (Interrupt controller) + FSP_IP_SCIF = 5, ///< Serial Communications Interface with FIFO + FSP_IP_RIIC = 6, ///< I2C Bus Interface + FSP_IP_RSPI = 7, ///< Renesas Serial Peripheral Interface + FSP_IP_MHU = 8, ///< Message Handling Unit + FSP_IP_DMAC = 9, ///< Direct Memory Access Controller + FSP_IP_DMAC_s = 9, ///< Direct Memory Access Controller + FSP_IP_SSI = 10, ///< Serial Sound Interface + FSP_IP_CANFD = 11, ///< CANFD Interface (RS-CANFD) + FSP_IP_ADC = 12, ///< A/D Converter + FSP_IP_TSU = 13, ///< Thermal Sensor Unit + FSP_IP_WDT = 14, ///< Watchdog Timer + FSP_IP_SCI = 15, ///< Serial Communications Interface + FSP_IP_XSPI = 16 ///< Expanded Serial Peripheral Interface +} fsp_ip_t; + +/* Private enum used in R_FSP_SystemClockHzGet. */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_ICLK = 0, /* Cortex-A55 Clock */ + FSP_PRIV_CLOCK_I2CLK, /* Cortex-M33 Clock */ + FSP_PRIV_CLOCK_I3CLK, /* Cortex-M33 FPU Clock */ + FSP_PRIV_CLOCK_S0CLK, /* DDR-PHY Clock */ + FSP_PRIV_CLOCK_OC0CLK, /* OCTA0 Clock */ + FSP_PRIV_CLOCK_OC1CLK, /* OCTA1 Clock */ + FSP_PRIV_CLOCK_SPI0CLK, /* SPI0 Clock */ + FSP_PRIV_CLOCK_SPI1CLK, /* SPI1 Clock */ + FSP_PRIV_CLOCK_SD0CLK, /* SDH0 Clock */ + FSP_PRIV_CLOCK_SD1CLK, /* SDH1 Clock */ + FSP_PRIV_CLOCK_SD2CLK, /* SDH2 Clock */ + FSP_PRIV_CLOCK_M0CLK, /* VCP, LCDC Clock */ + FSP_PRIV_CLOCK_HPCLK, /* Ethernet Clock */ + FSP_PRIV_CLOCK_TSUCLK, /* TSU Clock */ + FSP_PRIV_CLOCK_ZTCLK, /* JAUTH Clock */ + FSP_PRIV_CLOCK_P0CLK, /* APB-BUS Clock */ + FSP_PRIV_CLOCK_P1CLK, /* AXI-BUS Clock */ + FSP_PRIV_CLOCK_P2CLK, /* P2CLK */ + FSP_PRIV_CLOCK_P3CLK, /* P3CLK */ + FSP_PRIV_CLOCK_P4CLK, /* P4CLK */ + FSP_PRIV_CLOCK_P5CLK, /* P5CLK */ + FSP_PRIV_CLOCK_ATCLK, /* ATCLK */ + FSP_PRIV_CLOCK_OSCCLK, /* OSC Clock */ + FSP_PRIV_CLOCK_OSCCLK2, /* OSC2 Clock */ + FSP_PRIV_CLOCK_NUM, +} fsp_priv_clock_t; + +/*============================================== + * IOPORT Overrides + *==============================================*/ + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_peripheral +{ + /** Pin will function as a Mode1 peripheral pin */ + IOPORT_PERIPHERAL_MODE1 = (0x0UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode2 peripheral pin */ + IOPORT_PERIPHERAL_MODE2 = (0x1UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode3 peripheral pin */ + IOPORT_PERIPHERAL_MODE3 = (0x2UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode4 peripheral pin */ + IOPORT_PERIPHERAL_MODE4 = (0x3UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode5 peripheral pin */ + IOPORT_PERIPHERAL_MODE5 = (0x4UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode6 peripheral pin */ + IOPORT_PERIPHERAL_MODE6 = (0x5UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode7 peripheral pin */ + IOPORT_PERIPHERAL_MODE7 = (0x6UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a Mode8 peripheral pin */ + IOPORT_PERIPHERAL_MODE8 = (0x7UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), +} ioport_peripheral_t; + +/*============================================== + * Transfer API Overrides + *==============================================*/ + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** Normal mode. */ + TRANSFER_MODE_NORMAL = 0, + + /** Block mode. */ + TRANSFER_MODE_BLOCK = 1 +} transfer_mode_t; + +/** Transfer size specifies the size of each individual transfer. */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value + TRANSFER_SIZE_8_BYTE = 3, ///< Each transfer transfers a 64-bit value + TRANSFER_SIZE_16_BYTE = 4, ///< Each transfer transfers a 128-bit value + TRANSFER_SIZE_32_BYTE = 5, ///< Each transfer transfers a 256-bit value + TRANSFER_SIZE_64_BYTE = 6, ///< Each transfer transfers a 512-bit value + TRANSFER_SIZE_128_BYTE = 7 ///< Each transfer transfers a 1024-bit value +} transfer_size_t; + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 0, + + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 1 +} transfer_addr_mode_t; + +typedef struct st_transfer_info +{ + /** Select what happens to destination address after each transfer. */ + transfer_addr_mode_t dest_addr_mode; + + /** Select what happens to source address after each transfer. */ + transfer_addr_mode_t src_addr_mode; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode; + + /** Source address. */ + void const * volatile p_src; + + /** Destination address. */ + void * volatile p_dest; + + /** The total number of transfer bytes. */ + volatile uint32_t length; + + /** Select source data size to transfer at once. */ + transfer_size_t src_size; + + /** Select destination data size to transfer at once. */ + transfer_size_t dest_size; + + /** Next1 Register set settings */ + void const * p_next1_src; + void * p_next1_dest; + uint32_t next1_length; +} transfer_info_t; + +/*============================================== + * ADC API Overrides + *==============================================*/ + +/** ADC Information Structure for Transfer Interface */ +typedef struct st_adc_info +{ + volatile const void * p_address; ///< The address to start reading the data from + uint32_t length; ///< The total number of transfers to read + transfer_size_t transfer_size; ///< The size of each transfer + uint32_t calibration_data1; ///< Temperature sensor calibration data1 + uint32_t calibration_data2; ///< Temperature sensor calibration data2 +} adc_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_reset.h b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_reset.h new file mode 100644 index 00000000..895d0fc3 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_reset.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_reset.h + * Version : 1.00 + * Description : bsp_reset header + *********************************************************************************************************************/ + +#ifndef BSP_RESET_H +#define BSP_RESET_H + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ +#if BSP_CURRENT_CORE == RZG3S_CORE_CM33 + #define R_BSP_SECURE_VECTOR_SET(vector) {R_SYSC->SYS_CM33_CFG2 = (vector);} +#elif BSP_CURRENT_CORE == RZG3S_CORE_CM33_FPU + #define R_BSP_SECURE_VECTOR_SET(vector) {R_SYSC->SYS_CM33FPU_CFG2 = (vector);} +#endif + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * @addtogroup BSP_MPU_RZG3S + * @{ + *********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MPU_RZG3S) */ + +#endif /* BSP_RESET_H */ diff --git a/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_slave_address.h b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_slave_address.h new file mode 100644 index 00000000..1f8828aa --- /dev/null +++ b/drivers/rz/fsp/src/rzg/bsp/mcu/rzg3s/bsp_slave_address.h @@ -0,0 +1,81 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : bsp_slave_address.h + * Version : 1.00 + * Description : bsp_slave_address header + *********************************************************************************************************************/ + +#ifndef BSP_SLAVE_ADDRESS_H +#define BSP_SLAVE_ADDRESS_H + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ +#define BSP_ADDRESS_OFFSET_MASK (0x0FFFFFFF) + +#define BSP_ADDRESS_CM_SRAM_CODE_SECURE_BASE (0x00000000) +#define BSP_ADDRESS_CM_SRAM_CODE_NONSECURE_BASE (0x10000000) +#define BSP_ADDRESS_CM_SRAM_DATA_SECURE_BASE (0x20000000) +#define BSP_ADDRESS_CM_SRAM_DATA_NONSECURE_BASE (0x30000000) +#define BSP_ADDRESS_CA_SRAM_BASE (0x00000000) +#define BSP_ADDRESS_SRAM_SIZE (0x10000000) + +#define BSP_ADDRESS_CM_IOREG_SECURE_BASE (0x40000000) +#define BSP_ADDRESS_CM_IOREG_NONSECURE_BASE (0x50000000) +#define BSP_ADDRESS_CA_IOREG_BASE (0x10000000) +#define BSP_ADDRESS_IOREG_SIZE (0x10000000) + +#define BSP_ADDRESS_CM_DDR_SECURE_BASE (0x60000000) +#define BSP_ADDRESS_CM_DDR_NONSECURE_BASE (0x70000000) +#define BSP_ADDRESS_CA_DDR_BASE (0x40000000) +#define BSP_ADDRESS_DDR_SIZE (0x10000000) + +#define BSP_ADDRESS_CM_SPI_SECURE_BASE (0x80000000) +#define BSP_ADDRESS_CM_SPI_NONSECURE_BASE (0x90000000) +#define BSP_ADDRESS_CA_SPI_BASE (0x20000000) +#define BSP_ADDRESS_SPI_SIZE (0x10000000) + +#define BSP_ADDRESS_CM_PCIE_SECURE_BASE (0xA0000000) +#define BSP_ADDRESS_CM_PCIE_NONSECURE_BASE (0xB0000000) +#define BSP_ADDRESS_CA_PCIE_BASE (0x30000000) +#define BSP_ADDRESS_PCIE_SIZE (0x10000000) + +#define BSP_ADDRESS_CONVERT_TABLE_BODY \ + {BSP_ADDRESS_CM_SRAM_CODE_SECURE_BASE, BSP_ADDRESS_CA_SRAM_BASE, BSP_ADDRESS_SRAM_SIZE}, \ + {BSP_ADDRESS_CM_SRAM_CODE_NONSECURE_BASE, BSP_ADDRESS_CA_SRAM_BASE, BSP_ADDRESS_SRAM_SIZE}, \ + {BSP_ADDRESS_CM_SRAM_DATA_SECURE_BASE, BSP_ADDRESS_CA_SRAM_BASE, BSP_ADDRESS_SRAM_SIZE}, \ + {BSP_ADDRESS_CM_SRAM_DATA_NONSECURE_BASE, BSP_ADDRESS_CA_SRAM_BASE, BSP_ADDRESS_SRAM_SIZE}, \ + {BSP_ADDRESS_CM_IOREG_SECURE_BASE, BSP_ADDRESS_CA_IOREG_BASE, BSP_ADDRESS_IOREG_SIZE}, \ + {BSP_ADDRESS_CM_IOREG_NONSECURE_BASE, BSP_ADDRESS_CA_IOREG_BASE, BSP_ADDRESS_IOREG_SIZE}, \ + {BSP_ADDRESS_CM_DDR_SECURE_BASE, BSP_ADDRESS_CA_DDR_BASE, BSP_ADDRESS_DDR_SIZE}, \ + {BSP_ADDRESS_CM_DDR_NONSECURE_BASE, BSP_ADDRESS_CA_DDR_BASE, BSP_ADDRESS_DDR_SIZE}, \ + {BSP_ADDRESS_CM_SPI_SECURE_BASE, BSP_ADDRESS_CA_SPI_BASE, BSP_ADDRESS_SPI_SIZE}, \ + {BSP_ADDRESS_CM_SPI_NONSECURE_BASE, BSP_ADDRESS_CA_SPI_BASE, BSP_ADDRESS_SPI_SIZE}, \ + {BSP_ADDRESS_CM_PCIE_SECURE_BASE, BSP_ADDRESS_CA_PCIE_BASE, BSP_ADDRESS_PCIE_SIZE}, \ + {BSP_ADDRESS_CM_PCIE_NONSECURE_BASE, BSP_ADDRESS_CA_PCIE_BASE, BSP_ADDRESS_PCIE_SIZE} + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * @addtogroup BSP_MPU_RZG3S + * @{ + *********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MPU_RZG3S) */ + +#endif /* BSP_SLAVE_ADDRESS_H */ diff --git a/drivers/rz/fsp/src/rzg/r_ioport/r_ioport.c b/drivers/rz/fsp/src/rzg/r_ioport/r_ioport.c new file mode 100644 index 00000000..bcd51557 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/r_ioport/r_ioport.c @@ -0,0 +1,1290 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "r_ioport_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "PORT" in ASCII, used to determine if the module is open */ +#define IOPORT_OPEN (0x504F5254U) +#define IOPORT_CLOSED (0x00000000U) + +/* Shift to get pin 0 on a package in extended data. */ +#define IOPORT_PRV_EXISTS_B0_SHIFT (16UL) + +/* Mask to determine if any pins on port exist on this package. */ +#define IOPORT_PRV_PORT_EXISTS_MASK (0xFFFF0000U) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define IOPORT_PRV_PORT_OFFSET (8U) + +#define IOPORT_PRV_PORT_BITS (0xFF00U) +#define IOPORT_PRV_PIN_BITS (0x00FFU) + +/* Macro definition for generating the values to set for each register from the ioport_cfg_options_t enums. */ +#define IOPORT_PRV_P_OFFSET (0U) +#define IOPORT_PRV_PM_OFFSET (2U) +#define IOPORT_PRV_PUPD_OFFSET (4U) +#define IOPORT_PRV_IOLH_OFFSET (10U) +#define IOPORT_PRV_ISEL_OFFSET (14U) +#define IOPORT_PRV_PMC_OFFSET (16U) +#define IOPORT_PRV_SR_OFFSET (17U) +#define IOPORT_PRV_IEN_OFFSET (18U) +#define IOPORT_PRV_FILONOFF_OFFSET (19U) +#define IOPORT_PRV_FILNUM_OFFSET (20U) +#define IOPORT_PRV_FILCLKSEL_OFFSET (22U) +#define IOPORT_PRV_PFC_OFFSET (24U) + +#define IOPORT_PRV_ELC_PEL_MASK (0x80) +#define IOOPRT_PRV_ELC_PGC_MASK (0x88) +#define IOPORT_PRV_ELC_PEL_PSM_HIGH (0x20) + +#define IOPORT_PRV_PERIPHERAL_FUNCTION (1U << 16) + +#define IOPORT_PRV_2BIT_MASK (0x3U) +#define IOPORT_PRV_8BIT_MASK (0xFFU) + +#define IOPORT_PRV_BITFIELD_1BIT (1U) +#define IOPORT_PRV_BITFIELD_2BIT (3U) +#define IOPORT_PRV_BITFIELD_3BIT (7U) + +#define IOPORT_PRV_POS_ALIGN_2BIT (2U) +#define IOPORT_PRV_POS_ALIGN_4BIT (4U) +#define IOPORT_PRV_POS_ALIGN_8BIT (8U) + +#define IOPORT_PRV_SET_PWPR_PFSWE (0x40U) +#define IOPORT_PRV_SET_PWPR_BOWI (0x80U) + +#define IOPORT_PRV_NONMASK_ACCESS (0xFFFFFFFFUL) + +#define IOPORT_PRV_P_REG_BASE_SET(base) IOPORT_PRV_P_REG_BASE(base) +#define IOPORT_PRV_P_REG_BASE(base) (&R_GPIO->P ## base) +#define IOPORT_PRV_PM_REG_BASE_SET(base) IOPORT_PRV_PM_REG_BASE(base) +#define IOPORT_PRV_PM_REG_BASE(base) (&R_GPIO->PM ## base) +#define IOPORT_PRV_PMC_REG_BASE_SET(base) IOPORT_PRV_PMC_REG_BASE(base) +#define IOPORT_PRV_PMC_REG_BASE(base) (&R_GPIO->PMC ## base) +#define IOPORT_PRV_PFC_REG_BASE_SET(base) IOPORT_PRV_PFC_REG_BASE(base) +#define IOPORT_PRV_PFC_REG_BASE(base) (&R_GPIO->PFC ## base) +#define IOPORT_PRV_PIN_REG_BASE_SET(base) IOPORT_PRV_PIN_REG_BASE(base) +#define IOPORT_PRV_PIN_REG_BASE(base) (&R_GPIO->PIN ## base) +#define IOPORT_PRV_IEN_REG_BASE_SET(base) IOPORT_PRV_IEN_REG_BASE(base) +#define IOPORT_PRV_IEN_REG_BASE(base) (&R_GPIO->IEN ## base) +#define IOPORT_PRV_ISEL_REG_BASE_SET(base) IOPORT_PRV_ISEL_REG_BASE(base) +#define IOPORT_PRV_ISEL_REG_BASE(base) (&R_GPIO->ISEL ## base) +#define IOPORT_PRV_IOLH_REG_BASE_SET(base) IOPORT_PRV_IOLH_REG_BASE(base) +#define IOPORT_PRV_IOLH_REG_BASE(base) (&R_GPIO->IOLH ## base) +#define IOPORT_PRV_SR_REG_BASE_SET(base) IOPORT_PRV_SR_REG_BASE(base) +#define IOPORT_PRV_SR_REG_BASE(base) (&R_GPIO->SR ## base) +#define IOPORT_PRV_PUPD_REG_BASE_SET(base) IOPORT_PRV_PUPD_REG_BASE(base) +#define IOPORT_PRV_PUPD_REG_BASE(base) (&R_GPIO->PUPD ## base) +#define IOPORT_PRV_FILONOFF_REG_BASE_SET(base) IOPORT_PRV_FILONOFF_REG_BASE(base) +#define IOPORT_PRV_FILONOFF_REG_BASE(base) (&R_GPIO->FILONOFF ## base) +#define IOPORT_PRV_FILNUM_REG_BASE_SET(base) IOPORT_PRV_FILNUM_REG_BASE(base) +#define IOPORT_PRV_FILNUM_REG_BASE(base) (&R_GPIO->FILNUM ## base) +#define IOPORT_PRV_FILCLKSEL_REG_BASE_SET(base) IOPORT_PRV_FILCLKSEL_REG_BASE(base) +#define IOPORT_PRV_FILCLKSEL_REG_BASE(base) (&R_GPIO->FILCLKSEL ## base) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* IOPort Implementation of IOPort Driver */ +const ioport_api_t g_ioport_on_ioport = +{ + .open = R_IOPORT_Open, + .close = R_IOPORT_Close, + .pinsCfg = R_IOPORT_PinsCfg, + .pinCfg = R_IOPORT_PinCfg, + .pinEventInputRead = R_IOPORT_PinEventInputRead, + .pinEventOutputWrite = R_IOPORT_PinEventOutputWrite, + .pinRead = R_IOPORT_PinRead, + .pinWrite = R_IOPORT_PinWrite, + .portDirectionSet = R_IOPORT_PortDirectionSet, + .portEventInputRead = R_IOPORT_PortEventInputRead, + .portEventOutputWrite = R_IOPORT_PortEventOutputWrite, + .portRead = R_IOPORT_PortRead, + .portWrite = R_IOPORT_PortWrite, +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_ioport_pins_config(const ioport_cfg_t * p_cfg); + +static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value); + +static void r_ioport_dedicated_port_cfg(bsp_io_port_pin_t pin, uint32_t value); +static void r_ioport_peri_mode_pin_config(bsp_io_port_pin_t pin, uint32_t value); +static void r_ioport_port_mode_pin_config(bsp_io_port_pin_t pin, uint32_t value); +static void r_ioport_make_port_pin_num(bsp_io_port_pin_t pin, uint8_t * p_port_number, uint8_t * p_pin_number); +static void r_ioport_regwrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask); +static void r_ioport_regwrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask); +static void r_ioport_regwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask); + +static void r_ioport_event_config(const ioport_extend_cfg_t * p_extend_cfg_data); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes internal driver data, then calls pin configuration function to configure pins. + * + * @retval FSP_SUCCESS Pin configuration data written to PFS register(s) + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); + FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set driver status to open */ + p_instance_ctrl->open = IOPORT_OPEN; + + p_instance_ctrl->p_cfg = p_cfg; + + r_ioport_pins_config(p_cfg); + + r_ioport_event_config(p_cfg->p_extend); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets IOPORT registers. Implements @ref ioport_api_t::close + * + * @retval FSP_SUCCESS The IOPORT was successfully uninitialized + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set state to closed */ + p_instance_ctrl->open = IOPORT_CLOSED; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the functions of multiple pins by loading configuration data into each registers. + * Implements @ref ioport_api_t::pinsCfg. + * + * This function initializes the supplied list of each registers with the supplied values. This data define in + * pin_data.c. Different pin configurations can be loaded for different situations such as low power modes and testing. + * + * @retval FSP_SUCCESS Pin configuration data written to each registers + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg. + * + * @retval FSP_SUCCESS Pin configured + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. + * This function will change the configuration of the pin with the new configuration. For example it is not possible + * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To + * achieve this the original settings with the required change will need to be written using this function. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_BSP_PinAccessEnable(); + + r_ioport_pfs_write(pin, cfg); + + R_BSP_PinAccessDisable(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the level on a pin. Implements @ref ioport_api_t::pinRead. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different pins. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_pin_value = (bsp_io_level_t) R_BSP_PinRead(pin); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value on an IO port. Implements @ref ioport_api_t::portRead. + * + * The specified port will be read, and the levels for all the pins will be returned. + * Each bit in the returned value corresponds to a pin on the port. For example, bit 4 corresponds + * to pin 4, bit 3 to pin 3, and so on. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_port_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + volatile const uint8_t * p_ioport_regs; + p_ioport_regs = IOPORT_PRV_PIN_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_ioport_regs = &p_ioport_regs[port >> IOPORT_PRV_PORT_OFFSET]; + + /* Read current value of PIN register for the specified port */ + *p_port_value = *p_ioport_regs; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite. + * + * The input value will be written to the specified port. Each bit in the value parameter corresponds to a bit + * on the port. For example, bit 4 corresponds to pin 4, bit 3 to pin 3, and so on. + * Each bit in the mask parameter corresponds to a pin on the port. + * + * Only the bits with the corresponding bit in the mask value set will be updated. + * For example, value = 0xFFFF, mask = 0x0003 results in only bits 0 and 1 being updated. + * + * @retval FSP_SUCCESS Port written to + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + volatile uint8_t * p_ioport_regs; + p_ioport_regs = IOPORT_PRV_P_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_ioport_regs = &p_ioport_regs[port >> IOPORT_PRV_PORT_OFFSET]; + + /* Set the port level to P register */ + r_ioport_regwrite_8(p_ioport_regs, (uint8_t) value, 0, (uint8_t) mask); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite. + * + * @retval FSP_SUCCESS Pin written to + * @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opene + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different pins. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + bsp_io_port_t port = (bsp_io_port_t) (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin); + ioport_size_t shift = IOPORT_PRV_PIN_BITS & (ioport_size_t) pin; + ioport_size_t pin_mask = (ioport_size_t) (1U << shift); + + /* Get the port address */ + volatile uint8_t * p_ioport_regs; + p_ioport_regs = IOPORT_PRV_P_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_ioport_regs = &p_ioport_regs[port >> IOPORT_PRV_PORT_OFFSET]; + + /* Set the pin level to P register */ + r_ioport_regwrite_8(p_ioport_regs, (uint8_t) level, (uint8_t) shift, (uint8_t) pin_mask); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet(). + * + * Multiple pins on a port can be set to inputs or outputs at once. + * Each bit in the mask parameter corresponds to a pin on the port. For example, bit[9:8] corresponds to pin 4, + * bit[7:6] to pin 3, and so on. + * If bits are set to b'11 then the corresponding pin will be changed to an input or an output or Hi-Z as specified by + * the direction values. If a mask bits are set to b'00 then the direction of the pin will not be changed. + * + * @retval FSP_SUCCESS Port direction updated + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + volatile uint16_t * p_ioport_regs; + p_ioport_regs = IOPORT_PRV_PM_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_ioport_regs = &p_ioport_regs[port >> IOPORT_PRV_PORT_OFFSET]; + + /* Set the port direction to PM register */ + r_ioport_regwrite_16(p_ioport_regs, direction_values, 0, mask); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead(). + * + * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port. + * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * + * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_UNSUPPORTED The function is not supported on the device which doesn't support ELC. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data) +{ +#if !(BSP_FEATURE_BSP_HAS_ELC) + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(p_event_data); + + return FSP_ERR_UNSUPPORTED; +#else + uint8_t portgroup = 0U; + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_event_data); + FSP_ERROR_RETURN((port == BSP_FEATURE_IOPORT_GROUP1_PORT) || (port == BSP_FEATURE_IOPORT_GROUP2_PORT), + FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend; + + /* Get register address */ + R_GPIO_Type * p_ioport_regs = R_GPIO; + + /* Get port group number for the specified port */ + if (BSP_FEATURE_IOPORT_GROUP1_PORT == port) + { + portgroup = 0U; + } + else if (BSP_FEATURE_IOPORT_GROUP2_PORT == port) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + /* Read current value of buffer value from ELC_PDBF register for the specified port group */ + *p_event_data = + (uint16_t) (p_ioport_regs->PDBF[portgroup].ELC_PDBF & elc_cfg->p_port_group_input_cfg[portgroup].pin_select); + + return FSP_SUCCESS; +#endif +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead. + * + * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT. + * @retval FSP_ERR_UNSUPPORTED The function is not supported on the device which doesn't support ELC. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event) +{ +#if !(BSP_FEATURE_BSP_HAS_ELC) + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(pin); + FSP_PARAMETER_NOT_USED(p_pin_event); + + return FSP_ERR_UNSUPPORTED; +#else + uint8_t portgroup = 0U; + uint8_t portvalue; + uint8_t mask; + + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_event); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number == BSP_FEATURE_IOPORT_GROUP1_PORT >> IOPORT_PRV_PORT_OFFSET) || + (port_number == BSP_FEATURE_IOPORT_GROUP2_PORT >> IOPORT_PRV_PORT_OFFSET), + FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Get port and pin number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin); + uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin); + + /* Get register address */ + R_GPIO_Type * p_ioport_regs = R_GPIO; + + /* Get port group number for the specified port */ + if (BSP_FEATURE_IOPORT_GROUP1_PORT == port_num) + { + portgroup = 0U; + } + else if (BSP_FEATURE_IOPORT_GROUP2_PORT == port_num) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + /* Read current value of buffer value from ELC_PDBF register for the specified port group */ + portvalue = p_ioport_regs->PDBF[portgroup].ELC_PDBF; + mask = (uint8_t) (1U << pin_num); + + if ((portvalue & mask) == mask) + { + *p_pin_event = BSP_IO_LEVEL_HIGH; + } + else + { + *p_pin_event = BSP_IO_LEVEL_LOW; + } + return FSP_SUCCESS; +#endif +} + +/*******************************************************************************************************************//** + * This function writes the set and reset event output data for a port. Implements + * @ref ioport_api_t::portEventOutputWrite. + * + * Using the event system enables a port state to be stored by this function in advance of being output on the port. + * The output to the port will occur when the ELC event occurs. + * + * The input value will be written to the specified port when an ELC event configured for that port occurs. + * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7, + * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port. + * + * @retval FSP_SUCCESS Port event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_UNSUPPORTED The function is not supported on the device which doesn't support ELC. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value) +{ +#if !(BSP_FEATURE_BSP_HAS_ELC) + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(event_data); + FSP_PARAMETER_NOT_USED(mask_value); + + return FSP_ERR_UNSUPPORTED; +#else + uint8_t portgroup = 0U; + ioport_size_t temp_value; + + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((port == BSP_FEATURE_IOPORT_GROUP1_PORT) || (port == BSP_FEATURE_IOPORT_GROUP2_PORT), + FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Get register address */ + R_GPIO_Type * p_ioport_regs = R_GPIO; + + /* Get port group number for the specified port */ + if (BSP_FEATURE_IOPORT_GROUP1_PORT == port) + { + portgroup = 0U; + } + else if (BSP_FEATURE_IOPORT_GROUP2_PORT == port) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + temp_value = p_ioport_regs->PDBF[portgroup].ELC_PDBF; + temp_value &= (ioport_size_t) (~mask_value); + + p_ioport_regs->PDBF[portgroup].ELC_PDBF = (uint8_t) (temp_value | event_data); + + return FSP_SUCCESS; +#endif +} + +/*******************************************************************************************************************//** + * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite. + * + * Using the event system enables a pin state to be stored by this function in advance of being output on the pin. + * The output to the pin will occur when the ELC event occurs. + * + * @retval FSP_SUCCESS Pin event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_UNSUPPORTED The function is not supported on the device which doesn't support ELC. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value) +{ +#if !(BSP_FEATURE_BSP_HAS_ELC) + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(pin); + FSP_PARAMETER_NOT_USED(pin_value); + + return FSP_ERR_UNSUPPORTED; +#else + uint8_t singleport = 0U; + uint8_t cnt; + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number == BSP_FEATURE_IOPORT_GROUP1_PORT >> IOPORT_PRV_PORT_OFFSET) || + (port_number == BSP_FEATURE_IOPORT_GROUP2_PORT >> IOPORT_PRV_PORT_OFFSET), + FSP_ERR_INVALID_ARGUMENT); + #endif + + const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend; + + /* Get register address */ + R_GPIO_Type * p_ioport_regs = R_GPIO; + + for (cnt = 0; cnt < BSP_FEATURE_IOPORT_SINGLE_PORT_NUM; cnt++) + { + if ((bsp_io_port_pin_t) elc_cfg->p_single_port_cfg[cnt].port_num == pin) + { + singleport = cnt; + } + } + + if (BSP_IO_LEVEL_HIGH == pin_value) + { + p_ioport_regs->ELC_PEL[singleport] |= (uint8_t) IOPORT_PRV_ELC_PEL_PSM_HIGH; + } + else + { + p_ioport_regs->ELC_PEL[singleport] &= (uint8_t) (~IOPORT_PRV_ELC_PEL_PSM_HIGH); + } + return FSP_SUCCESS; +#endif +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IOPORT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures pins. + * + * @param[in] p_cfg Pin configuration data + **********************************************************************************************************************/ +static void r_ioport_pins_config (const ioport_cfg_t * p_cfg) +{ + uint16_t pin_count; + ioport_cfg_t * p_pin_data; + + p_pin_data = (ioport_cfg_t *) p_cfg; + + R_BSP_PinAccessEnable(); // Protect PWPR from re-entrancy + + for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++) + { + r_ioport_pfs_write(p_pin_data->p_pin_cfg_data[pin_count].pin, p_pin_data->p_pin_cfg_data[pin_count].pin_cfg); + } + + R_BSP_PinAccessDisable(); +} + +/********************************************************************************************************************** + * End of function r_ioport_pins_config + *********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Writes to the specified pin's PFS register + * + * @param[in] pin Pin to write PFS data for + * @param[in] value Value to be written to the PFS register + * + **********************************************************************************************************************/ +static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value) +{ + if (0 != (pin & IOPORT_PRV_PORT_EXISTS_MASK)) + { + r_ioport_dedicated_port_cfg(pin, value); + } + else if ((value & IOPORT_PRV_PERIPHERAL_FUNCTION) > 0) + { + r_ioport_peri_mode_pin_config(pin, value); + } + else + { + r_ioport_port_mode_pin_config(pin, value); + } +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's each registers for dedicated pin's + * + * @param[in] pin Pin to write pin function setting data for + * @param[in] value Value to be written to the each registers + * + **********************************************************************************************************************/ +static void r_ioport_dedicated_port_cfg (bsp_io_port_pin_t pin, uint32_t value) +{ + uint8_t u_port; + uint8_t u_pin; + uint32_t bitpos_align; + uint8_t adr_offset; + volatile uint32_t * p_ien; + volatile uint32_t * p_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + volatile uint32_t * p_sr; +#endif + volatile uint32_t * p_filonoff; + volatile uint32_t * p_filnum; + volatile uint32_t * p_filclksel; + uint32_t mask_ien; + uint32_t mask_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + uint32_t mask_sr; +#endif + uint32_t mask_filonoff; + uint32_t mask_filnum; + uint32_t mask_filclksel; + uint32_t value_ien; + uint32_t value_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + uint32_t value_sr; +#endif + uint32_t value_filonoff; + uint32_t value_filnum; + uint32_t value_filclksel; + + r_ioport_make_port_pin_num(pin, &u_port, &u_pin); + bitpos_align = (u_pin & IOPORT_PRV_2BIT_MASK) * IOPORT_PRV_POS_ALIGN_8BIT; + + adr_offset = (uint8_t) (((u_port - BSP_FEATURE_IOPORT_SP_REG_BASE_NUM) * 2) + (u_pin >> 2)); + + p_ien = IOPORT_PRV_IEN_REG_BASE_SET(BSP_FEATURE_IOPORT_IEN_SP_REG_BASE_NUM); + p_iolh = IOPORT_PRV_IOLH_REG_BASE_SET(BSP_FEATURE_IOPORT_IOLH_SP_REG_BASE_NUM); +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + p_sr = IOPORT_PRV_SR_REG_BASE_SET(BSP_FEATURE_IOPORT_SR_SP_REG_BASE_NUM); +#endif + p_filonoff = IOPORT_PRV_FILONOFF_REG_BASE_SET(BSP_FEATURE_IOPORT_FIL_SP_REG_BASE_NUM); + p_filnum = IOPORT_PRV_FILNUM_REG_BASE_SET(BSP_FEATURE_IOPORT_FIL_SP_REG_BASE_NUM); + p_filclksel = IOPORT_PRV_FILCLKSEL_REG_BASE_SET(BSP_FEATURE_IOPORT_FIL_SP_REG_BASE_NUM); + + mask_ien = IOPORT_PRV_BITFIELD_1BIT << bitpos_align; + mask_iolh = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + mask_sr = IOPORT_PRV_BITFIELD_1BIT << bitpos_align; +#endif + mask_filonoff = IOPORT_PRV_BITFIELD_1BIT << bitpos_align; + mask_filnum = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; + mask_filclksel = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; + + value_ien = (value >> IOPORT_PRV_IEN_OFFSET) & IOPORT_PRV_BITFIELD_1BIT; + value_iolh = (value >> IOPORT_PRV_IOLH_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + value_sr = (value >> IOPORT_PRV_SR_OFFSET) & IOPORT_PRV_BITFIELD_1BIT; +#endif + value_filonoff = (value >> IOPORT_PRV_FILONOFF_OFFSET) & IOPORT_PRV_BITFIELD_1BIT; + value_filnum = (value >> IOPORT_PRV_FILNUM_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; + value_filclksel = (value >> IOPORT_PRV_FILCLKSEL_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; + + /* Configure of IEN Register, IOLH Register, SR Register and PUPD Register */ + r_ioport_regwrite_32(&p_ien[adr_offset], value_ien, bitpos_align, mask_ien); + r_ioport_regwrite_32(&p_iolh[adr_offset], value_iolh, bitpos_align, mask_iolh); +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + r_ioport_regwrite_32(&p_sr[adr_offset], value_sr, bitpos_align, mask_sr); +#endif + + /* When use NMI pin, configure FILONOFF, FILNUM, FILCLKSEL register. */ + if (((BSP_IO_NMI & IOPORT_PRV_PORT_BITS) >> IOPORT_PRV_PORT_OFFSET) == u_port) + { + r_ioport_regwrite_32(p_filonoff, value_filonoff, bitpos_align, mask_filonoff); + r_ioport_regwrite_32(p_filnum, value_filnum, bitpos_align, mask_filnum); + r_ioport_regwrite_32(p_filclksel, value_filclksel, bitpos_align, mask_filclksel); + } +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's each registers for peripheral pin's + * + * @param[in] pin Pin to write pin function setting data for + * @param[in] value Value to be written to the each registers + * + **********************************************************************************************************************/ +static void r_ioport_peri_mode_pin_config (bsp_io_port_pin_t pin, uint32_t value) +{ + uint8_t u_port; + uint8_t u_pin; + uint32_t bitpos_align; + uint8_t adr_offset; + volatile uint8_t * p_pmc; + volatile uint32_t * p_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + volatile uint32_t * p_sr; +#endif + volatile uint32_t * p_pupd; + volatile uint32_t * p_filonoff; + volatile uint32_t * p_filnum; + volatile uint32_t * p_filclksel; + volatile uint32_t * p_pfc; + uint8_t mask_pmc; + uint32_t mask_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + uint32_t mask_sr; +#endif + uint32_t mask_pupd; + uint32_t mask_filonoff; + uint32_t mask_filnum; + uint32_t mask_filclksel; + uint32_t mask_pfc; + uint8_t value_pmc; + uint32_t value_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + uint32_t value_sr; +#endif + uint32_t value_pupd; + uint32_t value_filonoff; + uint32_t value_filnum; + uint32_t value_filclksel; + uint32_t value_pfc; + + r_ioport_make_port_pin_num(pin, &u_port, &u_pin); + bitpos_align = (u_pin & IOPORT_PRV_2BIT_MASK) * IOPORT_PRV_POS_ALIGN_8BIT; + + adr_offset = (uint8_t) ((u_port * 2) + (u_pin >> 2)); + + p_pmc = IOPORT_PRV_PMC_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_iolh = IOPORT_PRV_IOLH_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + p_sr = IOPORT_PRV_SR_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); +#endif + p_pupd = IOPORT_PRV_PUPD_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_filonoff = IOPORT_PRV_FILONOFF_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_filnum = IOPORT_PRV_FILNUM_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_filclksel = IOPORT_PRV_FILCLKSEL_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_pfc = IOPORT_PRV_PFC_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + + mask_pmc = (uint8_t) (IOPORT_PRV_BITFIELD_1BIT << u_pin); + mask_iolh = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + mask_sr = IOPORT_PRV_BITFIELD_1BIT << bitpos_align; +#endif + mask_pupd = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; + mask_filonoff = IOPORT_PRV_BITFIELD_1BIT << bitpos_align; + mask_filnum = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; + mask_filclksel = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; + mask_pfc = IOPORT_PRV_BITFIELD_3BIT << (u_pin * IOPORT_PRV_POS_ALIGN_4BIT); + + value_pmc = (uint8_t) ((value >> IOPORT_PRV_PMC_OFFSET) & IOPORT_PRV_BITFIELD_1BIT); + value_iolh = (value >> IOPORT_PRV_IOLH_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + value_sr = (value >> IOPORT_PRV_SR_OFFSET) & IOPORT_PRV_BITFIELD_1BIT; +#endif + value_pupd = (value >> IOPORT_PRV_PUPD_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; + value_filonoff = (value >> IOPORT_PRV_FILONOFF_OFFSET) & IOPORT_PRV_BITFIELD_1BIT; + value_filnum = (value >> IOPORT_PRV_FILNUM_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; + value_filclksel = (value >> IOPORT_PRV_FILCLKSEL_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; + value_pfc = ((value >> IOPORT_PRV_PFC_OFFSET) & IOPORT_PRV_BITFIELD_3BIT); + + r_ioport_regwrite_8(&p_pmc[u_port], value_pmc, u_pin, mask_pmc); + + /* Configure of IOLH Register, SR Register, PUPD Register */ + r_ioport_regwrite_32(&p_iolh[adr_offset], value_iolh, bitpos_align, mask_iolh); +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + r_ioport_regwrite_32(&p_sr[adr_offset], value_sr, bitpos_align, mask_sr); +#endif + r_ioport_regwrite_32(&p_pupd[adr_offset], value_pupd, bitpos_align, mask_pupd); + + r_ioport_regwrite_32(&p_filonoff[adr_offset], value_filonoff, bitpos_align, mask_filonoff); + r_ioport_regwrite_32(&p_filnum[adr_offset], value_filnum, bitpos_align, mask_filnum); + r_ioport_regwrite_32(&p_filclksel[adr_offset], value_filclksel, bitpos_align, mask_filclksel); + + r_ioport_regwrite_32(&p_pfc[u_port], value_pfc, (uint32_t) (u_pin * IOPORT_PRV_POS_ALIGN_4BIT), mask_pfc); +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's each registers for general purpose pin's + * + * @param[in] pin Pin to write pin function setting data for + * @param[in] value Value to be written to the each registers + * + **********************************************************************************************************************/ +static void r_ioport_port_mode_pin_config (bsp_io_port_pin_t pin, uint32_t value) +{ + uint8_t u_port; + uint8_t u_pin; + uint32_t bitpos_align; + uint8_t adr_offset; + volatile uint8_t * p_pmc; + volatile uint32_t * p_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + volatile uint32_t * p_sr; +#endif + volatile uint32_t * p_pupd; + volatile uint32_t * p_isel; + volatile uint32_t * p_filonoff; + volatile uint32_t * p_filnum; + volatile uint32_t * p_filclksel; + volatile uint16_t * p_pm; + volatile uint8_t * p_p; + uint8_t mask_pmc; + uint32_t mask_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + uint32_t mask_sr; +#endif + uint32_t mask_pupd; + uint32_t mask_isel; + uint32_t mask_filonoff; + uint32_t mask_filnum; + uint32_t mask_filclksel; + uint16_t mask_pm; + uint8_t mask_p; + uint8_t value_pmc; + uint32_t value_iolh; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + uint32_t value_sr; +#endif + uint32_t value_pupd; + uint32_t value_isel; + uint32_t value_filonoff; + uint32_t value_filnum; + uint32_t value_filclksel; + uint16_t value_pm; + uint8_t value_p; + + r_ioport_make_port_pin_num(pin, &u_port, &u_pin); + bitpos_align = (u_pin & IOPORT_PRV_2BIT_MASK) * IOPORT_PRV_POS_ALIGN_8BIT; + + adr_offset = (uint8_t) ((u_port * 2) + (u_pin >> 2)); + + p_pmc = IOPORT_PRV_PMC_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_iolh = IOPORT_PRV_IOLH_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + p_sr = IOPORT_PRV_SR_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); +#endif + p_pupd = IOPORT_PRV_PUPD_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_isel = IOPORT_PRV_ISEL_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_filonoff = IOPORT_PRV_FILONOFF_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_filnum = IOPORT_PRV_FILNUM_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_filclksel = IOPORT_PRV_FILCLKSEL_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_pm = IOPORT_PRV_PM_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + p_p = IOPORT_PRV_P_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM); + + mask_pmc = (uint8_t) (IOPORT_PRV_BITFIELD_1BIT << u_pin); + mask_pm = (uint16_t) (IOPORT_PRV_BITFIELD_2BIT << (u_pin * IOPORT_PRV_POS_ALIGN_2BIT)); + mask_iolh = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + mask_sr = IOPORT_PRV_BITFIELD_1BIT << bitpos_align; +#endif + mask_pupd = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; + mask_isel = IOPORT_PRV_BITFIELD_1BIT << bitpos_align; + mask_filonoff = IOPORT_PRV_BITFIELD_1BIT << bitpos_align; + mask_filnum = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; + mask_filclksel = IOPORT_PRV_BITFIELD_2BIT << bitpos_align; + mask_p = (uint8_t) (IOPORT_PRV_BITFIELD_1BIT << u_pin); + + value_pmc = (uint8_t) ((value >> IOPORT_PRV_PMC_OFFSET) & IOPORT_PRV_BITFIELD_1BIT); + value_iolh = (value >> IOPORT_PRV_IOLH_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + value_sr = (value >> IOPORT_PRV_SR_OFFSET) & IOPORT_PRV_BITFIELD_1BIT; +#endif + value_pupd = (value >> IOPORT_PRV_PUPD_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; + value_isel = (value >> IOPORT_PRV_ISEL_OFFSET) & IOPORT_PRV_BITFIELD_1BIT; + value_filonoff = (value >> IOPORT_PRV_FILONOFF_OFFSET) & IOPORT_PRV_BITFIELD_1BIT; + value_filnum = (value >> IOPORT_PRV_FILNUM_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; + value_filclksel = (value >> IOPORT_PRV_FILCLKSEL_OFFSET) & IOPORT_PRV_BITFIELD_2BIT; + value_pm = (uint16_t) ((value >> IOPORT_PRV_PM_OFFSET) & IOPORT_PRV_BITFIELD_2BIT); + value_p = (uint8_t) ((value >> IOPORT_PRV_P_OFFSET) & IOPORT_PRV_BITFIELD_1BIT); + + /* Write configuration */ + r_ioport_regwrite_8(&p_pmc[u_port], value_pmc, u_pin, mask_pmc); + + r_ioport_regwrite_32(&p_iolh[adr_offset], value_iolh, bitpos_align, mask_iolh); +#if (BSP_FEATURE_IOPORT_SUPPORT_SR_REG) + r_ioport_regwrite_32(&p_sr[adr_offset], value_sr, bitpos_align, mask_sr); +#endif + r_ioport_regwrite_32(&p_pupd[adr_offset], value_pupd, bitpos_align, mask_pupd); + + /* When setting the interrupt input using the GPIO input pin, set the ISEL register to "1". */ + r_ioport_regwrite_32(&p_isel[adr_offset], value_isel, bitpos_align, mask_isel); + + r_ioport_regwrite_32(&p_filonoff[adr_offset], value_filonoff, bitpos_align, mask_filonoff); + r_ioport_regwrite_32(&p_filnum[adr_offset], value_filnum, bitpos_align, mask_filnum); + r_ioport_regwrite_32(&p_filclksel[adr_offset], value_filclksel, bitpos_align, mask_filclksel); + + r_ioport_regwrite_16(&p_pm[u_port], value_pm, (uint16_t) (u_pin * IOPORT_PRV_POS_ALIGN_2BIT), mask_pm); + r_ioport_regwrite_8(&p_p[u_port], value_p, u_pin, mask_p); +} + +/*******************************************************************************************************************//** + * Make pin and port number + * + * @param[in] pin Pin and port number + * @param[out] p_port_number Port number + * @param[out] p_pin_number Pin number + * + **********************************************************************************************************************/ +static void r_ioport_make_port_pin_num (bsp_io_port_pin_t pin, uint8_t * p_port_number, uint8_t * p_pin_number) +{ + *p_port_number = (uint8_t) ((pin & IOPORT_PRV_PORT_BITS) >> IOPORT_PRV_PORT_OFFSET); + *p_pin_number = (uint8_t) (pin & IOPORT_PRV_PIN_BITS); +} + +/********************************************************************************************************************** + * IO register 8-bit write + * + * @param[in] ioreg IO register for writing + * Use register definition name of the iodefine.h + * @param[in] write_value Write value for the IO register + * @param[in] shift The number of left shifts to the target bit + * @param[in] mask Mask value for the IO register (Target bit : "1") + * + *********************************************************************************************************************/ +static void r_ioport_regwrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask) +{ + uint8_t reg_value; + + if ((uint8_t) IOPORT_PRV_NONMASK_ACCESS != mask) + { + /* Read from register */ + reg_value = *ioreg; + + /* Modify value */ + reg_value = (uint8_t) ((reg_value & (~mask)) | (write_value << shift)); + } + else + { + reg_value = write_value; + } + + /* Write to register */ + *ioreg = reg_value; +} + +/********************************************************************************************************************** + * IO register 16-bit write + * + * @param[in] ioreg IO register for writing + * Use register definition name of the iodefine.h + * @param[in] write_value Write value for the IO register + * @param[in] shift The number of left shifts to the target bit + * @param[in] mask Mask value for the IO register (Target bit : "1") + * + *********************************************************************************************************************/ +static void r_ioport_regwrite_16 (volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask) +{ + uint16_t reg_value; + + if ((uint16_t) IOPORT_PRV_NONMASK_ACCESS != mask) + { + /* Read from register */ + reg_value = *ioreg; + + /* Modify value */ + reg_value = (uint16_t) ((reg_value & (~mask)) | (write_value << shift)); + } + else + { + reg_value = write_value; + } + + /* Write to register */ + *ioreg = reg_value; +} + +/********************************************************************************************************************** + * IO register 32-bit write + * + * @param[in] ioreg IO register for writing + * Use register definition name of the iodefine.h + * @param[in] write_value Write value for the IO register + * @param[in] shift The number of left shifts to the target bit + * @param[in] mask Mask value for the IO register (Target bit : "1") + * + *********************************************************************************************************************/ +static void r_ioport_regwrite_32 (volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask) +{ + uint32_t reg_value; + + if (IOPORT_PRV_NONMASK_ACCESS != mask) + { + /* Read from register */ + reg_value = *ioreg; + + /* Modify value */ + reg_value = (uint32_t) ((reg_value & (~mask)) | (write_value << shift)); + } + else + { + reg_value = write_value; + } + + /* Write to register */ + *ioreg = reg_value; +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's multiple registers to generate event link function + * + * @param[in] p_extend_cfg_data Value to be written to the multiple registers + * + **********************************************************************************************************************/ +static void r_ioport_event_config (const ioport_extend_cfg_t * p_extend_cfg_data) +{ +#if !(BSP_FEATURE_BSP_HAS_ELC) + FSP_PARAMETER_NOT_USED(p_extend_cfg_data); +#else + uint8_t event_num; + uint8_t temp_value = 0x00; + uint8_t single_enable = 0x00; + uint8_t group_enable = 0x00; + R_GPIO_Type * p_ioport_regs; + ioport_extend_cfg_t * ex_cfg; + + ex_cfg = (ioport_extend_cfg_t *) p_extend_cfg_data; + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + /* Get register address */ + p_ioport_regs = R_GPIO; + + /* Single port configuration */ + for (event_num = 0U; event_num < BSP_FEATURE_IOPORT_SINGLE_PORT_NUM; event_num++) + { + uint8_t port = + (uint8_t) ((ex_cfg->p_single_port_cfg[event_num].port_num & IOPORT_PRV_PORT_BITS) >> + IOPORT_PRV_PORT_OFFSET); + uint8_t pin_num = (uint8_t) ex_cfg->p_single_port_cfg[event_num].port_num & IOPORT_PRV_PIN_BITS; + + temp_value = p_ioport_regs->ELC_PEL[event_num] & IOPORT_PRV_ELC_PEL_MASK; + + /* Port selection */ + if ((BSP_FEATURE_IOPORT_GROUP1_PORT >> IOPORT_PRV_PORT_OFFSET) == port) + { + temp_value |= 1U << R_GPIO_ELC_PEL_PSP_Pos; + } + else if ((BSP_FEATURE_IOPORT_GROUP2_PORT >> IOPORT_PRV_PORT_OFFSET) == port) + { + temp_value |= 1U << (R_GPIO_ELC_PEL_PSP_Pos + 1); + } + else + { + /* Do Nothing */ + } + + temp_value |= pin_num; // Pin number setting + + /* When the pin specified as single input port, Set edge detection */ + /* When the pin specified as single output port, Set output operation */ + if (IOPORT_EVENT_DIRECTION_INPUT == ex_cfg->p_single_port_cfg[event_num].direction) + { + temp_value |= (uint8_t) (ex_cfg->p_single_port_cfg[event_num].edge_detection << R_GPIO_ELC_PEL_PSM_Pos); // Edge detection + + /* Edge detection enable */ + p_ioport_regs->ELC_DPTC |= (uint8_t) (1U << event_num); + } + else + { + temp_value |= (uint8_t) (ex_cfg->p_single_port_cfg[event_num].operation << R_GPIO_ELC_PEL_PSM_Pos); // Output operation + } + + /* Set to ELC port setting register */ + p_ioport_regs->ELC_PEL[event_num] = temp_value; + + /* Single port event link function enable */ + if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->p_single_port_cfg[event_num].event_control) + { + single_enable |= (uint8_t) (1U << event_num); + } + } + + /* Port group configuration */ + for (event_num = 0U; event_num < BSP_FEATURE_IOPORT_PORT_GROUP_NUM; event_num++) + { + /* Pin selection */ + uint8_t group_pin = ex_cfg->p_port_group_input_cfg[event_num].pin_select | + ex_cfg->p_port_group_output_cfg[event_num].pin_select; + p_ioport_regs->ELC_PGR[event_num] = group_pin; + + if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->p_port_group_input_cfg[event_num].event_control) + { + /* Input port group control */ + temp_value = p_ioport_regs->ELC_PGC[event_num] & IOOPRT_PRV_ELC_PGC_MASK; + temp_value |= ex_cfg->p_port_group_input_cfg[event_num].edge_detection; // Edge detection + temp_value |= + (uint8_t) (ex_cfg->p_port_group_input_cfg[event_num].overwrite_control << R_GPIO_ELC_PGC_PGCOVE_Pos); // Overwrite setting + + /* Buffer register initialization */ + p_ioport_regs->PDBF[event_num].ELC_PDBF = ex_cfg->p_port_group_input_cfg[event_num].buffer_init_value; + + /* Input port group event link function enable */ + group_enable |= (uint8_t) (1U << event_num); + } + + /* Output port group operation */ + temp_value |= (uint8_t) (ex_cfg->p_port_group_output_cfg[event_num].operation << R_GPIO_ELC_PGC_PGCO_Pos); + + /* Set to port group control register */ + p_ioport_regs->ELC_PGC[event_num] = temp_value; + } + + /* Set to ELC port event control register */ + p_ioport_regs->PFC_ELC_ELSR2 = + (uint8_t) ((single_enable << R_GPIO_PFC_ELC_ELSR2_PES_Pos) | (group_enable << R_GPIO_PFC_ELC_ELSR2_PEG_Pos)); +#endif +} diff --git a/drivers/rz/fsp/src/rzg/r_scif_uart/r_scif_uart.c b/drivers/rz/fsp/src/rzg/r_scif_uart/r_scif_uart.c new file mode 100644 index 00000000..20b50113 --- /dev/null +++ b/drivers/rz/fsp/src/rzg/r_scif_uart/r_scif_uart.c @@ -0,0 +1,2036 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_scif_uart.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef SCIF_UART_CFG_RX_ENABLE + #define SCIF_UART_CFG_RX_ENABLE 1 +#endif +#ifndef SCIF_UART_CFG_TX_ENABLE + #define SCIF_UART_CFG_TX_ENABLE 1 +#endif + +/** Number of divisors in the data table used for baud rate calculation. */ +#define SCIF_UART_NUM_DIVISORS_ASYNC (9U) + +/** Valid range of values for the modulation duty register is 128 - 256 (256 = modulation disabled). */ +#define SCIF_UART_MDDR_MIN (128U) +#define SCIF_UART_MDDR_MAX (256U) + +/** The bit rate register is 8-bits, so the maximum value is 255. */ +#define SCIF_UART_BRR_MAX (255U) + +/** No limit to the number of bytes to read or write. */ +#define SCIF_UART_MAX_READ_WRITE (0xFFFFFFFFU) + +/** "SCFU" in ASCIFAI. Used to determine if the control block is open. */ +#define SCIF_UART_OPEN (0x53434655U) + +#define SCIF_UART_BRR_DEFAULT_VALUE (0xFFU) + +#define SCIF_UART_DMAC_RX_TRIGGER_LEVEL (1U) + +#define SCIF_UART_DMAC_MAX_TRANSFER (0xFFFFFFFFU) + +#define SCIF_REG_SIZE (R_SCIFA1_BASE - R_SCIFA0_BASE) + +#define SCI_UART_INVALID_16BIT_PARAM (0xFFFFU) + +/*********************************************************************************************************************** + * Private constants + **********************************************************************************************************************/ +static const uint32_t SCIF_UART_TX_FIFO_STAGES = 16; +static const int32_t SCIF_UART_100_PERCENT_X_1000 = 100000; +static const int32_t SCIF_UART_MDDR_DIVISOR = 256; + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) +static const uint32_t SCIF_UART_MAX_BAUD_RATE_ERROR_X_1000 = 15000; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_baud_setting_const_t +{ + uint8_t bgdm : 1; /**< BGDM value to get divisor */ + uint8_t abcs : 1; /**< ABCS value to get divisor */ + uint8_t cks : 2; /**< CKS value to get divisor (CKS = N) */ +} baud_setting_const_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * scif_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile scif_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_scif_negate_de_pin(scif_uart_instance_ctrl_t const * const p_ctrl); + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_scif_read_write_param_check(scif_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + +#endif + +static void r_scif_uart_config_set(scif_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +static void r_scif_uart_baud_set(R_SCIFA0_Type * p_scif_reg, scif_baud_setting_t const * const p_baud_setting); +static void r_scif_uart_call_callback(scif_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); + +static void r_scif_uart_fifo_cfg(scif_uart_instance_ctrl_t * const p_ctrl); + +static void r_scif_irq_cfg(scif_uart_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const p_irq); + +static void r_scif_irqs_cfg(scif_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +#if (SCIF_UART_CFG_RX_ENABLE) +static void scif_uart_receive_sub(scif_uart_instance_ctrl_t * const p_ctrl); +void scif_uart_rxi_isr(void); + +void scif_uart_eri_isr(void); +void scif_uart_bri_isr(void); + +#endif + +#if (SCIF_UART_CFG_TX_ENABLE) +void scif_uart_txi_isr(void); + +#endif + +#if (SCIF_UART_CFG_TX_ENABLE || SCIF_UART_CFG_RX_ENABLE) +void scif_uart_tei_isr(void); + +#endif + +#if SCIF_UART_CFG_DMAC_ENABLE +static fsp_err_t r_scif_uart_transfer_configure(transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t address); + +static fsp_err_t r_scif_uart_transfer_open(scif_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +static void r_scif_uart_transfer_close(scif_uart_instance_ctrl_t * p_ctrl); + +void scif_uart_tx_dmac_callback(scif_uart_instance_ctrl_t * p_ctrl); +void scif_uart_rx_dmac_callback(scif_uart_instance_ctrl_t * p_ctrl); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** Name of module used by error logger macro */ +#if BSP_CFG_ERROR_LOG != 0 +static const char g_module_name[] = "scif_uart"; +#endif + +/** Baud rate divisor information (UART mode) */ +static const baud_setting_const_t g_async_baud[SCIF_UART_NUM_DIVISORS_ASYNC] = +{ + {1U, 1U, 0U}, /* BGDM, ABCS, n */ + {1U, 0U, 0U}, + {0U, 0U, 0U}, + {1U, 0U, 1U}, + {0U, 0U, 1U}, + {1U, 0U, 2U}, + {0U, 0U, 2U}, + {1U, 0U, 3U}, + {0U, 0U, 3U} +}; + +static const uint16_t g_div_coefficient[SCIF_UART_NUM_DIVISORS_ASYNC] = +{ + 8U, + 16U, + 32U, + 64U, + 128U, + 256U, + 512U, + 1024U, + 2048U, +}; + +/** UART on SCIF HAL API mapping for UART interface */ +const uart_api_t g_uart_on_scif = +{ + .open = R_SCIF_UART_Open, + .close = R_SCIF_UART_Close, + .write = R_SCIF_UART_Write, + .read = R_SCIF_UART_Read, + .infoGet = R_SCIF_UART_InfoGet, + .baudSet = R_SCIF_UART_BaudSet, + .communicationAbort = R_SCIF_UART_Abort, + .callbackSet = R_SCIF_UART_CallbackSet, + .readStop = R_SCIF_UART_ReadStop, +}; + +/*******************************************************************************************************************//** + * @addtogroup SCIF_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is + * enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MPU. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_ARGUMENT Setting for RS485 DE Control pin is invalid + * + * @return See @ref RENESAS_ERROR_CODES + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg) +{ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(((scif_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting); + FSP_ERROR_RETURN(SCIF_UART_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCIF_CHANNELS & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); + FSP_ASSERT(((scif_uart_extended_cfg_t *) p_cfg->p_extend)->bri_irq >= 0); + #if (SCIF_UART_CFG_FLOW_CONTROL_SUPPORT) + if (((scif_uart_extended_cfg_t *) p_cfg->p_extend)->uart_mode != SCIF_UART_MODE_RS232) + { + FSP_ERROR_RETURN( + ((scif_uart_extended_cfg_t *) p_cfg->p_extend)->rs485_setting.de_control_pin != SCI_UART_INVALID_16BIT_PARAM, + FSP_ERR_INVALID_ARGUMENT); + } + #endif +#endif + +#if defined(BSP_MCU_GROUP_RZG3S) + + /* The difference of base address between channel 4 and 5 is 0x1800. But the difference between other channel is 0x0400 */ + if (5U == p_cfg->channel) + { + p_ctrl->p_reg = ((R_SCIFA0_Type *) (R_SCIFA5_BASE)); + } + else + { + p_ctrl->p_reg = ((R_SCIFA0_Type *) (R_SCIFA0_BASE + (SCIF_REG_SIZE * p_cfg->channel))); + } + +#else + p_ctrl->p_reg = ((R_SCIFA0_Type *) (R_SCIFA0_BASE + (SCIF_REG_SIZE * p_cfg->channel))); +#endif + + p_ctrl->p_cfg = p_cfg; + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Configure the interrupts. */ + r_scif_irqs_cfg(p_ctrl, p_cfg); + +#if SCIF_UART_CFG_DMAC_ENABLE + + /* Configure the transfer interface for transmission and reception if provided. */ + fsp_err_t err = r_scif_uart_transfer_open(p_ctrl, p_cfg); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + scif_uart_extended_cfg_t * p_extend = (scif_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Enable the SCIF channel and reset the registers to their initial state. */ + R_BSP_MODULE_START(FSP_IP_SCIF, p_cfg->channel); + + /* Initialize registers as defined in section "SCIFA Initialization in Asynchronous Mode" in the user's + * manual or the relevant section for the MPU being used. */ + p_ctrl->p_reg->SCR = 0U; + uint32_t fcr = p_ctrl->p_reg->FCR; + fcr |= (R_SCIFA0_FCR_TFRST_Msk | R_SCIFA0_FCR_RFRST_Msk); + p_ctrl->p_reg->FCR = (uint16_t) fcr; + p_ctrl->p_reg->FSR; + p_ctrl->p_reg->FSR = 0; + p_ctrl->p_reg->LSR; + p_ctrl->p_reg->LSR = 0; + + uint32_t scr = 0; + + switch (p_extend->clock) + { + case SCIF_UART_CLOCK_INT: + { + scr = 0 << R_SCIFA0_SCR_CKE_Pos; + break; + } + + case SCIF_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT: + { + scr = 1 << R_SCIFA0_SCR_CKE_Pos; + break; + } + + default: + { + scr = 2 << R_SCIFA0_SCR_CKE_Pos; + } + } + + p_ctrl->p_reg->SCR = (uint16_t) scr; + + /* Set the UART configuration settings provided in ::uart_cfg_t and ::scif_uart_extended_cfg_t. */ + r_scif_uart_config_set(p_ctrl, p_cfg); + + /* Set the default level of the TX pin to 1. */ + p_ctrl->sptr = R_SCIFA0_SPTR_SPB2IO_Msk | R_SCIFA0_SPTR_SPB2DT_Msk; + + p_ctrl->p_tx_src = NULL; + p_ctrl->tx_src_bytes = 0U; + p_ctrl->p_rx_dest = NULL; + p_ctrl->rx_dest_bytes = 0; + +#if (SCIF_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, enable reception. */ + /* NOTE: Transmitter and its interrupt are enabled in R_SCIF_UART_Write(). */ + scr |= R_SCIFA0_SCR_RE_Msk; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->eri_irq); + R_BSP_IrqEnable(p_extend->bri_irq); + + scr |= R_SCIFA0_SCR_RIE_Msk; +#endif + +#if (SCIF_UART_CFG_TX_ENABLE) + + /* To Acceptable transfer interrupts */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->tei_irq); + scr |= R_SCIFA0_SCR_TE_Msk; +#endif + p_ctrl->p_reg->SCR = (uint16_t) scr; + + /* Automatic RTS/CTS control */ + if (p_extend->flow_control != SCIF_UART_FLOW_CONTROL_NONE) + { + /* Controlled by IP */ + p_ctrl->p_reg->FCR_b.MCE = 1; + } + else + { + /* Always RTS */ + p_ctrl->sptr |= (R_SCIFA0_SPTR_RTS2IO_Msk | R_SCIFA0_SPTR_RTS2DT_Msk); + p_ctrl->p_reg->FCR_b.MCE = 0; + } + +#if SCIF_UART_CFG_FLOW_CONTROL_SUPPORT + if ((p_extend->rs485_setting.de_control_pin != SCIF_UART_INVALID_16BIT_PARAM) && + (p_extend->uart_mode != SCIF_UART_MODE_RS232)) + { + if (p_extend->uart_mode == SCIF_UART_MODE_RS485_FD) + { + R_BSP_PinAccessEnable(); + + /* Assert driver enable if RS-485 FullDuplex mode is enabled. */ + bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH == + p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW; + R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level); + + R_BSP_PinAccessDisable(); + } + else + { + /* Negate driver enable if RS-485 HalfDuplex mode is enabled. */ + r_scif_negate_de_pin(p_ctrl); + } + } +#endif + + p_ctrl->p_reg->SPTR = p_ctrl->sptr; + + p_ctrl->open = SCIF_UART_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Removes power. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_Close (uart_ctrl_t * const p_api_ctrl) +{ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCIF_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + /* Disable interrupts, receiver, and transmitter. Disable baud clock output.*/ + p_ctrl->p_reg->SCR = 0U; + +#if (SCIF_UART_CFG_RX_ENABLE) + scif_uart_extended_cfg_t * p_extend = (scif_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* If reception is enabled at build time, disable reception irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + R_BSP_IrqDisable(p_extend->bri_irq); +#endif +#if (SCIF_UART_CFG_TX_ENABLE) + + /* If transmission is enabled at build time, disable transmission irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); +#endif + +#if SCIF_UART_CFG_DMAC_ENABLE + + /* Close the lower level transfer instances. */ + r_scif_uart_transfer_close(p_ctrl); +#endif + + /* Remove power to the channel. */ + R_BSP_MODULE_STOP(FSP_IP_SCIF, p_ctrl->p_cfg->channel); + + /* Negate driver enable if RS-485 mode is enabled. */ + r_scif_negate_de_pin(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @retval FSP_ERR_UNSUPPORTED SCIF_UART_CFG_RX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ +#if (SCIF_UART_CFG_RX_ENABLE) + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + + #if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_scif_read_write_param_check(p_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->rx_dest_bytes, FSP_ERR_IN_USE); + #endif + + #if SCIF_UART_CFG_DMAC_ENABLE + + /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + #if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(bytes <= SCIF_UART_DMAC_MAX_TRANSFER); + #endif + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = (void *) p_dest; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = bytes; + + err = + p_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_ctrl->rx_dest_bytes = 0; + } + #endif + + /* Save the destination address and size for use in rxi_isr. */ + p_ctrl->p_rx_dest = p_dest; + p_ctrl->rx_dest_bytes = bytes; + + return err; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UART transmission is in progress + * @retval FSP_ERR_UNSUPPORTED SCIF_UART_CFG_TX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ +#if (SCIF_UART_CFG_TX_ENABLE) + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; + + #if SCIF_UART_CFG_PARAM_CHECKING_ENABLE || SCIF_UART_CFG_DMAC_ENABLE + fsp_err_t err = FSP_SUCCESS; + #endif + + #if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_scif_read_write_param_check(p_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE); + #endif + + /* Transmit interrupts must be disabled to start with. */ + p_ctrl->p_reg->SCR_b.TIE = 0; + p_ctrl->p_reg->SCR_b.TEIE = 0; + + p_ctrl->tx_src_bytes = bytes; + p_ctrl->p_tx_src = p_src; + + #if SCIF_UART_CFG_DMAC_ENABLE + + /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested + * data. */ + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && p_ctrl->tx_src_bytes) + { + uint32_t num_transfer = p_ctrl->tx_src_bytes; + p_ctrl->tx_src_bytes = 0; + #if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(num_transfer <= SCIF_UART_DMAC_MAX_TRANSFER); + #endif + + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = (void const *) (p_ctrl->p_tx_src); + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = num_transfer; + + err = p_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + #if (SCIF_UART_CFG_FLOW_CONTROL_SUPPORT) + scif_uart_extended_cfg_t * p_extend = (scif_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* If RS-485 is enabled, then assert the driver enable pin at the start of a write transfer. */ + if (p_extend->uart_mode == SCIF_UART_MODE_RS485_HD) + { + R_BSP_PinAccessEnable(); + + bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH == + p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW; + R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level); + + R_BSP_PinAccessDisable(); + } + #endif + + /* Trigger a TXI interrupt */ + p_ctrl->p_reg->SCR_b.TIE = 1; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void const * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCIF_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCIF_UART_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + uart_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(uart_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a scif_baud_setting_t + * structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) +{ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCIF_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify that the On-Chip baud rate generator is currently selected. */ + FSP_ASSERT((p_ctrl->p_reg->SCR_b.CKE & 0x2) == 0U); +#endif + + /* Disables transmitter and receiver. This terminates any in-progress transmission. */ + uint32_t scr = p_ctrl->p_reg->SCR; + scr &= (~( + R_SCIFA0_SCR_TE_Msk | + R_SCIFA0_SCR_TIE_Msk | + R_SCIFA0_SCR_TEIE_Msk | + R_SCIFA0_SCR_RE_Msk | + R_SCIFA0_SCR_RIE_Msk)); + p_ctrl->p_reg->SCR = (uint16_t) scr; + p_ctrl->p_tx_src = NULL; + + /* Apply new baud rate register settings. */ + r_scif_uart_baud_set(p_ctrl->p_reg, p_baud_setting); + +#if (SCIF_UART_CFG_RX_ENABLE) + + /* Enable receive. */ + scr |= (R_SCIFA0_SCR_RE_Msk | R_SCIFA0_SCR_RIE_Msk); +#endif +#if (SCIF_UART_CFG_TX_ENABLE) + + /* Enable transmit. */ + scr |= R_SCIFA0_SCR_TE_Msk; +#endif + p_ctrl->p_reg->SCR = (uint16_t) scr; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info) +{ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_info); + FSP_ERROR_RETURN(SCIF_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + p_info->read_bytes_max = SCIF_UART_MAX_READ_WRITE; + p_info->write_bytes_max = SCIF_UART_MAX_READ_WRITE; + +#if (SCIF_UART_CFG_RX_ENABLE) + + /* Store number of bytes that can be read at a time. */ + #if SCIF_UART_CFG_DMAC_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_info->write_bytes_max = SCIF_UART_DMAC_MAX_TRANSFER; + } + #endif +#endif + +#if (SCIF_UART_CFG_TX_ENABLE) + + /* Store number of bytes that can be written at a time. */ + #if SCIF_UART_CFG_DMAC_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_info->read_bytes_max = SCIF_UART_DMAC_MAX_TRANSFER; + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) +{ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCIF_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCIF_UART_CFG_TX_ENABLE) + if (UART_DIR_TX & communication_to_abort) + { + err = FSP_SUCCESS; + uint32_t scr = p_ctrl->p_reg->SCR; + scr &= (~(R_SCIFA0_SCR_TIE_Msk | R_SCIFA0_SCR_TEIE_Msk)); + p_ctrl->p_reg->SCR = (uint16_t) scr; + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + err = p_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + + p_ctrl->tx_src_bytes = 0U; + + /* Reset the transmit fifo */ + p_ctrl->p_reg->FCR_b.TFRST = 1U; + + /* Confirm that 1 can be written to TFRST. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR_b.TFRST, 1); + + /* Clear the TFRST bit */ + p_ctrl->p_reg->FCR_b.TFRST = 0U; + + /* Negate driver enable if RS-485 mode is enabled. */ + r_scif_negate_de_pin(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif +#if (SCIF_UART_CFG_RX_ENABLE) + if (UART_DIR_RX & communication_to_abort) + { + err = FSP_SUCCESS; + + p_ctrl->rx_dest_bytes = 0U; + + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + /* Reset the receive fifo */ + p_ctrl->p_reg->FCR_b.RFRST = 1U; + + /* Confirm that 1 can be written to RFRST. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR_b.RFRST, 1); + + /* Clear the RFRST bit */ + p_ctrl->p_reg->FCR_b.RFRST = 0U; + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes) +{ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCIF_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCIF_UART_CFG_RX_ENABLE) + *remaining_bytes = p_ctrl->rx_dest_bytes; + p_ctrl->rx_dest_bytes = 0U; + + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + transfer_properties_t transfer_info; + err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + *remaining_bytes = transfer_info.transfer_length_remaining; + } + + /* Reset the receive fifo */ + p_ctrl->p_reg->FCR_b.RFRST = 1U; + + /* Confirm that 1 can be written to RFRST. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR_b.RFRST, 1); + + /* Clear the RFRST bit */ + p_ctrl->p_reg->FCR_b.RFRST = 0U; +#else + + return FSP_ERR_UNSUPPORTED; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. + * + * @param[in] p_api_ctrl Pointer to the UART control block. + * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. + * @param[in] bitrate_modulation Enable bitrate modulation + * @param[in] baud_rate_error_x_1000 <baud_rate_percent_error> x 1000 required for module to function. + * Absolute max baud_rate_error is 15000 (15%). + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is set successfully + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', source clock frequency could not be read, or error in + * calculated baud rate is larger than 10%. + **********************************************************************************************************************/ +fsp_err_t R_SCIF_UART_BaudCalculate (uart_ctrl_t * const p_api_ctrl, + uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + scif_baud_setting_t * const p_baud_setting) +{ +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_api_ctrl); + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN(SCIF_UART_MAX_BAUD_RATE_ERROR_X_1000 >= baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT); +#endif + scif_uart_instance_ctrl_t const * p_ctrl = (scif_uart_instance_ctrl_t const *) p_api_ctrl; + + p_baud_setting->brr = SCIF_UART_BRR_MAX; + p_baud_setting->semr_baudrate_bits_b.brme = 0U; + p_baud_setting->mddr = SCIF_UART_MDDR_MIN; + + /* Find the best BRR (bit rate register) value. + * In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values. Each set of divisors + * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as + * follows and it must be 255 or less: + * BRR = (PCLK / (div_coefficient * baud)) - 1 + */ + int32_t hit_bit_err = SCIF_UART_100_PERCENT_X_1000; + uint32_t divisor = 0U; + + uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_SCIF_CLOCK); + + for (uint32_t select_16_base_clk_cycles = 0U; + (select_16_base_clk_cycles <= 1U) && (hit_bit_err > ((int32_t) baud_rate_error_x_1000)); + select_16_base_clk_cycles++) + { + for (uint32_t i = 0U; i < SCIF_UART_NUM_DIVISORS_ASYNC; i++) + { + /* if select_16_base_clk_cycles == true: Skip this calculation for divisors that are not acheivable with + * 16 base clk cycles per bit. + * if select_16_base_clk_cycles == false: Skip this calculation for divisors that are only acheivable + * without 16 base clk cycles per bit. + */ + if (((uint8_t) select_16_base_clk_cycles) ^ (g_async_baud[i].abcs)) + { + continue; + } + + if ((p_ctrl->p_cfg->channel == 0) && (g_async_baud[i].cks == 2)) + { + /* Skip if channel eq 0 and cks eq 2 */ + continue; + } + + divisor = (uint32_t) g_div_coefficient[i] * baudrate; + uint32_t temp_brr = freq_hz / divisor; + + if (temp_brr <= (SCIF_UART_BRR_MAX + 1U)) + { + while (temp_brr > 0U) + { + temp_brr -= 1U; + + /* Calculate the bit rate error. The formula is as follows: + * bit rate error[%] = {(PCLK / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * calculates bit rate error[%] to three decimal places + */ + int32_t err_divisor = (int32_t) (divisor * (temp_brr + 1U)); + + /* Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. (temp_brr + 1) can be off by an upper limit of 1 due to rounding from the calculation: + * freq_hz / divisor, or: + * freq_hz / divisor <= (temp_brr + 1) < (freq_hz / divisor) + 1 + * 2. Solving for err_divisor: + * freq_hz <= err_divisor < freq_hz + divisor + * 3. Solving for bit_err: + * 0 >= bit_err >= (freq_hz * 100000 / (freq_hz + divisor)) - 100000 + * 4. freq_hz >= divisor (or temp_brr would be -1 and we would never enter this while loop), so: + * 0 >= bit_err >= 100000 / freq_hz - 100000 + * 5. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the bit_err approaches -100000, so: + * 0 >= bit_err >= -100000 + * 6. bit_err is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ + int32_t bit_err = (int32_t) ((((int64_t) freq_hz * SCIF_UART_100_PERCENT_X_1000) / err_divisor) - + SCIF_UART_100_PERCENT_X_1000); + + uint32_t mddr = SCIF_UART_MDDR_MAX; + if (bitrate_modulation) + { + /* Calculate the MDDR (M) value if bit rate modulation is enabled, + * The formula to calculate MBBR (from the M and N relationship given in the hardware manual) + * is as follows and it must be between 128 and 256. + * MDDR = ((div_coefficient * baud * 256) * (BRR + 1)) / PCLK */ + mddr = (uint32_t) err_divisor / (freq_hz / SCIF_UART_MDDR_MAX); + + /* The maximum value that could result from the calculation above is 256, which is a valid MDDR + * value, so only the lower bound is checked. */ + if (mddr < SCIF_UART_MDDR_MIN) + { + break; + } + + /* Adjust bit rate error for bit rate modulation. The following formula is used: + * bit rate error [%] = ((bit rate error [%, no modulation] + 100) * MDDR / 256) - 100 + */ + bit_err = + (((bit_err + SCIF_UART_100_PERCENT_X_1000) * (int32_t) mddr) / SCIF_UART_MDDR_DIVISOR) - + SCIF_UART_100_PERCENT_X_1000; + } + + /* Take the absolute value of the bit rate error. */ + if (bit_err < 0) + { + bit_err = -bit_err; + } + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if (bit_err < hit_bit_err) + { + p_baud_setting->semr_baudrate_bits_b.bgdm = g_async_baud[i].bgdm; + p_baud_setting->semr_baudrate_bits_b.abcs = g_async_baud[i].abcs; + p_baud_setting->semr_baudrate_bits_b.cks = g_async_baud[i].cks; + p_baud_setting->brr = (uint8_t) temp_brr; + hit_bit_err = bit_err; + if (SCIF_UART_MDDR_MAX <= mddr) + { + p_baud_setting->semr_baudrate_bits_b.brme = 0U; + p_baud_setting->mddr = SCIF_UART_MDDR_MAX - 1; + } + else + { + p_baud_setting->semr_baudrate_bits_b.brme = 1U; + p_baud_setting->mddr = (uint8_t) mddr; + } + + if (!bitrate_modulation) + { + break; + } + } + } + } + } + } + + /* Return an error if the percent error is larger than the maximum percent error allowed for this instance */ + FSP_ERROR_RETURN((hit_bit_err <= (int32_t) baud_rate_error_x_1000), FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCIF_UART) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Negate the DE pin if it is enabled. + * + * @param[in] p_ctrl Pointer to the control block for the channel. + **********************************************************************************************************************/ +static void r_scif_negate_de_pin (scif_uart_instance_ctrl_t const * const p_ctrl) +{ +#if (SCIF_UART_CFG_FLOW_CONTROL_SUPPORT) + scif_uart_extended_cfg_t * p_extend = (scif_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* If RS-485 is enabled, then negate the driver enable pin at the end of a write transfer. */ + if (p_extend->uart_mode == SCIF_UART_MODE_RS485_HD) + { + R_BSP_PinAccessEnable(); + bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH == + p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH; + R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level); + + R_BSP_PinAccessDisable(); + } + +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif +} + +#if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL + **********************************************************************************************************************/ +static fsp_err_t r_scif_read_write_param_check (scif_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(addr); + FSP_ASSERT(0U != bytes); + FSP_ERROR_RETURN(SCIF_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + return FSP_SUCCESS; +} + +#endif + +#if SCIF_UART_CFG_DMAC_ENABLE + +/*******************************************************************************************************************//** + * Subroutine to apply common UART transfer settings. + * + * @param[in] p_cfg Pointer to UART specific configuration structure + * @param[in] p_transfer Pointer to transfer instance to configure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer + **********************************************************************************************************************/ +static fsp_err_t r_scif_uart_transfer_configure (transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t scif_buffer_address) +{ + /* Configure the transfer instance, if enabled. */ + #if (SCIF_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_ctrl); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend); + #endif + + /* Casting for compatibility with 7 or 8 bit mode. */ + *p_transfer_reg = scif_buffer_address; + + fsp_err_t err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures UART related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer or required interrupt not enabled in vector table + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +static fsp_err_t r_scif_uart_transfer_open (scif_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + #if (SCIF_UART_CFG_RX_ENABLE) + + /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_rx) + { + transfer_info_t * p_info = p_cfg->p_transfer_rx->p_cfg->p_info; + + err = r_scif_uart_transfer_configure(p_cfg->p_transfer_rx, + (uint32_t *) &p_info->p_src, + (uint32_t) (uintptr_t) &(p_ctrl->p_reg->FRDR)); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + #if (SCIF_UART_CFG_TX_ENABLE) + + /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_tx) + { + transfer_info_t * p_info = p_cfg->p_transfer_tx->p_cfg->p_info; + + err = r_scif_uart_transfer_configure(p_cfg->p_transfer_tx, + (uint32_t *) &p_info->p_dest, + (uint32_t) (uintptr_t) &(p_ctrl->p_reg->FTDR)); + + #if (SCIF_UART_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_cfg->p_transfer_rx)) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + #endif + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + return err; +} + +/*******************************************************************************************************************//** + * Closes transfer interfaces. + * + * @param[in] p_ctrl Pointer to UART instance control block + **********************************************************************************************************************/ +static void r_scif_uart_transfer_close (scif_uart_instance_ctrl_t * p_ctrl) +{ + #if (SCIF_UART_CFG_RX_ENABLE) + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if (SCIF_UART_CFG_TX_ENABLE) + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Configures UART related registers based on user configurations. + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_scif_uart_config_set (scif_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + /* Configure SMR register (data size, parity and stop bits). */ + /* Note: CKS part is set by r_scif_uart_baud_set function. */ + uint32_t smr = 0; + if (p_cfg->data_bits == UART_DATA_BITS_7) + { + smr |= R_SCIFA0_SMR_CHR_Msk; + } + + if (p_cfg->parity != UART_PARITY_OFF) + { + smr |= R_SCIFA0_SMR_PE_Msk; + } + + if (p_cfg->parity == UART_PARITY_ODD) + { + smr |= R_SCIFA0_SMR_PM_Msk; + } + + if (p_cfg->stop_bits == UART_STOP_BITS_2) + { + smr |= R_SCIFA0_SMR_STOP_Msk; + } + + /* Write to the SMR register. */ + p_ctrl->p_reg->SMR = (uint16_t) smr; + + scif_uart_extended_cfg_t * p_extend = (scif_uart_extended_cfg_t *) p_cfg->p_extend; + if ((SCIF_UART_CLOCK_EXT8X == p_extend->clock) || (SCIF_UART_CLOCK_EXT16X == p_extend->clock)) + { + /* Use external clock for baud rate */ + uint32_t semr = 0; + + if (SCIF_UART_CLOCK_EXT8X == p_extend->clock) + { + /* Set baud rate as (external clock / 8) */ + semr |= R_SCIFA0_SEMR_ABCS0_Msk; + } + + p_ctrl->p_reg->SEMR = (uint8_t) semr; + + p_ctrl->p_reg->BRR = SCIF_UART_BRR_DEFAULT_VALUE; + } + else + { + /* Set the baud rate settings for the internal baud rate generator. */ + r_scif_uart_baud_set(p_ctrl->p_reg, p_extend->p_baud_setting); + } + + /* Configure FIFO related registers. */ + r_scif_uart_fifo_cfg(p_ctrl); + + /* Enables the noise cancellation, fixed to the minimum level, if enabled in the extension. */ + if (p_extend->noise_cancel != SCIF_UART_NOISE_CANCELLATION_DISABLE) + { + p_ctrl->p_reg->SEMR_b.NFEN = 1; + } + else + { + p_ctrl->p_reg->SEMR_b.NFEN = 0; + } +} + +/*******************************************************************************************************************//** + * Make RTRG register field value + * + * @param[in] rtrg Parameter on configuration table + * @return RTRG Field value + **********************************************************************************************************************/ +static uint32_t r_scif_uart_make_rtrg (scif_uart_receive_trigger_t rtrg) +{ + uint32_t value = 0; + switch (rtrg) + { + case SCIF_UART_RECEIVE_TRIGGER_ONE: + { + /* stay RTRG as 0 */ + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_QUARTER: + { + value = 1 << R_SCIFA0_FCR_RTRG_Pos; + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_HALF: + { + value = 2 << R_SCIFA0_FCR_RTRG_Pos; + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_MAX: + { + value = 3 << R_SCIFA0_FCR_RTRG_Pos; + break; + } + + default: + { + /* stay RTRG as 0 */ + break; + } + } + + return value; +} + +/*******************************************************************************************************************//** + * Make RTRGS and RFTC register field value + * + * @param[in] rtrg Parameter on configuration table + * @return RFTC|RTRGS Field value + **********************************************************************************************************************/ +static uint32_t r_scif_uart_make_rftc (scif_uart_receive_trigger_t rtrg) +{ + uint32_t value = 0; + switch (rtrg) + { + case SCIF_UART_RECEIVE_TRIGGER_1: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (1 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_2: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (2 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_3: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (3 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_4: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (4 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_5: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (5 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_6: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (6 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_7: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (7 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_8: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (8 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_9: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (9 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_10: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (10 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_11: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (11 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_12: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (12 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_13: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (13 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_14: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (14 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + case SCIF_UART_RECEIVE_TRIGGER_15: + { + value = R_SCIFA0_FTCR_RTRGS_Msk | (15 << R_SCIFA0_FTCR_RFTC_Pos); + break; + } + + default: + { + /* stay RFTC and RTRGS as 0 */ + break; + } + } + + return value; +} + +/*******************************************************************************************************************//** + * Make RSTRG register field value + * + * @param[in] rstrg Parameter on configuration table + * @return RSTRG Field value + **********************************************************************************************************************/ +static uint32_t r_scif_uart_make_rstrg (scif_uart_rts_trigger_t rstrg) +{ + uint32_t value = 0; + switch (rstrg) + { + case SCIF_UART_RTS_TRIGGER_1: + { + value = 1 << R_SCIFA0_FCR_RSTRG_Pos; + break; + } + + case SCIF_UART_RTS_TRIGGER_4: + { + value = 2 << R_SCIFA0_FCR_RSTRG_Pos; + break; + } + + case SCIF_UART_RTS_TRIGGER_6: + { + value = 3 << R_SCIFA0_FCR_RSTRG_Pos; + break; + } + + case SCIF_UART_RTS_TRIGGER_8: + { + value = 4 << R_SCIFA0_FCR_RSTRG_Pos; + break; + } + + case SCIF_UART_RTS_TRIGGER_10: + { + value = 5 << R_SCIFA0_FCR_RSTRG_Pos; + break; + } + + case SCIF_UART_RTS_TRIGGER_12: + { + value = 6 << R_SCIFA0_FCR_RSTRG_Pos; + break; + } + + case SCIF_UART_RTS_TRIGGER_14: + { + value = 7 << R_SCIFA0_FCR_RSTRG_Pos; + break; + } + + case SCIF_UART_RTS_TRIGGER_15: + { + /* Stay RSTRG as 0 */ + break; + } + + default: + { + /* Stay RSTRG as 0 */ + break; + } + } + + return value; +} + +/*******************************************************************************************************************//** + * Resets FIFO related registers. + * + * @param[in] p_ctrl Pointer to UART instance control + **********************************************************************************************************************/ +static void r_scif_uart_fifo_cfg (scif_uart_instance_ctrl_t * const p_ctrl) +{ + /* Enable the fifo and set the tx and rx reset bits */ + uint32_t fcr = p_ctrl->p_reg->FCR; + fcr |= (R_SCIFA0_FCR_RFRST_Msk | R_SCIFA0_FCR_TFRST_Msk); + fcr &= (~(R_SCIFA0_FCR_RTRG_Msk | R_SCIFA0_FCR_TTRG_Msk | R_SCIFA0_FCR_RSTRG_Msk)); + p_ctrl->p_reg->FCR = (uint16_t) fcr; + uint32_t ftcr = 0U; + +#if (SCIF_UART_CFG_RX_ENABLE) + { + /* Otherwise, set receive trigger number as configured by the user. */ + scif_uart_extended_cfg_t const * p_extend = p_ctrl->p_cfg->p_extend; + + /* RTRG(Receive FIFO Data Trigger Number) controls when the RXI interrupt will be generated. If data is + * received but the trigger number is not met the RXI interrupt will be generated after 15 ETUs from + * the last stop bit in asynchronous mode. For more information see the FIFO Selected section of "Serial Data + * Reception in Asynchronous Mode" in the user's manual or the relevant section for the MPU being used. */ + ftcr = r_scif_uart_make_rftc(p_extend->rx_fifo_trigger); + fcr |= r_scif_uart_make_rtrg(p_extend->rx_fifo_trigger); + + #if SCIF_UART_CFG_DMAC_ENABLE + + /* When using DMAC transfer, set the threshold of the interrupt generation condition to 0. */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + ftcr |= R_SCIFA0_FTCR_RTRGS_Msk | (SCIF_UART_DMAC_RX_TRIGGER_LEVEL << R_SCIFA0_FTCR_RFTC_Pos); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + ftcr |= R_SCIFA0_FTCR_TTRGS_Msk; + } + #endif + + fcr |= r_scif_uart_make_rstrg(p_extend->rts_fifo_trigger); + } +#endif + p_ctrl->p_reg->FTCR = (uint16_t) ftcr; + + /* Set the FCR for cancellation reset. */ + fcr &= (~(R_SCIFA0_FCR_RFRST_Msk | R_SCIFA0_FCR_TFRST_Msk)); + p_ctrl->p_reg->FCR = (uint16_t) fcr; +} + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info. + * + * @param[in] p_ctrl Pointer to driver control block + * @param[in] ipl Interrupt priority level + * @param[in] irq IRQ number for this interrupt + **********************************************************************************************************************/ +static void r_scif_irq_cfg (scif_uart_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const irq) +{ + /* Disable interrupts, set priority, and store control block in the vector information so it can be accessed + * from the callback. */ + R_BSP_IrqDisable(irq); + R_BSP_IrqStatusClear(irq); + R_BSP_IrqCfg(irq, ipl, p_ctrl); +} + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info for all interrupts. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_scif_irqs_cfg (scif_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ +#if (SCIF_UART_CFG_RX_ENABLE) + scif_uart_extended_cfg_t const * p_extend = (scif_uart_extended_cfg_t const *) p_ctrl->p_cfg->p_extend; + + /* ERI is optional. */ + r_scif_irq_cfg(p_ctrl, p_cfg->eri_ipl, p_cfg->eri_irq); + r_scif_irq_cfg(p_ctrl, p_cfg->rxi_ipl, p_cfg->rxi_irq); + r_scif_irq_cfg(p_ctrl, p_extend->bri_ipl, p_extend->bri_irq); +#endif +#if (SCIF_UART_CFG_TX_ENABLE) + r_scif_irq_cfg(p_ctrl, p_cfg->txi_ipl, p_cfg->txi_irq); + r_scif_irq_cfg(p_ctrl, p_cfg->tei_ipl, p_cfg->tei_irq); +#endif +} + +/*******************************************************************************************************************//** + * Changes baud rate based on predetermined register settings. + * + * @param[in] p_scif_reg Base pointer for SCIF registers + * @param[in] p_baud_setting Pointer to other divisor related settings + * + * @note The transmitter and receiver (TE and RE bits in SCR) must be disabled prior to calling this function. + **********************************************************************************************************************/ +static void r_scif_uart_baud_set (R_SCIFA0_Type * p_scif_reg, scif_baud_setting_t const * const p_baud_setting) +{ + /* Set BRR register value. */ + uint32_t semr = p_scif_reg->SEMR & + (~(R_SCIFA0_SEMR_MDDRS_Msk | R_SCIFA0_SEMR_ABCS0_Msk | R_SCIFA0_SEMR_BGDM_Msk | + R_SCIFA0_SEMR_BRME_Msk)); + p_scif_reg->SEMR = (uint8_t) semr; + p_scif_reg->BRR = p_baud_setting->brr; + + /* Set clock source for the on-chip baud rate generator. */ + p_scif_reg->SMR_b.CKS = p_baud_setting->semr_baudrate_bits_b.cks; + + /* Set MDDR register value. */ + if (p_baud_setting->semr_baudrate_bits_b.brme && (p_baud_setting->mddr >= SCIF_UART_MDDR_MIN)) + { + p_scif_reg->SEMR = (uint8_t) semr | R_SCIFA0_SEMR_MDDRS_Msk; + p_scif_reg->MDDR = p_baud_setting->mddr; + semr |= R_SCIFA0_SEMR_BRME_Msk; + } + + /* Set clock divisor settings. */ + semr |= ((unsigned) p_baud_setting->semr_baudrate_bits_b.abcs << R_SCIFA0_SEMR_ABCS0_Pos); + semr |= ((unsigned) p_baud_setting->semr_baudrate_bits_b.bgdm << R_SCIFA0_SEMR_BGDM_Pos); + p_scif_reg->SEMR = (uint8_t) semr; +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_scif_uart_call_callback (scif_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) +{ + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + uart_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the + * callback. */ + scif_uart_prv_ns_callback p_callback = (scif_uart_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the + * callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +#if (SCIF_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TXI interrupt processing for UART mode. TXI interrupt fires when the data in the data register or FIFO register has + * been transferred to the data shift register, and the next data can be written. This interrupt writes the next data. + * After the last data byte is written, this interrupt disables the TXI interrupt and enables the TEI (transmit end) + * interrupt. + **********************************************************************************************************************/ +void scif_uart_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if ((NULL == p_ctrl->p_cfg->p_transfer_tx) && (0U != p_ctrl->tx_src_bytes)) + { + /* Write data until FIFO is full. */ + uint32_t fifo_count = (uint32_t) p_ctrl->p_reg->FDR_b.T; + for (uint32_t cnt = fifo_count; (cnt < SCIF_UART_TX_FIFO_STAGES) && p_ctrl->tx_src_bytes; cnt++) + { + p_ctrl->p_reg->FTDR = *p_ctrl->p_tx_src; + + p_ctrl->tx_src_bytes -= 1; + p_ctrl->p_tx_src += 1; + } + + /* Clear TDFE flag */ + p_ctrl->p_reg->FSR_b.TDFE = 0U; + } + + if (0U == p_ctrl->tx_src_bytes) + { + /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */ + uint32_t scr_temp; + scr_temp = p_ctrl->p_reg->SCR; + scr_temp |= R_SCIFA0_SCR_TEIE_Msk; + scr_temp &= (~R_SCIFA0_SCR_TIE_Msk); + p_ctrl->p_reg->SCR = (uint16_t) scr_temp; + + p_ctrl->p_tx_src = NULL; + if (NULL != p_ctrl->p_callback) + { + r_scif_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY); + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +#if (SCIF_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * Common code for retrieving FIFO data on RXI and DRI. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @retval none + **********************************************************************************************************************/ +static void scif_uart_receive_sub (scif_uart_instance_ctrl_t * const p_ctrl) +{ + uint8_t data; + uint16_t fsr; + uart_event_t event; + + while (p_ctrl->p_reg->FDR_b.R > 0U) + { + event = 0; + fsr = p_ctrl->p_reg->FSR; + data = p_ctrl->p_reg->FRDR; + + /* Set error event */ + if (fsr & R_SCIFA0_FSR_FER_Msk) + { + event |= UART_EVENT_ERR_FRAMING; + } + + if (fsr & R_SCIFA0_FSR_PER_Msk) + { + event |= UART_EVENT_ERR_PARITY; + } + + if (0 == p_ctrl->rx_dest_bytes) + { + /* Call user callback with the data. */ + if (0 == event) + { + event |= UART_EVENT_RX_CHAR; + } + + if (NULL != p_ctrl->p_callback) + { + r_scif_uart_call_callback(p_ctrl, (uint32_t) data, event); + } + } + else + { + if (event) + { + if (NULL != p_ctrl->p_callback) + { + r_scif_uart_call_callback(p_ctrl, (uint32_t) data, event); + } + } + else + { + *p_ctrl->p_rx_dest = data; + p_ctrl->p_rx_dest += 1; + p_ctrl->rx_dest_bytes -= 1; + + if (0 == p_ctrl->rx_dest_bytes) + { + if (NULL != p_ctrl->p_callback) + { + r_scif_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + } + } + } +} + +/*******************************************************************************************************************//** + * RXI interrupt processing for UART mode. RXI interrupt happens when data arrives to the data register or the FIFO + * register. This function calls callback function when it meets conditions below. + * - UART_EVENT_RX_COMPLETE: The number of data which has been read reaches to the number specified in R_SCIF_UART_Read() + * if a transfer instance is used for reception. + * - UART_EVENT_RX_CHAR: Data is received asynchronously (read has not been called) + * + * This interrupt also calls the callback function for RTS pin control if it is registered in R_SCIF_UART_Open(). This is + * special functionality to expand SCIF hardware capability and make RTS/CTS hardware flow control possible. If macro + * 'SCIF_UART_CFG_FLOW_CONTROL_SUPPORT' is set, it is called at the beginning in this function to set the RTS pin high, + * then it is it is called again just before leaving this function to set the RTS pin low. + * @retval none + **********************************************************************************************************************/ +void scif_uart_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* call common receive function */ + scif_uart_receive_sub(p_ctrl); + + /* Clear RDF flag */ + uint32_t fsr = p_ctrl->p_reg->FSR; + fsr &= (~R_SCIFA0_FSR_RDF_Msk); + p_ctrl->p_reg->FSR = (uint16_t) fsr; + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +#if (SCIF_UART_CFG_TX_ENABLE || SCIF_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * TEI interrupt processing for UART mode. The TEI interrupt fires after the last byte is transmitted on the TX pin. + * The user callback function is called with the UART_EVENT_TX_COMPLETE event code (if it is registered in + * R_SCIF_UART_Open()). + **********************************************************************************************************************/ +void scif_uart_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Obtaining FSR register */ + uint32_t fsr = (uint32_t) p_ctrl->p_reg->FSR; + + /* Clearing DRI and TEI */ + p_ctrl->p_reg->FSR = (uint16_t) (fsr & (~(R_SCIFA0_FSR_DR_Msk | R_SCIFA0_FSR_TEND_Msk))); + + /* Check if DRI */ + if (fsr & R_SCIFA0_FSR_DR_Msk) + { + /* call common receive function */ + scif_uart_receive_sub(p_ctrl); + } + + /* Check if TEI */ + if (fsr & R_SCIFA0_FSR_TEND_Msk) + { + uint32_t scr = p_ctrl->p_reg->SCR; + + /* Clear TEIE */ + if (0U == p_ctrl->tx_src_bytes) + { + /* Also clear TIE if no more data */ + scr &= (~(R_SCIFA0_SCR_TIE_Msk | R_SCIFA0_SCR_TEIE_Msk)); + } + else + { + scr &= (~(R_SCIFA0_SCR_TEIE_Msk)); + } + + p_ctrl->p_reg->SCR = (uint16_t) scr; + + if (NULL != p_ctrl->p_callback) + { + r_scif_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Negate driver enable if RS-485 mode is enabled. */ + r_scif_negate_de_pin(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +#if (SCIF_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * ERI interrupt processing for UART mode. When an ERI interrupt fires, the user callback function is called if it is + * registered in R_SCIF_UART_Open() with the event code that triggered the interrupt. + **********************************************************************************************************************/ +void scif_uart_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Determine cause of error. */ + uint32_t fsr = p_ctrl->p_reg->FSR; + if (fsr & R_SCIFA0_FSR_ER_Msk) + { + fsr &= (~R_SCIFA0_FSR_ER_Msk); + } + + /* Clear error condition. */ + p_ctrl->p_reg->FSR = (uint16_t) fsr; + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * BRI interrupt processing for UART mode. When an BRI interrupt fires, the user callback function is called if it is + * registered in R_SCIF_UART_Open() with the event code that triggered the interrupt. + **********************************************************************************************************************/ +void scif_uart_bri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + scif_uart_instance_ctrl_t * p_ctrl = (scif_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t data = 0U; + uart_event_t event; + + /* Determine cause of error. */ + event = 0; + uint32_t fsr = p_ctrl->p_reg->FSR; + uint32_t lsr = p_ctrl->p_reg->LSR; + if (fsr & R_SCIFA0_FSR_BRK_Msk) + { + event |= UART_EVENT_BREAK_DETECT; + fsr &= (~R_SCIFA0_FSR_BRK_Msk); + } + + if (lsr & R_SCIFA0_LSR_ORER_Msk) + { + event |= UART_EVENT_ERR_OVERFLOW; + lsr &= (~R_SCIFA0_LSR_ORER_Msk); + } + + /* Clear error condition. */ + p_ctrl->p_reg->FSR = (uint16_t) fsr; + p_ctrl->p_reg->LSR = (uint16_t) lsr; + + /* Call callback. */ + if (event) + { + if (NULL != p_ctrl->p_callback) + { + r_scif_uart_call_callback(p_ctrl, data, event); + } + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +#if SCIF_UART_CFG_DMAC_ENABLE + +/*******************************************************************************************************************//** + * Dedicated function for DMAC linkage at the time of transmission. + **********************************************************************************************************************/ +void scif_uart_tx_dmac_callback (scif_uart_instance_ctrl_t * p_ctrl) +{ + /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */ + uint32_t scr_temp; + scr_temp = p_ctrl->p_reg->SCR; + scr_temp |= R_SCIFA0_SCR_TEIE_Msk; + scr_temp &= (uint32_t) (~R_SCIFA0_SCR_TIE_Msk); + p_ctrl->p_reg->SCR = (uint16_t) scr_temp; + + p_ctrl->p_tx_src = NULL; + r_scif_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY); +} + +/*******************************************************************************************************************//** + * Dedicated function for DMAC linkage at the time of receptions. + **********************************************************************************************************************/ +void scif_uart_rx_dmac_callback (scif_uart_instance_ctrl_t * p_ctrl) +{ + p_ctrl->rx_dest_bytes = 0; + + p_ctrl->p_rx_dest = NULL; + + /* Call callback */ + r_scif_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); +} + +#endif diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index a6156c37..681a3985 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -1,3 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RA_FSP ra) +add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RZ_FSP rz) diff --git a/zephyr/rz/CMakeLists.txt b/zephyr/rz/CMakeLists.txt new file mode 100644 index 00000000..4c014264 --- /dev/null +++ b/zephyr/rz/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(rz_cfg) +zephyr_include_directories(portable) diff --git a/zephyr/rz/portable/bsp_api.h b/zephyr/rz/portable/bsp_api.h new file mode 100644 index 00000000..5d70d8b0 --- /dev/null +++ b/zephyr/rz/portable/bsp_api.h @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_API_H +#define BSP_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* FSP Common Includes. */ +#include "fsp_common_api.h" + +/* Gets MCU configuration information. */ +#include "bsp_cfg.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic push + +/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. + * We are not modifying these files so we will ignore these warnings temporarily. */ + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" +#endif + +/* Vector information for this project. This is generated by the tooling. */ +/* "vector_data.h" is not used */ + +/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ +#include "renesas.h" +#include "system.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic pop +#endif + +/* BSP Common Includes. */ +#include "bsp_common.h" + +/* BSP MCU Specific Includes. */ +#include "bsp_irq.h" +#include "bsp_io.h" +#include "bsp_group_irq.h" +#include "bsp_clocks.h" +#include "bsp_module_stop.h" +#include "bsp_security.h" + +/* Factory MCU information. */ +#include "fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ +#include "bsp_delay.h" +#include "bsp_mcu_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/zephyr/rz/portable/bsp_common.h b/zephyr/rz/portable/bsp_common.h new file mode 100644 index 00000000..7fddb866 --- /dev/null +++ b/zephyr/rz/portable/bsp_common.h @@ -0,0 +1,288 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#include "bsp_compiler_support.h" +#include "bsp_cfg.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used to signify that an interrupt factor is not available. */ +#define BSP_IRQ_DISABLED (0xFFU) + +/* Version of this module's code and API. */ +#define BSP_CODE_VERSION_MAJOR (1U) +#define BSP_CODE_VERSION_MINOR (0U) +#define BSP_API_VERSION_MAJOR (1U) +#define BSP_API_VERSION_MINOR (0U) + +#define FSP_CONTEXT_SAVE +#define FSP_CONTEXT_RESTORE + +/** Macro to log and return error without an assertion. */ +#ifndef FSP_RETURN + + #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ + return err; +#endif + +/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in + * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ +#if (1 == BSP_CFG_ERROR_LOG) + + #ifndef FSP_ERROR_LOG + #define FSP_ERROR_LOG(err) \ + fsp_error_log((err), __FILE__, __LINE__); + #endif +#else + + #define FSP_ERROR_LOG(err) +#endif + +/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP + * functions. */ +#if (3 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) +#elif (2 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) {assert(a);} +#else + #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) +#endif // ifndef FSP_ASSERT + +/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used + * to identify runtime errors in FSP functions. */ + +#define FSP_ERROR_RETURN(a, err) \ + { \ + if ((a)) \ + { \ + (void) 0; /* Do nothing */ \ + } \ + else \ + { \ + FSP_ERROR_LOG(err); \ + return err; \ + } \ + } + +/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates. + * This macro can be redefined to add a timeout if necessary. */ +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#ifndef FSP_REGISTER_READ + +/* Read a register and discard the result. */ + #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); +#endif + +/** Version data structure used by error logger macro. */ +extern const fsp_version_t g_bsp_version; + +/**************************************************************** + * + * This check is performed to select suitable ASM API with respect to core + * + * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, + * but defined(__IAR_SYSTEMS_ICC__) is false for GCC, + * so the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ + +#if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \ + defined(__ARM_ARCH_7EM__) // CM4 + #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) + #endif +#else // CM23 + #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #endif + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) +#endif + +/* This macro defines a variable for saving previous mask value */ +#ifndef FSP_CRITICAL_SECTION_DEFINE + + #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U +#endif + +/* These macros abstract methods to save and restore the interrupt state for different architectures. */ +#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK + #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) +#else + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI + #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ + (8U - __NVIC_PRIO_BITS))) +#endif + +/** This macro temporarily saves the current interrupt state and disables interrupts. */ +#ifndef FSP_CRITICAL_SECTION_ENTER + #define FSP_CRITICAL_SECTION_ENTER \ + old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ + FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) +#endif + +/** This macro restores the previously saved interrupt state, reenabling interrupts. */ +#ifndef FSP_CRITICAL_SECTION_EXIT + #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) +#endif + +/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ +#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) + +/** Used to signify that the requested IRQ vector is not defined in this system. */ +#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) + +/* Use the secure registers for secure projects and flat projects. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + #define FSP_PRIV_TZ_USE_SECURE_REGS (1) +#else + #define FSP_PRIV_TZ_USE_SECURE_REGS (0) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Different warm start entry locations in the BSP. */ +typedef enum e_bsp_warm_start_event +{ + BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. + BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. + BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up +} bsp_warm_start_event_t; + +#ifndef BSP_OVERRIDE_FSP_PRIV_CLOCK_T + +/* Private enum used in R_FSP_SystemClockHzGet. */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_ICLK = 0, /* Cortex-A55 Clock */ + FSP_PRIV_CLOCK_I2CLK, /* Cortex-M33 Clock */ + FSP_PRIV_CLOCK_GCLK, /* GPU Clock */ + FSP_PRIV_CLOCK_S0CLK, /* DDR-PHY Clock */ + FSP_PRIV_CLOCK_SPI0CLK, /* SPI0 Clock */ + FSP_PRIV_CLOCK_SPI1CLK, /* SPI1 Clock */ + FSP_PRIV_CLOCK_SD0CLK, /* SDH0 Clock */ + FSP_PRIV_CLOCK_SD1CLK, /* SDH1 Clock */ + FSP_PRIV_CLOCK_M0CLK, /* VCP, LCDC Clock */ + FSP_PRIV_CLOCK_M1CLK, /* MIPI-DSI, MIPI-CSI Clock */ + FSP_PRIV_CLOCK_M2CLK, /* CRU, MIPI-DSI Clock */ + FSP_PRIV_CLOCK_M3CLK, /* MIPI-DSI, LCDC Clock */ + FSP_PRIV_CLOCK_M4CLK, /* MIPI-DSI Clock */ + FSP_PRIV_CLOCK_HPCLK, /* Ethernet Clock */ + FSP_PRIV_CLOCK_TSUCLK, /* TSU Clock */ + FSP_PRIV_CLOCK_ZTCLK, /* JAUTH Clock */ + FSP_PRIV_CLOCK_P0CLK, /* APB-BUS Clock */ + FSP_PRIV_CLOCK_P1CLK, /* AXI-BUS Clock */ + FSP_PRIV_CLOCK_P2CLK, /* P2CLK */ + FSP_PRIV_CLOCK_ATCLK, /* ATCLK */ + FSP_PRIV_CLOCK_OSCCLK, /* OSC Clock */ + FSP_PRIV_CLOCK_NUM, +} fsp_priv_clock_t; + +#endif + +typedef struct st_bsp_unique_id +{ + union + { + uint32_t unique_id_words[4]; + uint8_t unique_id_bytes[16]; + }; +} bsp_unique_id_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables (defined in other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Return active interrupt vector number value + * + * @return Active interrupt vector number value + **********************************************************************************************************************/ +__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) +{ + xPSR_Type xpsr_value; + xpsr_value.w = __get_xPSR(); + + return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); +} + +/*******************************************************************************************************************//** + * Get unique ID is not supported in this device. + * + * @return A pointer to the unique identifier structure + **********************************************************************************************************************/ +__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet () +{ + return (bsp_unique_id_t *) NULL; +} + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +uint32_t R_FSP_SystemClockHzGet(fsp_priv_clock_t clock); +void R_FSP_SystemClockHzSet(fsp_priv_clock_t clock, uint32_t clock_sel, uint32_t clock_div); + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ +void fsp_error_log(fsp_err_t err, const char * file, int32_t line); + +#endif + +/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will + * alert the user of the error. The user can override this default behavior by defining their own + * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. + */ +#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) + + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/zephyr/rz/portable/bsp_irq.h b/zephyr/rz/portable/bsp_irq.h new file mode 100644 index 00000000..6deefaba --- /dev/null +++ b/zephyr/rz/portable/bsp_irq.h @@ -0,0 +1,217 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IRQ_H +#define BSP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) + +/*********************************************************************************************************************** + * IM33 DISABLE + * + * @param + **********************************************************************************************************************/ +#ifndef R_BSP_IM33_DISABLE + #define R_BSP_IM33_DISABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 | R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk;} +#endif + +/*********************************************************************************************************************** + * IM33 ENABLE + * + * @param + **********************************************************************************************************************/ +#ifndef R_BSP_IM33_ENABLE + #define R_BSP_IM33_ENABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 & ~R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk;} +#endif + +#define R_INTC_IM33_BEISR1_BESTAT_Msk (0x00001FFFUL) +#define R_INTC_IM33_EREISR_E1STAT_Msk (0x000000FFUL) +#define R_INTC_IM33_EREISR_E2STAT_Msk (0x0000FF00UL) +#define R_INTC_IM33_EREISR_OFSTAT_Msk (0x00FF0000UL) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + gp_renesas_isr_context[irq] = p_context; +} + +/*******************************************************************************************************************//** + * Clear the interrupt status flag for a given interrupt. + * + * @note This function does not implement processing on this device. + * + * @param[in] irq Not used + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) +{ + FSP_PARAMETER_NOT_USED(irq); + + /* Do nothing */ +} + +/*******************************************************************************************************************//** + * Clear the interrupt status flag for a given interrupt and clear the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the status flag. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) +{ + /* Clear the status flag in IM33. */ + R_BSP_IrqStatusClear(irq); + + /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ to configure. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + /* Zephyr interrupt priority will have offset, remove priority config in FSP to prevent override seting on Zephyr */ + FSP_PARAMETER_NOT_USED(priority); + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the NVIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex + * Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions + * every time an interrupt is enabled in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Clears pending interrupts in both IM33 and NVIC, then enables the interrupt. + * + * @param[in] irq Interrupt for which to clear status flag and enable in the NVIC. Note that the enums listed + * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the status flag and NVIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the NVIC. + * + * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) +{ + /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +/*******************************************************************************************************************//** + * @brief Finds the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @return ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + return gp_renesas_isr_context[irq]; +} + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/zephyr/rz/portable/fsp_features.h b/zephyr/rz/portable/fsp_features.h new file mode 100644 index 00000000..05e03161 --- /dev/null +++ b/zephyr/rz/portable/fsp_features.h @@ -0,0 +1,234 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_FEATURES_H +#define FSP_FEATURES_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#include "bsp_compiler_support.h" +#include "bsp_module_stop.h" +#include "bsp_clocks.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be started + * @param ch The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_START(ip, ch) (R_BSP_MODULE_START_ ## ip(ip, ch)) + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param ch The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_STOP(ip, ch) (R_BSP_MODULE_STOP_ ## ip(ip, ch)) + +/*******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + **********************************************************************************************************************/ + +#define R_BSP_MODULE_START_FSP_IP_GTM(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTON(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_GTM(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#define R_BSP_MODULE_START_FSP_IP_MTU3(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_MTU3(ip, ch) {NULL;} + +#define R_BSP_MODULE_START_FSP_IP_GPT(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_GPT(ip, ch) {NULL;} + +#define R_BSP_MODULE_START_FSP_IP_POEG(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_POEG(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#define R_BSP_MODULE_START_FSP_IP_SCIF(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_SCIF(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#define R_BSP_MODULE_START_FSP_IP_RIIC(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_RIIC(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#define R_BSP_MODULE_START_FSP_IP_RSPI(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_RSPI(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#define R_BSP_MODULE_START_FSP_IP_MHU(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_MHU(ip, ch) {NULL;} + +#define R_BSP_MODULE_START_FSP_IP_DMAC(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(FSP_IP_DMAC_s, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_DMAC(ip, ch) {NULL;} + +#define R_BSP_MODULE_START_FSP_IP_DMAC_s(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_DMAC_s(ip, ch) {NULL;} + +#define R_BSP_MODULE_START_FSP_IP_SSI(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_SSI(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#if BSP_FEATURE_CANFD_LITE + #define R_BSP_MODULE_START_FSP_IP_CANFD(ip, ch) {R_BSP_MSTP_START(ip, ch);} +#else + #if BSP_FEATURE_CANFD_HAS_RSCANFD == 0 + #define R_BSP_MODULE_START_FSP_IP_CANFD(ip, ch) {R_BSP_MSTP_START(ip, 0U); \ + R_BSP_MODULE_CLKON(ip, 0U); \ + R_BSP_MODULE_CLKON(ip, 1U); \ + R_BSP_MODULE_RSTOFF(ip, 0U); \ + R_BSP_MODULE_RSTOFF(ip, 1U);} + #else + #define R_BSP_MODULE_START_FSP_IP_CANFD(ip, ch) {R_BSP_MSTP_START(ip, 0U); \ + R_BSP_MODULE_CLKON(ip, 0U); \ + R_BSP_MODULE_RSTOFF(ip, 0U); \ + R_BSP_MODULE_RSTOFF(ip, 1U);} + #endif +#endif + +#if BSP_FEATURE_CANFD_LITE + #define R_BSP_MODULE_STOP_FSP_IP_CANFD(ip, ch) {R_BSP_MSTP_STOP(ip, ch)}; +#else + #define R_BSP_MODULE_STOP_FSP_IP_CANFD(ip, ch) {R_BSP_MODULE_CLKOFF(ip, 0U); \ + R_BSP_MSTP_STOP(ip, 0U);} +#endif + +#define R_BSP_MODULE_START_FSP_IP_ADC(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_ADC(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#define R_BSP_MODULE_START_FSP_IP_TSU(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_TSU(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#define R_BSP_MODULE_START_FSP_IP_WDT(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch) \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_WDT(ip, ch) {NULL;} + +#define R_BSP_MODULE_START_FSP_IP_SCI(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_SCI(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +#define R_BSP_MODULE_START_FSP_IP_XSPI(ip, ch) {R_BSP_MODULE_CLKON(ip, ch); \ + R_BSP_MSTP_START(ip, ch); \ + R_BSP_MODULE_RSTOFF(ip, ch);} + +#define R_BSP_MODULE_STOP_FSP_IP_XSPI(ip, ch) {R_BSP_MSTP_STOP(ip, ch); \ + R_BSP_MODULE_CLKOFF(ip, ch);} + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ + +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_FSP_IP_T + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_GTM = 0, ///< General Timer + FSP_IP_GPT = 1, ///< General PWM Timer + FSP_IP_POEG = 2, ///< Port Output Enable for GPT + FSP_IP_PORT = 3, ///< I/O Ports + FSP_IP_IM33 = 4, ///< IM33 (Interrupt controller) + FSP_IP_SCIF = 5, ///< Serial Communications Interface with FIFO + FSP_IP_RIIC = 6, ///< I2C Bus Interface + FSP_IP_RSPI = 7, ///< Renesas Serial Peripheral Interface + FSP_IP_MHU = 8, ///< Message Handling Unit + FSP_IP_DMAC = 9, ///< Direct Memory Access Controller + FSP_IP_DMAC_s = 9, ///< Direct Memory Access Controller + FSP_IP_SSI = 10, ///< Serial Sound Interface + FSP_IP_CANFD = 11, ///< CANFD Interface (RS-CANFD) + FSP_IP_ADC = 12, ///< A/D Converter + FSP_IP_TSU = 13, ///< Thermal Sensor Unit + FSP_IP_WDT = 14, ///< Watchdog Timer + FSP_IP_SCI = 15, ///< Serial Communications Interface + FSP_IP_MTU3 = 16, ///< Multi-Function Timer Pulse Unit 3 + FSP_IP_XSPI = 17, ///< Expanded Serial Peripheral Interface +} fsp_ip_t; + +#endif + +typedef void (* fsp_vector_t)(void); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* FSP_FEATURES_H */ diff --git a/zephyr/rz/rz_cfg/CMakeLists.txt b/zephyr/rz/rz_cfg/CMakeLists.txt new file mode 100644 index 00000000..e5f9ad6a --- /dev/null +++ b/zephyr/rz/rz_cfg/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Extract the RZ family name from CONFIG_SOC_SERIES +string(SUBSTRING ${CONFIG_SOC_SERIES} 0 3 SOC_SERIES_PREFIX) + +zephyr_include_directories(fsp_cfg/${SOC_SERIES_PREFIX}) +zephyr_include_directories(fsp_cfg/bsp/${CONFIG_SOC_SERIES}) diff --git a/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_cfg.h b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_cfg.h new file mode 100644 index 00000000..d8fa157d --- /dev/null +++ b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_cfg.h @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" + +#ifndef BSP_CFG_RTOS + #define BSP_CFG_RTOS (0) +#endif + +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_S_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_HEAP_BYTES (0x4000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#endif /* BSP_CFG_H_ */ diff --git a/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_clock_cfg.h b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_clock_cfg.h new file mode 100644 index 00000000..a9cbb47e --- /dev/null +++ b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_clock_cfg.h @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_CLOCK_OSCCLK_HZ (24000000) /* OSC 24000000Hz */ +#define BSP_CFG_CLOCK_PLL1_HZ (1100000000) /* PLL1 1100000000Hz */ +#define BSP_CFG_DIVPL1_SET_DIV (BSP_CLOCKS_PL1_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_CLOCK_ICLK_HZ (1100000000) /* ICLK 1100000000Hz */ +#define BSP_CFG_CLOCK_PLL2_1600_HZ (1600000000) /* PLL2 1600000000Hz */ +#define BSP_CFG_DIVPL2B_SET_DIV (BSP_CLOCKS_PL2B_DIV_1) /* P0CLK Div /1 */ +#define BSP_CFG_CLOCK_P0CLK_HZ (100000000) /* P0CLK 100000000Hz */ +#define BSP_CFG_CLOCK_P4CLK_HZ (160000000) /* P4CLK 160000000Hz */ +#define BSP_CFG_CLOCK_P5CLK_HZ (200000000) /* P5CLK 200000000Hz */ +#define BSP_CFG_CLOCK_TSUCLK_HZ (100000000) /* TSUCLK 100000000Hz */ +#define BSP_CFG_SEL_SDHI0_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266) /* SD0CLK Sel: 266MHz */ +#define BSP_CFG_DIVSDHI0_SET_DIV (BSP_CLOCKS_SDHI0_DIV_2) /* SD0CLK Div /2 */ +#define BSP_CFG_CLOCK_SD0CLK_HZ (133333333) /* SD0CLK 133333333Hz */ +#define BSP_CFG_SEL_SDHI1_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266) /* SD1CLK Sel: 266MHz */ +#define BSP_CFG_DIVSDHI1_SET_DIV (BSP_CLOCKS_SDHI1_DIV_2) /* SD1CLK Div /2 */ +#define BSP_CFG_CLOCK_SD1CLK_HZ (133333333) /* SD1CLK 133333333Hz */ +#define BSP_CFG_SEL_SDHI2_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266) /* SD2CLK Sel: 266MHz */ +#define BSP_CFG_DIVSDHI2_SET_DIV (BSP_CLOCKS_SDHI2_DIV_2) /* SD2CLK Div /2 */ +#define BSP_CFG_CLOCK_SD2CLK_HZ (133333333) /* SD2CLK 133333333Hz */ +#define BSP_CFG_CLOCK_PLL3_HZ (1600000000) /* PLL3 1600000000Hz */ +#define BSP_CFG_CLOCK_M0CLK_HZ (200000000) /* M0CLK 200000000Hz */ +#define BSP_CFG_DIVPL3A_SET_DIV (BSP_CLOCKS_PL3A_DIV_1) /* P1CLK Div /1 */ +#define BSP_CFG_CLOCK_P1CLK_HZ (200000000) /* P1CLK 200000000Hz */ +#define BSP_CFG_DIVPL3B_SET_DIV (BSP_CLOCKS_PL3B_DIV_1) /* P2CLK Div /1 */ +#define BSP_CFG_CLOCK_P2CLK_HZ (100000000) /* P2CLK 100000000Hz */ +#define BSP_CFG_DIVPL3C_SET_DIV (BSP_CLOCKS_PL3C_DIV_1) /* P3CLK Div /1 */ +#define BSP_CFG_CLOCK_P3CLK_HZ (200000000) /* P3CLK 200000000Hz */ +#define BSP_CFG_CLOCK_ATCLK_HZ (400000000) /* ATCLK 400000000Hz */ +#define BSP_CFG_CLOCK_ZTCLK_HZ (100000000) /* ZTCLK 100000000Hz */ +#define BSP_CFG_SELOCTA_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266) /* OCCLK Sel: 266MHz */ +#define BSP_CFG_DIVOCTA_SET_DIV (BSP_CLOCKS_OCTA_DIV_8) /* OCCLK Div /8 */ +#define BSP_CFG_CLOCK_OC0CLK_HZ (33333333) /* OC0CLK 33333333Hz */ +#define BSP_CFG_CLOCK_OC1CLK_HZ (16666666) /* OC1CLK 16666666Hz */ +#define BSP_CFG_SELSPI_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400) /* SPICLK Sel: 400MHz */ +#define BSP_CFG_DIVSPI_SET_DIV (BSP_CLOCKS_SPI_DIV_4) /* SPICLK Div /4 */ +#define BSP_CFG_CLOCK_SPI0CLK_HZ (100000000) /* SPI0CLK 100000000Hz */ +#define BSP_CFG_CLOCK_SPI1CLK_HZ (50000000) /* SPI1CLK 50000000Hz */ +#define BSP_CFG_CLOCK_PLL4_HZ (800000000) /* PLL4 800MHz */ +#define BSP_CFG_SELPL4_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL4) /* Sel: PLL4 */ +#define BSP_CFG_CLOCK_S0CLK_HZ (400000000) /* S0CLK 400000000Hz */ +#define BSP_CFG_CLOCK_PLL6_HZ (500000000) /* PLL6 500000000Hz */ +#define BSP_CFG_DIVPL6A_SET_DIV (BSP_CLOCKS_PL6A_DIV_1) /* I2CLK Div /1 */ +#define BSP_CFG_CLOCK_I2CLK_HZ (250000000) /* I2CLK 250000000Hz */ +#define BSP_CFG_DIVPL6B_SET_DIV (BSP_CLOCKS_PL6B_DIV_1) /* I3CLK Div /1 */ +#define BSP_CFG_CLOCK_I3CLK_HZ (250000000) /* I3CLK 250000000Hz */ +#define BSP_CFG_CLOCK_HPCLK_HZ (250000000) /* HPCLK 250000000Hz */ +#define BSP_CFG_CLOCK_OSCCLK2_HZ (8000000) /* OSC2 8000000Hz */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_device_cfg.h b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_device_cfg.h new file mode 100644 index 00000000..6991899d --- /dev/null +++ b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_device_cfg.h @@ -0,0 +1,10 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ + +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_device_pn_cfg.h b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_device_pn_cfg.h new file mode 100644 index 00000000..6a00d896 --- /dev/null +++ b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,14 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R9A08G045S33GBG +#define BSP_ROM_SIZE_BYTES (0) +#define BSP_RAM_SIZE_BYTES (131072) +#define BSP_PACKAGE_LFBGA +#define BSP_PACKAGE_PINS (359) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_family_cfg.h b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_family_cfg.h new file mode 100644 index 00000000..643bf2ed --- /dev/null +++ b/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/bsp_mcu_family_cfg.h @@ -0,0 +1,59 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_GROUP_RZG3S (1) +#define BSP_CURRENT_CORE (RZG3S_CORE_CM33) +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (496U) +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "bsp_multi_core.h" +#include "bsp_override.h" +#include "bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#if defined(_RZG3S_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) +#elif defined(_RZG3S_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) +#else + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) +#endif + +#define BSP_NONSECURE_TRANSITION (0) + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + +#define SCB_SCR_SLEEPDEEPS_VAL (0) +#define SCB_SCR_SLEEPDEEP_VAL (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (1) +#define SCB_AIRCR_SYSRESETREQS_VAL (0) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif +#define SCB_SHCSR_SECUREFAULTENA_VAL (1) + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (0U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (0) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/zephyr/rz/rz_cfg/fsp_cfg/rzg/r_ioport_cfg.h b/zephyr/rz/rz_cfg/fsp_cfg/rzg/r_ioport_cfg.h new file mode 100644 index 00000000..6d6f882c --- /dev/null +++ b/zephyr/rz/rz_cfg/fsp_cfg/rzg/r_ioport_cfg.h @@ -0,0 +1,18 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/zephyr/rz/rz_cfg/fsp_cfg/rzg/r_scif_uart_cfg.h b/zephyr/rz/rz_cfg/fsp_cfg/rzg/r_scif_uart_cfg.h new file mode 100644 index 00000000..4c41d9ea --- /dev/null +++ b/zephyr/rz/rz_cfg/fsp_cfg/rzg/r_scif_uart_cfg.h @@ -0,0 +1,12 @@ +/* +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCIF_UART_CFG_H_ +#define R_SCIF_UART_CFG_H_ +#define SCIF_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCIF_UART_CFG_DMAC_ENABLE (0) +#define SCIF_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#endif /* R_SCIF_UART_CFG_H_ */