diff --git a/drivers/ra/CMakeLists.txt b/drivers/ra/CMakeLists.txt index 386d3778..b4212cc9 100644 --- a/drivers/ra/CMakeLists.txt +++ b/drivers/ra/CMakeLists.txt @@ -81,12 +81,8 @@ if(CONFIG_USE_RA_FSP_SDHI) ) endif() +zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_ETHER_PHY + fsp/src/r_ether_phy/r_ether_phy.c) + zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_ETHER fsp/src/r_ether/r_ether.c) - -if (CONFIG_USE_RA_FSP_ETHER) - file(GLOB ether_phy_srcs - "fsp/src/r_ether_phy/r_ether_phy.c" - "fsp/src/r_ether_phy/targets/*/*.c") - zephyr_sources(${ether_phy_srcs}) -endif() diff --git a/drivers/ra/README b/drivers/ra/README index 8d764f68..989824fa 100644 --- a/drivers/ra/README +++ b/drivers/ra/README @@ -62,3 +62,18 @@ Patch List: * Remove the static definition in SDHI Impacted files: drivers/ra/fsp/src/r_sdhi/r_sdhi.c + + * Add in ETHER_CFG_USE_CUSTOM_PHY_DRIVER to Ethernet controller driver to skip the phy control and allow the use of Zephyr phy driver. + Add phy link speed to Ethernet controller driver instance control. + Remove static definition of some internal function is ethernet driver to allow their usage in Zephyr side + Add phy_lsi_address to Ethernet phy instance control to allow the control of phy address as input. + Remove the phy target settings as they are not used. + Impacted files: + drivers/ra/fsp/src/r_ether/r_ether.c + drivers/ra/fsp/src/r_ether_phy/r_ether_phy.c + drivers/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c + drivers/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c + drivers/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c + drivers/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c + drivers/ra/fsp/inc/instances/r_ether_phy.h + drivers/ra/fsp/inc/instances/r_ether.h diff --git a/drivers/ra/fsp/inc/instances/r_ether.h b/drivers/ra/fsp/inc/instances/r_ether.h index e934aec5..a42e4878 100644 --- a/drivers/ra/fsp/inc/instances/r_ether.h +++ b/drivers/ra/fsp/inc/instances/r_ether.h @@ -105,6 +105,7 @@ typedef struct st_ether_instance_ctrl ether_link_change_t link_change; ///< status of link change ether_magic_packet_t magic_packet; ///< status of magic packet detection ether_link_establish_status_t link_establish_status; ///< Current Link status + uint32_t link_speed_duplex; ///< Current Link speed and duplex status /* Pointer to callback and optional working memory */ void (* p_callback)(ether_callback_args_t *); diff --git a/drivers/ra/fsp/inc/instances/r_ether_phy.h b/drivers/ra/fsp/inc/instances/r_ether_phy.h index ac6aa1df..d8fcd2d4 100644 --- a/drivers/ra/fsp/inc/instances/r_ether_phy.h +++ b/drivers/ra/fsp/inc/instances/r_ether_phy.h @@ -42,6 +42,7 @@ typedef enum e_ether_phy_interface_status typedef struct st_ether_phy_instance_ctrl { uint32_t open; ///< Used to determine if the channel is configured + uint8_t phy_lsi_address; ///< Address of PHY-LSI /* Configuration of Ethernet PHY-LSI module. */ ether_phy_cfg_t const * p_ether_phy_cfg; ///< Pointer to initial configurations. diff --git a/drivers/ra/fsp/src/r_ether/r_ether.c b/drivers/ra/fsp/src/r_ether/r_ether.c index 7ad57825..9ba82c15 100644 --- a/drivers/ra/fsp/src/r_ether/r_ether.c +++ b/drivers/ra/fsp/src/r_ether/r_ether.c @@ -161,7 +161,7 @@ static void ether_enable_icu(ether_instance_ctrl_t * const p_instance_ctrl) static void ether_disable_icu(ether_instance_ctrl_t * const p_instance_ctrl); static void ether_reset_mac(R_ETHERC_EDMAC_Type * const p_reg); static void ether_init_descriptors(ether_instance_ctrl_t * const p_instance_ctrl); -static void ether_init_buffers(ether_instance_ctrl_t * const p_instance_ctrl); +void ether_init_buffers(ether_instance_ctrl_t * const p_instance_ctrl); static fsp_err_t ether_buffer_get(ether_instance_ctrl_t * const p_instance_ctrl, void ** const p_buffer, uint32_t * p_buffer_size); @@ -170,10 +170,10 @@ static void ether_pause_resolution(uint32_t const local_ability, uint32_t const partner_ability, uint32_t * ptx_pause, uint32_t * prx_pause); -static void ether_configure_mac(ether_instance_ctrl_t * const p_instance_ctrl, +void ether_configure_mac(ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mac_addr[], const uint8_t mode); -static fsp_err_t ether_do_link(ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode); +fsp_err_t ether_do_link(ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode); static fsp_err_t ether_link_status_check(ether_instance_ctrl_t const * const p_instance_ctrl); static uint8_t ether_check_magic_packet_detection_bit(ether_instance_ctrl_t const * const p_instance_ctrl); static void ether_configure_padding(ether_instance_ctrl_t * const p_instance_ctrl); @@ -307,7 +307,6 @@ fsp_err_t R_ETHER_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p p_instance_ctrl->p_context = p_cfg->p_context; p_instance_ctrl->p_callback_memory = NULL; - R_BSP_MODULE_START(FSP_IP_ETHER, p_instance_ctrl->p_ether_cfg->channel); /* Software reset */ ether_reset_mac(p_instance_ctrl->p_reg_edmac); @@ -315,6 +314,7 @@ fsp_err_t R_ETHER_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p /* Setting the padding function */ ether_configure_padding(p_instance_ctrl); +#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER /* Software reset the PHY */ phy_ret = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->open( p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl, @@ -330,11 +330,16 @@ fsp_err_t R_ETHER_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_cfg); } #endif +#else + phy_ret = FSP_SUCCESS; +#endif if (FSP_SUCCESS == phy_ret) { +#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->startAutoNegotiate( p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl); +#endif /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ p_reg_etherc->ECSR = ETHER_ETHERC_INTERRUPT_FACTOR_ALL; @@ -398,8 +403,10 @@ fsp_err_t R_ETHER_Close (ether_ctrl_t * const p_ctrl) /* Disable Ethernet interrupt. */ ether_disable_icu(p_instance_ctrl); +#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->close( p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl); +#endif p_reg_etherc->ECSIPR_b.LCHNGIP = 0; p_reg_edmac->EESIPR_b.ECIIP = 0; @@ -1328,7 +1335,7 @@ static void ether_init_descriptors (ether_instance_ctrl_t * const p_instance_ctr * ETHERC control block. * Return Value : none ***********************************************************************************************************************/ -static void ether_init_buffers (ether_instance_ctrl_t * const p_instance_ctrl) +void ether_init_buffers (ether_instance_ctrl_t * const p_instance_ctrl) { uint32_t i; uint32_t buffer_num; @@ -1547,7 +1554,7 @@ static void ether_pause_resolution (uint32_t const local_ability, * USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode * Return Value : none ***********************************************************************************************************************/ -static void ether_configure_mac (ether_instance_ctrl_t * const p_instance_ctrl, +void ether_configure_mac (ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mac_addr[], const uint8_t mode) { @@ -1603,7 +1610,7 @@ static void ether_configure_mac (ether_instance_ctrl_t * const p_instance_ctrl, * or result of Auto-negotiation is abnormal. * ***********************************************************************************************************************/ -static fsp_err_t ether_do_link (ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode) +fsp_err_t ether_do_link (ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode) { fsp_err_t err; R_ETHERC0_Type * p_reg_etherc; @@ -1625,12 +1632,17 @@ static fsp_err_t ether_do_link (ether_instance_ctrl_t * const p_instance_ctrl, c p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; +#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER /* Set the link status */ link_result = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->linkPartnerAbilityGet( p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl, &link_speed_duplex, &local_pause_bits, &partner_pause_bits); +#else + link_result = FSP_SUCCESS; + link_speed_duplex = p_instance_ctrl->link_speed_duplex; +#endif if (FSP_SUCCESS == link_result) { @@ -1807,11 +1819,15 @@ static uint8_t ether_check_magic_packet_detection_bit (ether_instance_ctrl_t con **********************************************************************************************************************/ static fsp_err_t ether_link_status_check (ether_instance_ctrl_t const * const p_instance_ctrl) { - fsp_err_t err = FSP_SUCCESS; + fsp_err_t err; fsp_err_t link_status; +#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER link_status = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->linkStatusGet( p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl); +#else + link_status = FSP_SUCCESS; +#endif if (FSP_ERR_ETHER_PHY_ERROR_LINK == link_status) { diff --git a/drivers/ra/fsp/src/r_ether_phy/r_ether_phy.c b/drivers/ra/fsp/src/r_ether_phy/r_ether_phy.c index 368e655b..14439860 100644 --- a/drivers/ra/fsp/src/r_ether_phy/r_ether_phy.c +++ b/drivers/ra/fsp/src/r_ether_phy/r_ether_phy.c @@ -213,8 +213,7 @@ fsp_err_t R_ETHER_PHY_Open (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t con /* Initialize configuration of ethernet phy module. */ p_instance_ctrl->p_ether_phy_cfg = p_cfg; - /* Configure pins for MII or RMII. Set PHYMODE0 if MII is selected. */ - R_PMISC->PFENET = (uint8_t) ((ETHER_PHY_MII_TYPE_MII == p_cfg->mii_type) << R_PMISC_PFENET_PHYMODE0_Pos); + R_BSP_MODULE_START(FSP_IP_ETHER, p_instance_ctrl->p_ether_phy_cfg->channel); #if ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC uint32_t reg = 0; @@ -670,7 +669,7 @@ static void ether_phy_reg_set (ether_phy_instance_ctrl_t * p_instance_ctrl, uint data |= (ETHER_PHY_MII_WRITE << 12); /* OP code(WT) */ } - data |= (uint32_t) (p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << 7); /* PHY Address */ + data |= (uint32_t) (p_instance_ctrl->phy_lsi_address << 7); /* PHY Address */ data |= (reg_addr << 2); /* Reg Address */ diff --git a/drivers/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c b/drivers/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c deleted file mode 100644 index f8628c22..00000000 --- a/drivers/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c +++ /dev/null @@ -1,94 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - ***********************************************************************************************************************/ - -/* Access to peripherals and board defines. */ -#include "bsp_api.h" -#include "r_ether_phy.h" - -#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) - -/*********************************************************************************************************************** - * Macro definitions - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - ***********************************************************************************************************************/ - -/* Vendor Specific PHY Registers */ - #define ETHER_PHY_REG_PAGE_SELECT (0x13) - #define ETHER_PHY_REG_14H (0x14) - -/*********************************************************************************************************************** - * Exported global variables (to be accessed by other files) - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global function - ***********************************************************************************************************************/ -void ether_phy_target_dp83620_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); -bool ether_phy_target_dp83620_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, - uint32_t line_speed_duplex); - -/*********************************************************************************************************************** - * Private global variables and functions - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Function Name: ether_phy_targets_initialize - * Description : PHY-LSI specific initialization processing - * Arguments : p_api_ctrl - - * Ethernet channel number - * Return Value : none - ***********************************************************************************************************************/ -void ether_phy_target_dp83620_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) -{ - uint32_t reg; - - if (ETHER_PHY_MII_TYPE_RMII == p_instance_ctrl->p_ether_phy_cfg->mii_type) - { - /* - * The following is the recommended settings for TI to output 50 MHz from CLK_OUT when using Texas Instruments DP83620 - * in RMII master mode. - */ - R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PAGE_SELECT, 0x0006); - R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_14H, ®); - if (0x800A == reg) - { - R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_14H, 0x000A); - R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PAGE_SELECT, 0x0000); - } - } -} /* End of function ether_phy_targets_initialize() */ - -/*********************************************************************************************************************** - * Function Name: ether_phy_targets_is_support_link_partner_ability - * Description : Check if the PHY-LSI connected Ethernet controller supports link ability - * Arguments : p_instance_ctrl - - * Ethernet control block - * line_speed_duplex - - * Line speed duplex of link partner PHY-LSI - * Return Value : bool - ***********************************************************************************************************************/ -bool ether_phy_target_dp83620_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, - uint32_t line_speed_duplex) -{ - FSP_PARAMETER_NOT_USED(p_instance_ctrl); - FSP_PARAMETER_NOT_USED(line_speed_duplex); - - /* This PHY-LSI supports half and full duplex mode. */ - return true; -} /* End of function ether_phy_targets_is_support_link_partner_ability() */ - -#endif /* ETHER_PHY_CFG_TARGET_DP83620_ENABLE */ diff --git a/drivers/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c b/drivers/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c deleted file mode 100644 index 2b31ae5d..00000000 --- a/drivers/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c +++ /dev/null @@ -1,110 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - ***********************************************************************************************************************/ - -/* Access to peripherals and board defines. */ -#include "bsp_api.h" -#include "r_ether_phy.h" - -#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) - -/*********************************************************************************************************************** - * Macro definitions - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - ***********************************************************************************************************************/ - -/* Vendor Specific PHY Registers */ - #define ETHER_PHY_REG_PHY_CONTROL_20 (0x14) - -/*********************************************************************************************************************** - * Exported global variables (to be accessed by other files) - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global function - ***********************************************************************************************************************/ -void ether_phy_target_ics1894_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); -bool ether_phy_target_ics1894_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, - uint32_t line_speed_duplex); - -/*********************************************************************************************************************** - * Private global variables and functions - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Function Name: ether_phy_targets_initialize - * Description : PHY-LSI specific initialization processing - * Arguments : p_instance_ctrl - - * Ethernet control block - * Return Value : none - ***********************************************************************************************************************/ -void ether_phy_target_ics1894_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) -{ - uint32_t reg; - - /* - * When ICS1894NL of the the Renesas Electronics Corporation. is used, - * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. - * The setting of the pin is changed so that only the state of LINK is output. - */ - R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_20, ®); - reg |= 0x0007U; - R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_20, reg); -} /* End of function ether_phy_targets_initialize() */ - -/*********************************************************************************************************************** - * Function Name: ether_phy_targets_is_support_link_partner_ability - * Description : Check if the PHY-LSI connected Ethernet controller supports link ability - * Arguments : p_instance_ctrl - - * Ethernet control block - * line_speed_duplex - - * Line speed duplex of link partner PHY-LSI - * Return Value : bool - ***********************************************************************************************************************/ -bool ether_phy_target_ics1894_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, - uint32_t line_speed_duplex) -{ - FSP_PARAMETER_NOT_USED(p_instance_ctrl); - bool ret = false; - - /* This PHY-LSI only supports full duplex mode. */ - switch (line_speed_duplex) - { - /* 10Mbps full duplex */ - case ETHER_PHY_LINK_SPEED_10F: - { - ret = true; - break; - } - - /* 100Mbps full duplex */ - case ETHER_PHY_LINK_SPEED_100F: - { - ret = true; - break; - } - - /* Half duplex is not supported */ - default: - { - break; - } - } - - return ret; -} /* End of function ether_phy_targets_is_support_link_partner_ability() */ - -#endif /* ETHER_PHY_CFG_TARGET_ICS1894_ENABLE */ diff --git a/drivers/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c b/drivers/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c deleted file mode 100644 index 966bf442..00000000 --- a/drivers/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c +++ /dev/null @@ -1,91 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - ***********************************************************************************************************************/ - -/* Access to peripherals and board defines. */ -#include "bsp_api.h" -#include "r_ether_phy.h" - -#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) - -/*********************************************************************************************************************** - * Macro definitions - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - ***********************************************************************************************************************/ - -/* Vendor Specific PHY Registers */ - #define ETHER_PHY_REG_PHY_CONTROL_1 (0x1E) - - #define ETHER_PHY_LED_MODE_LED0_LINK_LED1_ACTIVITY (0x4000U) - #define ETHER_PHY_LED_MODE_MASK (0xC000U) - -/*********************************************************************************************************************** - * Exported global variables (to be accessed by other files) - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global function - ***********************************************************************************************************************/ -void ether_phy_target_ksz8041_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); -bool ether_phy_target_ksz8041_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, - uint32_t line_speed_duplex); - -/*********************************************************************************************************************** - * Private global variables and functions - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Function Name: ether_phy_targets_initialize - * Description : PHY-LSI specific initialization processing - * Arguments : p_api_ctrl - - * Ethernet channel number - * Return Value : none - ***********************************************************************************************************************/ -void ether_phy_target_ksz8041_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) -{ - uint32_t reg; - - /* - * When KSZ8041NL of the Micrel, Inc. is used, - * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. - * The setting of the pin is changed so that only the state of LINK is output. - */ - R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_1, ®); - reg &= ~ETHER_PHY_LED_MODE_MASK; - reg |= ETHER_PHY_LED_MODE_LED0_LINK_LED1_ACTIVITY; - R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_1, reg); -} /* End of function ether_phy_targets_initialize() */ - -/*********************************************************************************************************************** - * Function Name: ether_phy_targets_is_support_link_partner_ability - * Description : Check if the PHY-LSI connected Ethernet controller supports link ability - * Arguments : p_instance_ctrl - - * Ethernet control block - * line_speed_duplex - - * Line speed duplex of link partner PHY-LSI - * Return Value : bool - ***********************************************************************************************************************/ -bool ether_phy_target_ksz8041_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, - uint32_t line_speed_duplex) -{ - FSP_PARAMETER_NOT_USED(p_instance_ctrl); - FSP_PARAMETER_NOT_USED(line_speed_duplex); - - /* This PHY-LSI supports half and full duplex mode. */ - return true; -} /* End of function ether_phy_targets_is_support_link_partner_ability() */ - -#endif /* ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE */ diff --git a/drivers/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c b/drivers/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c deleted file mode 100644 index 6af6aba7..00000000 --- a/drivers/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c +++ /dev/null @@ -1,105 +0,0 @@ -/* -* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ - -/*********************************************************************************************************************** - * Includes , "Project Includes" - ***********************************************************************************************************************/ - -/* Access to peripherals and board defines. */ -#include "bsp_api.h" -#include "r_ether_phy.h" - -#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) - -/*********************************************************************************************************************** - * Macro definitions - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Typedef definitions - ***********************************************************************************************************************/ - -/* Vendor Specific PHY Registers */ - #define ETHER_PHY_REG_INTERRUPT_CONTROL (0x1B) - #define ETHER_PHY_REG_PHY_CONTROL2 (0x1F) - - #define ETHER_PHY_REG_INTERRUPT_CONTROL_LUIE_OFFSET (0x8) - #define ETHER_PHY_REG_INTERRUPT_CONTROL_LDIE_OFFSET (0xA) - #define ETHER_PHY_REG_PHY_CONTROL2_RMII_RCS_OFFSET (0x7) - #define ETHER_PHY_REG_PHY_CONTROL2_RMII_IL_OFFSET (0x9) - -/*********************************************************************************************************************** - * Exported global variables (to be accessed by other files) - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Exported global function - ***********************************************************************************************************************/ -void ether_phy_target_ksz8091rnb_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); -bool ether_phy_target_ksz8091rnb_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, - uint32_t line_speed_duplex); - -/*********************************************************************************************************************** - * Private global variables and functions - ***********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Function Name: ether_phy_targets_initialize - * Description : PHY-LSI specific initialization processing - * Arguments : p_api_ctrl - - * Ethernet channel number - * Return Value : none - ***********************************************************************************************************************/ -void ether_phy_target_ksz8091rnb_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) -{ - uint32_t reg; - - /* When KSZ8091RNB of the Micrel, Inc. is used. - * This processing is a setting to use Link -up and Link-down as a factor of INTPR. - * b10=1:Enable link-down interrupt - * b8=1 :Enable link-up interrupt - */ - R_ETHER_PHY_Write(p_instance_ctrl, - ETHER_PHY_REG_INTERRUPT_CONTROL, - (0x1 << ETHER_PHY_REG_INTERRUPT_CONTROL_LUIE_OFFSET | 0x1 << - ETHER_PHY_REG_INTERRUPT_CONTROL_LDIE_OFFSET)); - R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_INTERRUPT_CONTROL, ®); - R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL2, ®); - - /* b7=1:RMII 50MHz clock mode; clock input to XI(pin 9) is 50MHz */ - #if (ETHER_PHY_CFG_USE_REF_CLK == 0) - reg |= (0x1 << ETHER_PHY_REG_PHY_CONTROL2_RMII_RCS_OFFSET); - #endif - - /* b9=0:Interrupt pin active low */ - reg &= (uint16_t) ~(0x1 << ETHER_PHY_REG_PHY_CONTROL2_RMII_IL_OFFSET); - R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL2, reg); -} /* End of function ether_phy_targets_initialize() */ - -/*********************************************************************************************************************** - * Function Name: ether_phy_targets_is_support_link_partner_ability - * Description : Check if the PHY-LSI connected Ethernet controller supports link ability - * Arguments : p_instance_ctrl - - * Ethernet control block - * line_speed_duplex - - * Line speed duplex of link partner PHY-LSI - * Return Value : bool - ***********************************************************************************************************************/ -bool ether_phy_target_ksz8091rnb_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, - uint32_t line_speed_duplex) -{ - FSP_PARAMETER_NOT_USED(p_instance_ctrl); - FSP_PARAMETER_NOT_USED(line_speed_duplex); - - /* This PHY-LSI supports half and full duplex mode. */ - return true; -} /* End of function ether_phy_targets_is_support_link_partner_ability() */ - -#endif /* ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE */ diff --git a/zephyr/ra/ra_cfg/fsp_cfg/r_ether_cfg.h b/zephyr/ra/ra_cfg/fsp_cfg/r_ether_cfg.h index 42726bd7..c059b248 100644 --- a/zephyr/ra/ra_cfg/fsp_cfg/r_ether_cfg.h +++ b/zephyr/ra/ra_cfg/fsp_cfg/r_ether_cfg.h @@ -13,6 +13,7 @@ extern "C" { #define ETHER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) #define ETHER_CFG_LINK_PRESENT (0) #define ETHER_CFG_USE_LINKSTA (0) +#define ETHER_CFG_USE_CUSTOM_PHY_DRIVER (1) #ifdef __cplusplus } diff --git a/zephyr/ra/ra_cfg/fsp_cfg/r_ether_phy_cfg.h b/zephyr/ra/ra_cfg/fsp_cfg/r_ether_phy_cfg.h index 1df55acd..afd6538e 100644 --- a/zephyr/ra/ra_cfg/fsp_cfg/r_ether_phy_cfg.h +++ b/zephyr/ra/ra_cfg/fsp_cfg/r_ether_phy_cfg.h @@ -10,27 +10,15 @@ extern "C" { #endif -#if DT_PROP(DT_NODELABEL(eth), phy_type) == 4 -#define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE 1 -#elif DT_PROP(DT_NODELABEL(eth), phy_type) == 3 -#define ETHER_PHY_CFG_TARGET_DP83620_ENABLE 1 -#elif DT_PROP(DT_NODELABEL(eth), phy_type) == 2 -#define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE 1 -#elif DT_PROP(DT_NODELABEL(eth), phy_type) == 1 -#define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE 1 -#else -#error "Invalid LSI type" -#endif - #define ETHER_PHY_LSI_TYPE_KIT_COMPONENT DT_PROP(DT_NODELABEL(eth), phy_type) -#define BOARD_PHY_REF_CLK (1) +#define BOARD_PHY_REF_CLK (0) #define ETHER_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) #ifndef ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (0) #endif #ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE -#define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (1) +#define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (0) #endif #ifndef ETHER_PHY_CFG_TARGET_DP83620_ENABLE #define ETHER_PHY_CFG_TARGET_DP83620_ENABLE (0) @@ -39,10 +27,10 @@ extern "C" { #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) #endif #ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE -#define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (1) #endif #define ETHER_PHY_CFG_USE_REF_CLK (BOARD_PHY_REF_CLK) -#define ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC (1) +#define ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC (0) #ifdef __cplusplus }