From 8e1b3e180722449b441bfe069e5c0ce68e23cc8b Mon Sep 17 00:00:00 2001 From: Abram Early Date: Fri, 6 Sep 2024 16:07:12 -0600 Subject: [PATCH 1/2] stm32cube: update stm32l4 to cube version V1.18.1 Update Cube version for STM32L4xx series on https://github.com/STMicroelectronics from version v1.18.0 to version v1.18.1 Signed-off-by: Abram Early --- stm32cube/stm32l4xx/README | 4 +- .../drivers/include/Legacy/stm32_hal_legacy.h | 80 +- .../drivers/include/stm32l4xx_hal_comp.h | 136 ++-- .../drivers/include/stm32l4xx_hal_cortex.h | 2 + .../drivers/include/stm32l4xx_hal_dma2d.h | 8 +- .../drivers/include/stm32l4xx_hal_dsi.h | 6 +- .../drivers/include/stm32l4xx_hal_i2c.h | 2 - .../drivers/include/stm32l4xx_hal_lptim.h | 4 +- .../drivers/include/stm32l4xx_hal_ltdc.h | 7 +- .../drivers/include/stm32l4xx_hal_nand.h | 2 +- .../drivers/include/stm32l4xx_hal_pcd.h | 17 +- .../drivers/include/stm32l4xx_hal_pcd_ex.h | 1 - .../drivers/include/stm32l4xx_hal_pka.h | 4 +- .../drivers/include/stm32l4xx_hal_pssi.h | 60 +- .../drivers/include/stm32l4xx_hal_qspi.h | 6 +- .../drivers/include/stm32l4xx_hal_rng_ex.h | 34 +- .../drivers/include/stm32l4xx_hal_smbus.h | 2 - .../drivers/include/stm32l4xx_hal_spi.h | 46 +- .../drivers/include/stm32l4xx_hal_spi_ex.h | 2 +- .../drivers/include/stm32l4xx_hal_tim.h | 48 +- .../drivers/include/stm32l4xx_hal_uart.h | 5 +- .../drivers/include/stm32l4xx_hal_usart.h | 5 +- .../drivers/include/stm32l4xx_ll_cortex.h | 2 +- .../drivers/include/stm32l4xx_ll_dma.h | 6 +- .../drivers/include/stm32l4xx_ll_dma2d.h | 125 ++-- .../drivers/include/stm32l4xx_ll_fmc.h | 58 +- .../drivers/include/stm32l4xx_ll_i2c.h | 9 +- .../drivers/include/stm32l4xx_ll_iwdg.h | 14 +- .../drivers/include/stm32l4xx_ll_lpuart.h | 17 + .../drivers/include/stm32l4xx_ll_pka.h | 20 +- .../drivers/include/stm32l4xx_ll_rng.h | 2 +- .../drivers/include/stm32l4xx_ll_rtc.h | 20 +- .../drivers/include/stm32l4xx_ll_spi.h | 115 +-- .../drivers/include/stm32l4xx_ll_system.h | 38 +- .../drivers/include/stm32l4xx_ll_tim.h | 36 +- .../drivers/include/stm32l4xx_ll_usb.h | 101 +-- .../drivers/include/stm32l4xx_ll_utils.h | 2 +- .../stm32l4xx/drivers/src/stm32l4xx_hal.c | 2 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_can.c | 41 +- .../drivers/src/stm32l4xx_hal_comp.c | 2 +- .../drivers/src/stm32l4xx_hal_cortex.c | 82 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_crc.c | 2 +- .../drivers/src/stm32l4xx_hal_crc_ex.c | 2 - .../drivers/src/stm32l4xx_hal_cryp.c | 58 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_dac.c | 12 +- .../drivers/src/stm32l4xx_hal_dac_ex.c | 13 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_dma.c | 2 +- .../drivers/src/stm32l4xx_hal_dma2d.c | 35 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_dsi.c | 63 +- .../drivers/src/stm32l4xx_hal_gpio.c | 8 +- .../drivers/src/stm32l4xx_hal_hash.c | 71 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_hcd.c | 37 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_i2c.c | 294 ++++++-- .../drivers/src/stm32l4xx_hal_iwdg.c | 3 +- .../drivers/src/stm32l4xx_hal_lptim.c | 4 +- .../drivers/src/stm32l4xx_hal_ltdc.c | 28 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_mmc.c | 13 +- .../drivers/src/stm32l4xx_hal_nand.c | 2 +- .../drivers/src/stm32l4xx_hal_ospi.c | 11 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_pcd.c | 71 +- .../drivers/src/stm32l4xx_hal_pcd_ex.c | 4 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_pka.c | 40 +- .../drivers/src/stm32l4xx_hal_pssi.c | 186 +++-- .../drivers/src/stm32l4xx_hal_qspi.c | 22 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_rcc.c | 6 +- .../drivers/src/stm32l4xx_hal_rcc_ex.c | 6 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_rng.c | 10 +- .../drivers/src/stm32l4xx_hal_rng_ex.c | 12 +- .../drivers/src/stm32l4xx_hal_rtc_ex.c | 2 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_sai.c | 32 +- .../stm32l4xx/drivers/src/stm32l4xx_hal_sd.c | 11 +- .../drivers/src/stm32l4xx_hal_smartcard.c | 2 +- .../drivers/src/stm32l4xx_hal_smbus.c | 7 +- .../drivers/src/stm32l4xx_hal_smbus_ex.c | 2 + .../stm32l4xx/drivers/src/stm32l4xx_hal_spi.c | 399 +++++----- .../drivers/src/stm32l4xx_hal_spi_ex.c | 2 +- .../drivers/src/stm32l4xx_hal_sram.c | 3 + .../stm32l4xx/drivers/src/stm32l4xx_hal_tim.c | 30 +- .../drivers/src/stm32l4xx_hal_tim_ex.c | 33 +- .../drivers/src/stm32l4xx_hal_uart.c | 41 +- .../drivers/src/stm32l4xx_hal_uart_ex.c | 2 +- .../drivers/src/stm32l4xx_hal_usart.c | 17 +- .../drivers/src/stm32l4xx_hal_usart_ex.c | 2 +- .../stm32l4xx/drivers/src/stm32l4xx_ll_adc.c | 10 - .../stm32l4xx/drivers/src/stm32l4xx_ll_comp.c | 6 +- .../drivers/src/stm32l4xx_ll_dma2d.c | 10 +- .../stm32l4xx/drivers/src/stm32l4xx_ll_fmc.c | 65 +- .../stm32l4xx/drivers/src/stm32l4xx_ll_pka.c | 2 +- .../stm32l4xx/drivers/src/stm32l4xx_ll_rcc.c | 2 +- .../stm32l4xx/drivers/src/stm32l4xx_ll_rng.c | 2 +- .../stm32l4xx/drivers/src/stm32l4xx_ll_spi.c | 7 +- .../stm32l4xx/drivers/src/stm32l4xx_ll_tim.c | 29 +- .../stm32l4xx/drivers/src/stm32l4xx_ll_usb.c | 177 +++-- stm32cube/stm32l4xx/release_note.html | 701 ++++++++++++++++-- stm32cube/stm32l4xx/soc/stm32l412xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l422xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l431xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l432xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l433xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l442xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l443xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l451xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l452xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l462xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l471xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l475xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l476xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l485xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l486xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l496xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l4a6xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l4p5xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l4q5xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l4r5xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l4r7xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l4r9xx.h | 4 +- stm32cube/stm32l4xx/soc/stm32l4s5xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l4s7xx.h | 2 +- stm32cube/stm32l4xx/soc/stm32l4s9xx.h | 4 +- stm32cube/stm32l4xx/soc/stm32l4xx.h | 2 +- 120 files changed, 2408 insertions(+), 1432 deletions(-) diff --git a/stm32cube/stm32l4xx/README b/stm32cube/stm32l4xx/README index 202119b39..c4125ac04 100644 --- a/stm32cube/stm32l4xx/README +++ b/stm32cube/stm32l4xx/README @@ -6,7 +6,7 @@ Origin: http://www.st.com/en/embedded-software/stm32cubel4.html Status: - version v1.18.0 + version v1.18.1 Purpose: ST Microelectronics official MCU package for STM32L4 series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeL4 Commit: - 82e7ade76252f4c973c9fc7515ebc42b850b7c0b + d4c40b36185bd0d75e33c94ebc8337b634bbcc94 Maintained-by: External diff --git a/stm32cube/stm32l4xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32l4xx/drivers/include/Legacy/stm32_hal_legacy.h index e6fbac213..cb912660d 100644 --- a/stm32cube/stm32l4xx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32l4xx/drivers/include/Legacy/stm32_hal_legacy.h @@ -275,7 +275,7 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -548,6 +548,16 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -796,6 +806,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -1239,10 +1264,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) +#if defined(STM32H5) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 */ +#endif /* STM32H5 || STM32H7RS */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1254,10 +1279,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1595,6 +1620,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1805,7 +1832,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1987,12 +2014,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ /** * @} @@ -2307,8 +2334,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2341,8 +2368,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2399,8 +2426,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2417,7 +2444,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -2719,6 +2746,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3642,8 +3675,12 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3745,9 +3782,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 - +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3893,7 +3931,7 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3930,7 +3968,8 @@ extern "C" { #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ defined (STM32H7) || \ - defined (STM32L0) || defined (STM32L1) + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG #endif @@ -4215,6 +4254,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_comp.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_comp.h index 88d5623fa..148602400 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_comp.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_comp.h @@ -388,16 +388,16 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ } while(0) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ } while(0) @@ -473,16 +473,16 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ } while(0) @@ -618,46 +618,46 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ +/* compatibility with other STM32 series. */ #if defined(COMP_CSR_INMESEL_1) && defined(DAC_CHANNEL2_SUPPORT) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) ||\ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5)) #elif defined(COMP_CSR_INMESEL_1) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) ||\ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5)) #elif defined(DAC_CHANNEL2_SUPPORT) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)) #else -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)) #endif /* COMP_CSR_INMESEL_1 && DAC_CHANNEL2_SUPPORT */ @@ -671,57 +671,57 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #if defined(COMP2) #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ ) #else #if defined(TIM3) #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ ) #else #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ ) #endif /* TIM3 */ #endif /* COMP2 */ #if defined(COMP2) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ + ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) #else #if defined(TIM3) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - (((__INSTANCE__) == COMP1) && \ - (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + (((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) #else #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - (((__INSTANCE__) == COMP1) && \ - (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + (((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) )) #endif /* TIM3 */ #endif /* COMP2 */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_cortex.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_cortex.h index 3688093a2..8a1600710 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_cortex.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_cortex.h @@ -296,6 +296,8 @@ void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dma2d.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dma2d.h index ea2af19d2..6b7fe7d35 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dma2d.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dma2d.h @@ -510,9 +510,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); @@ -549,8 +549,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t */ /* Peripheral State functions ***************************************************/ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); /** * @} diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dsi.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dsi.h index c6106ac3f..3844d58cc 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dsi.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dsi.h @@ -1184,7 +1184,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t *ParametersTable); + const uint8_t *ParametersTable); HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, @@ -1222,8 +1222,8 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun * @brief Peripheral State and Errors functions * @{ */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi); +HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi); /** * @} diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_i2c.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_i2c.h index 51adedc9f..a4671ee4c 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_i2c.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_lptim.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_lptim.h index a1f354099..a99e10d19 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_lptim.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_lptim.h @@ -466,6 +466,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value + * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. * @retval None * @note The ARR register can only be modified when the LPTIM instance is enabled. */ @@ -864,9 +865,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ - ((__AUTORELOAD__) <= 0x0000FFFFUL)) - #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) #define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_ltdc.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_ltdc.h index d1451175c..77bfae175 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_ltdc.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_ltdc.h @@ -600,7 +600,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); @@ -633,8 +634,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * @{ */ /* Peripheral State functions *************************************************/ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc); /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_nand.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_nand.h index 3b149f455..de748b4a4 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_nand.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_nand.h @@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd.h index 3cf254972..0f538dc66 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd.h @@ -864,20 +864,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); \ *(pdwReg) &= 0x3FFU; \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - *(pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd_ex.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd_ex.h index d86c89c85..72216a49f 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd_ex.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd_ex.h @@ -45,7 +45,6 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_FS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pka.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pka.h index 97ba96c4a..60f3ba94d 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pka.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pka.h @@ -541,8 +541,8 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka); -uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka); +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka); +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka); /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pssi.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pssi.h index df7a69669..0d369c771 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pssi.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pssi.h @@ -31,6 +31,12 @@ extern "C" { * @{ */ #if defined(PSSI) + +#ifndef USE_HAL_PSSI_REGISTER_CALLBACKS +/* For backward compatibility, if USE_HAL_PSSI_REGISTER_CALLBACKS not defined, define it to 1*/ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + /** @addtogroup PSSI PSSI * @brief PSSI HAL module driver * @{ @@ -47,12 +53,18 @@ extern "C" { */ typedef struct { - uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ - uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ - uint32_t ControlSignal; /* !< Configures Data enable and Data ready */ - uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */ - uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */ - uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */ + uint32_t DataWidth; /* !< Configures the data width. + This parameter can be a value of @ref PSSI_DATA_WIDTH. */ + uint32_t BusWidth; /* !< Configures the parallel bus width. + This parameter can be a value of @ref PSSI_BUS_WIDTH. */ + uint32_t ControlSignal; /* !< Configures Data enable and Data ready. + This parameter can be a value of @ref ControlSignal_Configuration. */ + uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity. + This parameter can be a value of @ref Clock_Polarity. */ + uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity. + This parameter can be a value of @ref Data_Enable_Polarity. */ + uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity. + This parameter can be a value of @ref Ready_Polarity. */ } PSSI_InitTypeDef; @@ -76,16 +88,23 @@ typedef enum /** * @brief PSSI handle Structure definition */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) typedef struct __PSSI_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ { PSSI_TypeDef *Instance; /*!< PSSI register base address. */ PSSI_InitTypeDef Init; /*!< PSSI Initialization Structure. */ uint32_t *pBuffPtr; /*!< PSSI Data buffer. */ uint32_t XferCount; /*!< PSSI transfer count */ uint32_t XferSize; /*!< PSSI transfer size */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< PSSI Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< PSSI Rx DMA Handle parameters */ +#endif /*HAL_DMA_MODULE_ENABLED*/ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ @@ -93,6 +112,7 @@ typedef struct __PSSI_HandleTypeDef void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp Init callback. */ void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback. */ +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ HAL_LockTypeDef Lock; /*!< PSSI lock. */ __IO HAL_PSSI_StateTypeDef State; /*!< PSSI transfer state. */ @@ -100,7 +120,7 @@ typedef struct __PSSI_HandleTypeDef } PSSI_HandleTypeDef; - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /** * @brief HAL PSSI Callback pointer definition */ @@ -120,7 +140,7 @@ typedef enum HAL_PSSI_MSPDEINIT_CB_ID = 0x06U /*!< PSSI Msp DeInit callback ID */ } HAL_PSSI_CallbackIDTypeDef; - +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ /** * @} @@ -140,8 +160,9 @@ typedef enum #define HAL_PSSI_ERROR_OVER_RUN 0x00000004U /*!< FIFO Over-run error */ #define HAL_PSSI_ERROR_DMA 0x00000008U /*!< Dma error */ #define HAL_PSSI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) #define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */ - +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ /** * @} @@ -201,7 +222,7 @@ typedef enum /** * @} */ -/** @defgroup Reday_Polarity Reday Polarity +/** @defgroup Ready_Polarity Ready Polarity * @{ */ #define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */ @@ -215,8 +236,6 @@ typedef enum */ #define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */ #define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */ - - /** * @} */ @@ -272,12 +291,15 @@ typedef enum * @param __HANDLE__ specifies the PSSI handle. * @retval None */ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) #define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ }while(0) +#else +#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PSSI_STATE_RESET) +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ /** @@ -414,6 +436,7 @@ typedef enum #define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \ ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH )) + /** * @} */ @@ -434,11 +457,11 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi); /* Callbacks Register/UnRegister functions ***********************************/ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID); - +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ /** * @} @@ -452,9 +475,11 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +#if defined(HAL_DMA_MODULE_ENABLED) HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @} @@ -465,8 +490,8 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); */ /* Peripheral State functions ***************************************************/ -HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi); -uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); +HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi); +uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi); /** * @} @@ -482,7 +507,6 @@ void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); - /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_qspi.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_qspi.h index 519e33b9c..028d8cd66 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_qspi.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_qspi.h @@ -630,13 +630,13 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); -uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); +HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi); +uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); -uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); +uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi); #if defined(QUADSPI_CR_DFM) HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); #endif diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rng_ex.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rng_ex.h index e3a4f926c..8de89d127 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rng_ex.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,9 +55,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -65,11 +65,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -108,7 +108,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -132,7 +132,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -141,7 +141,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -150,7 +150,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -187,7 +187,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -196,11 +196,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -211,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_smbus.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_smbus.h index 7ae5e807a..2f71e9fdb 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_smbus.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi.h index a7b6b2a56..c139d462b 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi_ex.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi_ex.h index 359d30e8b..d60065267 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi_ex.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi_ex.h @@ -48,7 +48,7 @@ extern "C" { /** @addtogroup SPIEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_tim.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_tim.h index 6cbfe7abd..571d93140 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_tim.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_tim.h @@ -398,29 +398,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1001,8 +1000,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ /** * @} */ @@ -1842,8 +1841,9 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ - ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -1896,7 +1896,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -1955,8 +1954,8 @@ mode. ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ @@ -2285,7 +2284,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_uart.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_uart.h index 9d23073c3..f3e60f3a2 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_uart.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_uart.h @@ -1263,7 +1263,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @{ */ #if defined(USART_PRESC_PRESCALER) -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1278,8 +1278,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_usart.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_usart.h index 5b2b06dae..922557195 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_usart.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_usart.h @@ -566,8 +566,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval None */ #define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF) -#endif /* USART_CR2_SLVEN */ +#endif /* USART_CR2_SLVEN */ /** @brief Enable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. * @param __INTERRUPT__ specifies the USART interrupt source to enable. @@ -747,8 +747,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_cortex.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_cortex.h index 4ad94d653..e88c3c932 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_cortex.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_cortex.h @@ -586,7 +586,7 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisa /* Set base address */ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); /* Configure MPU */ - WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); } /** diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma.h index 5f936140f..ca62934c5 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma.h @@ -70,7 +70,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) /* Defines used for the bit position in the register and perform offsets */ -#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U)) +#define DMA_POSITION_CSELR_CXS(Channel) POSITION_VAL(DMA_CSELR_C1S << (((Channel)*4U) & 0x1FU)) /** * @} */ @@ -1512,7 +1512,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) { MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, - DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); + DMA_CSELR_C1S << (((Channel) * 4U) & 0x1FU), PeriphRequest << DMA_POSITION_CSELR_CXS(Channel)); } /** @@ -1546,7 +1546,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, - DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS); + DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS(Channel)); } #endif /* DMAMUX1 */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma2d.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma2d.h index d5b5f1d97..19a421d7a 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma2d.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma2d.h @@ -579,7 +579,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); } @@ -616,7 +616,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); } @@ -641,7 +641,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); } @@ -680,7 +680,7 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) * * (*) value not defined in all devices. */ -__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); } @@ -713,7 +713,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); } @@ -740,7 +740,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_ * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); } @@ -767,7 +767,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } @@ -825,7 +825,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); } @@ -857,7 +857,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF @endif */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); } @@ -880,7 +880,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint * @param DMA2Dx DMA2D Instance * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); } @@ -903,7 +903,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrO * @param DMA2Dx DMA2D Instance * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); } @@ -926,7 +926,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t O * @param DMA2Dx DMA2D Instance * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); } @@ -947,8 +947,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) { - MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ - OutputColor); + WRITE_REG(DMA2Dx->OCOLR, OutputColor); } /** @@ -963,7 +962,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t Out * @param DMA2Dx DMA2D Instance * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); @@ -987,7 +986,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t L * @param DMA2Dx DMA2D Instance * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); } @@ -1010,7 +1009,7 @@ __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTi * @param DMA2Dx DMA2D Instance * @retval Dead time value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); } @@ -1043,7 +1042,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); } @@ -1070,7 +1069,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); } @@ -1092,7 +1091,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); } @@ -1137,7 +1136,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); } @@ -1166,7 +1165,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); } @@ -1189,7 +1188,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); } @@ -1216,7 +1215,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); } @@ -1243,7 +1242,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); } @@ -1266,7 +1265,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); } @@ -1306,7 +1305,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); } @@ -1329,7 +1328,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); } @@ -1352,7 +1351,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); } @@ -1375,7 +1374,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); } @@ -1398,7 +1397,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); } @@ -1425,7 +1424,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); } @@ -1456,7 +1455,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); } @@ -1478,7 +1477,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); } @@ -1523,7 +1522,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); } @@ -1552,7 +1551,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); } @@ -1575,7 +1574,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); } @@ -1602,7 +1601,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); } @@ -1629,7 +1628,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); } @@ -1652,7 +1651,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); } @@ -1692,7 +1691,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); } @@ -1715,7 +1714,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); } @@ -1738,7 +1737,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); } @@ -1761,7 +1760,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); } @@ -1784,7 +1783,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); } @@ -1811,7 +1810,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); } @@ -1835,7 +1834,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); } @@ -1846,7 +1845,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); } @@ -1857,7 +1856,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); } @@ -1868,7 +1867,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); } @@ -1879,7 +1878,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); } @@ -1890,7 +1889,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); } @@ -2107,7 +2106,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); } @@ -2118,7 +2117,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); } @@ -2129,7 +2128,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); } @@ -2140,7 +2139,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); } @@ -2151,7 +2150,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); } @@ -2162,7 +2161,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); } @@ -2178,16 +2177,16 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) * @{ */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx); ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); /** diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_fmc.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_fmc.h index 4a697d4fd..e44c9bcfd 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_fmc.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_fmc.h @@ -162,76 +162,77 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number - This parameter can be a value of @ref FMC_Byte_Lane */ + This parameter can be a value of @ref FMC_Byte_Lane */ #if defined(FMC_PCSCNTR_CSCOUNT) FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank for PSRAM refresh. - This parameter can be set to ENABLE or DISABLE */ + This parameter can be set to ENABLE or DISABLE */ uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses, valid only if MaxChipSelectPulse is ENABLE. This parameter can be a value between Min_Data = 1 and Max_Data = 65535. - @note: This parameter is common to all NSBank. */ -#endif + @note: This parameter is common to all NSBank. */ +#endif /* FMC_PCSCNTR_CSCOUNT */ } FMC_NORSRAM_InitTypeDef; /** @@ -280,7 +281,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; #endif /* FMC_BANK1 */ @@ -787,11 +788,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -819,11 +820,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -834,7 +835,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -845,7 +846,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u #endif /* FMC_BANK3 */ - /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_i2c.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_i2c.h index 5e1b626fc..612bc76f8 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_i2c.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_i2c.h @@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_iwdg.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_iwdg.h index 6bf901a20..9986a0ed3 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_iwdg.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_iwdg.h @@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } @@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); } diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_lpuart.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_lpuart.h index b2553cb5f..2e8cd5d83 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_lpuart.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_lpuart.h @@ -2837,6 +2837,23 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +#if defined(USART_CR1_FIFOEN) +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +#endif /* USART_CR1_FIFOEN */ /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_pka.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_pka.h index 9bb222b1e..daf43027e 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_pka.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_pka.h @@ -223,7 +223,7 @@ __STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabled(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabled(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL); } @@ -282,7 +282,7 @@ __STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode) * @arg @ref LL_PKA_MODE_MODULAR_SUB * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL */ -__STATIC_INLINE uint32_t LL_PKA_GetMode(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_GetMode(const PKA_TypeDef *PKAx) { return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); } @@ -379,7 +379,7 @@ __STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL); } @@ -390,7 +390,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL); } @@ -402,7 +402,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL); } @@ -421,7 +421,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL); } @@ -432,7 +432,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL); } @@ -444,7 +444,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL); } @@ -455,7 +455,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); } @@ -504,7 +504,7 @@ __STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx) * @{ */ -ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx); +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx); ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct); void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct); diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rng.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rng.h index f0d06368f..b67a19ba0 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rng.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rng.h @@ -683,7 +683,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthconfiguration(RNG_TypeDef *RNGx) * @{ */ #if defined(RNG_CR_CED) -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); #endif /* RNG_CR_CED */ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rtc.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rtc.h index 8d231980d..88a7e8e74 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rtc.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rtc.h @@ -1524,7 +1524,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1558,7 +1558,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1593,7 +1593,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1628,7 +1628,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1678,7 +1678,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1825,7 +1825,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n @@ -1859,7 +1859,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1906,7 +1906,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n @@ -1948,7 +1948,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n @@ -2010,7 +2010,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h index d377cca13..ffc750e24 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_system.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_system.h index 94b722bf7..f9ac27e00 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_system.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_system.h @@ -60,6 +60,8 @@ extern "C" { * @{ */ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ + /** * @brief Power-down in Run mode Flash key */ @@ -154,22 +156,22 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE * @{ */ -#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */ /** * @} */ @@ -772,7 +774,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) */ __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) { - MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); + MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << POSITION_VAL((Line >> LL_EXTI_REGISTER_PINPOS_SHFT))); } /** @@ -813,7 +815,7 @@ __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) */ __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) { - return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); } /** diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_tim.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_tim.h index fb8110f22..bbde1c905 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_tim.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_tim.h @@ -653,10 +653,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -2143,8 +2163,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) @@ -2183,8 +2203,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_usb.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_usb.h index 38f9d47c6..fb8ad14b9 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_usb.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_usb.h @@ -37,6 +37,13 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ + +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ /** * @brief USB Mode definition @@ -85,42 +92,42 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ #if defined (USB_OTG_FS) - uint32_t Host_channels; /*!< Host Channels number. + uint8_t Host_channels; /*!< Host Channels number. This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ +#endif /* defined (USB_OTG_FS) */ - uint32_t dma_enable; /*!< USB DMA state. + uint8_t dma_enable; /*!< USB DMA state. If DMA is not supported this parameter shall be set by default to zero */ -#endif /* defined (USB_OTG_FS) */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ #if defined (USB_OTG_FS) - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ #endif /* defined (USB_OTG_FS) */ } USB_CfgTypeDef; @@ -513,41 +520,41 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup); -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); -uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, @@ -556,12 +563,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc); -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB_OTG_FS) */ #if defined (USB) diff --git a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_utils.h b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_utils.h index d465c0dd6..8c2d542f3 100644 --- a/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_utils.h +++ b/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_utils.h @@ -274,7 +274,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks + * @param Ticks Frequency of Ticks (Hz) * @retval None */ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal.c index 87385fc50..9d0c69301 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal.c @@ -53,7 +53,7 @@ */ #define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */ -#define STM32L4XX_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ +#define STM32L4XX_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ #define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\ |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_can.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_can.c index 9c51e6fb2..c0d18e4a4 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_can.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_can.c @@ -33,7 +33,7 @@ (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() (++) Configure CAN pins (+++) Enable the clock for the CAN GPIOs - (+++) Configure CAN pins as alternate function open-drain + (+++) Configure CAN pins as alternate function (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) (+++) Configure the CAN interrupt priority using HAL_NVIC_SetPriority() @@ -235,6 +235,7 @@ * @{ */ #define CAN_TIMEOUT_VALUE 10U +#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U /** * @} */ @@ -248,8 +249,8 @@ */ /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Request initialisation */ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); @@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) #else /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /* Reset the CAN peripheral */ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); @@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca */ /** @defgroup CAN_Exported_Functions_Group2 Configuration functions - * @brief Configuration functions. - * + * @brief Configuration functions. + * @verbatim ============================================================================== ##### Configuration functions ##### @@ -868,7 +869,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter /* Check the parameters */ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); -#endif +#endif /* CAN3 */ /* Initialisation mode for the filter */ SET_BIT(can_ip->FMR, CAN_FMR_FINIT); @@ -878,7 +879,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); -#endif +#endif /* CAN3 */ /* Convert filter number into bit position */ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); @@ -970,8 +971,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter */ /** @defgroup CAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * + * @brief Control functions + * @verbatim ============================================================================== ##### Control functions ##### @@ -1143,7 +1144,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) { __IO uint32_t count = 0; - uint32_t timeout = 1000000U; HAL_CAN_StateTypeDef state = hcan->State; if ((state == HAL_CAN_STATE_READY) || @@ -1159,15 +1159,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) count++; /* Check if timeout is reached */ - if (count > timeout) + if (count > CAN_WAKEUP_TIMEOUT_COUNTER) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; return HAL_ERROR; } - } - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); /* Return function status */ return HAL_OK; @@ -1608,8 +1607,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi */ /** @defgroup CAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * + * @brief Interrupts management + * @verbatim ============================================================================== ##### Interrupts management ##### @@ -2074,8 +2073,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group5 Callback functions - * @brief CAN Callback functions - * + * @brief CAN Callback functions + * @verbatim ============================================================================== ##### Callback functions ##### @@ -2324,8 +2323,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * + * @brief CAN Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_comp.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_comp.c index 9af268399..80650672d 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_comp.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_comp.c @@ -351,7 +351,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) #else MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | - COMP_CSR_POLARITY | COMP_CSR_HYST | + COMP_CSR_POLARITY | COMP_CSR_HYST | COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, tmp_csr ); diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cortex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cortex.c index 8b4ef7d8f..c529a48ef 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cortex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cortex.c @@ -451,6 +451,37 @@ void HAL_MPU_Disable(void) MPU->CTRL = 0; } +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} /** * @brief Initialize and configure the Region and the memory to be protected. @@ -463,38 +494,31 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; - if ((MPU_Init->Enable) != RESET) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00; - MPU->RASR = 0x00; - } +/* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); } #endif /* __MPU_PRESENT */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc.c index 0382661cc..cdf1f2638 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc.c @@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) #else /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + CLEAR_REG(hcrc->Instance->IDR); #endif /* CRC_IDR32BITSLENGTH_SUPPORT */ /* DeInit the low level hardware */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc_ex.c index ffe13b1f1..c876bb6be 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cryp.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cryp.c index 223c61439..8fe7662c8 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cryp.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cryp.c @@ -529,7 +529,7 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) ============================================================================== [..] This section provides functions allowing to: (+) Encrypt plaintext using AES algorithm in different chaining modes - (+) Decrypt cyphertext using AES algorithm in different chaining modes + (+) Decrypt ciphertext using AES algorithm in different chaining modes [..] Three processing functions are available: (+) Polling mode (+) Interrupt mode @@ -546,7 +546,7 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). @@ -577,7 +577,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). @@ -608,7 +608,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). @@ -634,10 +634,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer * @param Timeout Specify Timeout value @@ -665,10 +665,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer * @param Timeout Specify Timeout value @@ -696,10 +696,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Decrypt pCypherData in AES CTR decryption mode, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer * @param Timeout Specify Timeout value @@ -732,7 +732,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -762,7 +762,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -793,7 +793,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -818,10 +818,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly @@ -848,10 +848,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly @@ -878,10 +878,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly @@ -913,7 +913,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -946,7 +946,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -977,7 +977,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * the configuration information for CRYP module * @param pPlainData Pointer to the plaintext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData Pointer to the cyphertext buffer. + * @param pCypherData Pointer to the ciphertext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -1003,10 +1003,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES ECB decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly @@ -1034,10 +1034,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CBC decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly @@ -1065,10 +1065,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CTR decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the deciphered data are available in pPlainData. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData Pointer to the cyphertext buffer + * @param pCypherData Pointer to the ciphertext buffer * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly @@ -1687,7 +1687,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) } else /* Process the rest of input data */ { - /* Get the Intput data address */ + /* Get the Input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Increment/decrement instance pointer/counter */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac.c index 9a9394e86..b74bef585 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac.c @@ -264,7 +264,7 @@ and a pointer to the user callback function. Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. @@ -279,9 +279,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + reset to the legacy weak (overridden) functions in the HAL_DAC_Init and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -296,7 +296,7 @@ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** DAC HAL driver macros list *** ============================================= @@ -1445,7 +1445,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1554,7 +1554,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call /** * @brief Unregister a User DAC Callback - * DAC Callback is redirected to the weak (surcharged) predefined callback + * DAC Callback is redirected to the weak (overridden) predefined callback * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac_ex.c index 994811f93..db05de93d 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac_ex.c @@ -425,10 +425,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* OPAMP_CSR_OUTCAL is actually one value more */ - trimmingvalue++; - /* Set right trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + /* Check trimming value below maximum */ + if (trimmingvalue < 0x1FU) + { + /* Trimming is actually one value more */ + trimmingvalue++; + + /* Set right trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + } } /* Disable the selected DAC channel calibration */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma.c index d476444ac..c9927db55 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma.c @@ -895,7 +895,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Channel. * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma2d.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma2d.c index bee68498f..d0f03db53 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma2d.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma2d.c @@ -118,7 +118,7 @@ and a pointer to the user callback function. (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. + weak (surcharged) function. @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -130,16 +130,16 @@ (+) MspDeInitCallback : DMA2D MspDeInit. (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions: + all callbacks are reset to the corresponding legacy weak (surcharged) functions: examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init + reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Exception as well for Transfer Completion and Transfer Error callbacks that are not defined - as weak (overridden) functions. They must be defined by the user to be resorted to. + as weak (surcharged) functions. They must be defined by the user to be resorted to. Callbacks can be registered/unregistered in READY state only. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered @@ -151,7 +151,7 @@ When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. + and weak (surcharged) callbacks are used. [..] (@) You can refer to the DMA2D HAL driver header file for more useful macros @@ -335,7 +335,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /* Before aborting any DMA2D transfer or CLUT loading, check first whether or not DMA2D clock is enabled */ - if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) + if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U) { /* Abort DMA2D transfer if any */ if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) @@ -443,7 +443,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief Register a User DMA2D Callback - * To be used instead of the weak (overridden) predefined callback + * To be used instead of the weak (surcharged) predefined callback * @param hdma2d DMA2D handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -542,7 +542,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM /** * @brief Unregister a DMA2D Callback - * DMA2D Callback is redirected to the weak (overridden) predefined callback + * DMA2D Callback is redirected to the weak (surcharged) predefined callback * @param hdma2d DMA2D handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -583,11 +583,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ break; case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ break; case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ break; default : @@ -603,11 +603,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ switch (CallbackID) { case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ break; case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ break; default : @@ -1043,7 +1043,8 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); @@ -1097,7 +1098,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ @@ -1800,7 +1801,7 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - DMA2D_LayerCfgTypeDef *pLayerCfg; + const DMA2D_LayerCfgTypeDef *pLayerCfg; uint32_t regMask; uint32_t regValue; @@ -2082,7 +2083,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t * the configuration information for the DMA2D. * @retval HAL state */ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->State; } @@ -2093,7 +2094,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) * the configuration information for DMA2D. * @retval DMA2D Error Code */ -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->ErrorCode; } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dsi.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dsi.c index ddb64423a..8c3dd6d2e 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dsi.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dsi.c @@ -130,7 +130,7 @@ all callbacks are set to the corresponding weak functions: examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DSI_Init() + reset to the legacy weak (overridden) functions in the HAL_DSI_Init() and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -395,24 +395,53 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI } } - /*************************** Set the PHY parameters ***************************/ + __HAL_DSI_ENABLE(hdsi); + + /************************ Set the DSI clock parameters ************************/ + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + /*************************** Set the PHY parameters ***************************/ /* D-PHY clock and digital enable*/ - hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + hdsi->Instance->PCTLR |= DSI_PCTLR_DEN; + + hdsi->Instance->PCTLR |= DSI_PCTLR_CKE; - /* Clock lane configuration */ - hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); - hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); /* Configure the number of active data lanes */ hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; - /************************ Set the DSI clock parameters ************************/ + /* Get tick */ + tickstart = HAL_GetTick(); + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC)) + { + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); - /* Set the TX escape clock division factor */ - hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; - hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + return HAL_TIMEOUT; + } + } + } + else + { + while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \ + DSI_PSR_PSS1 | DSI_PSR_PSSC)) + { + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ @@ -431,6 +460,12 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI hdsi->Instance->IER[1U] = 0U; hdsi->ErrorMsk = 0U; + __HAL_DSI_DISABLE(hdsi); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + /* Initialize the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; @@ -1628,14 +1663,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t *ParametersTable) + const uint8_t *ParametersTable) { uint32_t uicounter; uint32_t nbBytes; uint32_t count; uint32_t tickstart; uint32_t fifoword; - uint8_t *pparams = ParametersTable; + const uint8_t *pparams = ParametersTable; /* Process locked */ __HAL_LOCK(hdsi); @@ -3099,7 +3134,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun * the configuration information for the DSI. * @retval HAL state */ -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi) { return hdsi->State; } @@ -3110,7 +3145,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) * the configuration information for the DSI. * @retval DSI Error Code */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi) { /* Get the error code */ return hdsi->ErrorCode; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_gpio.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_gpio.c index 6ba7d60e8..5933b2d20 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_gpio.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_gpio.c @@ -301,7 +301,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) * @brief De-initialize the GPIOx peripheral registers to their default reset values. * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) @@ -387,7 +387,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @brief Read the specified input port pin. * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin specifies the port bit to read. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -417,7 +417,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin @@ -468,7 +468,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * until the next reset. * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin specifies the port bits to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_hash.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_hash.c index 8eede1343..2d17a9a29 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_hash.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_hash.c @@ -123,7 +123,7 @@ (#) HAL in interruption mode (interruptions driven) (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes. - This is why, for driver implementation simplicity’s sake, user is requested to enter a message the + This is why, for driver implementation simplicity s sake, user is requested to enter a message the length of which is a multiple of 4 bytes. (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR @@ -1825,8 +1825,9 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint32_t tmp; - for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U) + for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++) { /* Write input data 4 bytes at a time */ HASH->DIN = *(uint32_t *)inputaddr; @@ -1834,8 +1835,16 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size)) + if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size)) { + /* wait for flag BUSY not set before Wait for DINIS = 1*/ + if ((buffercounter * 4U) >= 64U) + { + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + } /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free in the input buffer */ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) @@ -1850,14 +1859,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashInCount = Size - (buffercounter + 4U); + hhash->HashInCount = Size - ((buffercounter * 4U) + 4U); } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashKeyCount = Size - (buffercounter + 4U); + hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U); } else { @@ -1876,6 +1885,52 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */ /* At this point, all the data have been entered to the Peripheral: exit */ + + if ((Size % 4U) != 0U) + { + if (hhash->Init.DataType == HASH_DATATYPE_16B) + { + /* Write remaining input data */ + + if ((Size % 4U) <= 2U) + { + HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + HASH->DIN = *(uint32_t *)inputaddr; + } + + } + else if ((hhash->Init.DataType == HASH_DATATYPE_8B) + || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */ + { + /* Write remaining input data */ + if ((Size % 4U) == 1U) + { + HASH->DIN = (uint32_t) * (uint8_t *)inputaddr; + } + if ((Size % 4U) == 2U) + { + HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + tmp = *(uint8_t *)inputaddr; + tmp |= (uint32_t)*(uint8_t *)(inputaddr + 1U) << 8U; + tmp |= (uint32_t)*(uint8_t *)(inputaddr + 2U) << 16U; + HASH->DIN = tmp; + } + + } + else + { + HASH->DIN = *(uint32_t *)inputaddr; + } + /*hhash->HashInCount += 4U;*/ + } + + return HAL_OK; } @@ -2963,11 +3018,11 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, HAL_StatusTypeDef status ; HAL_HASH_StateTypeDef State_tmp = hhash->State; -#if defined (HASH_CR_MDMAT) + #if defined (HASH_CR_MDMAT) /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set (case of multi-buffer HASH processing) */ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); -#endif /* MDMA defined*/ + #endif /* MDMA defined*/ /* If State is ready or suspended, start or resume polling-based HASH processing */ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { @@ -3446,7 +3501,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Enable the DMA In DMA channel */ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \ - : (inputSize / 4U))); + : (inputSize / 4U))); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_hcd.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_hcd.c index b3eb1c62f..6592b2c94 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_hcd.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_hcd.c @@ -106,8 +106,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx; - /* Check the HCD handle allocation */ if (hhcd == NULL) { @@ -117,8 +115,6 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); - USBx = hhcd->Instance; - if (hhcd->State == HAL_HCD_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -148,22 +144,31 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) hhcd->State = HAL_HCD_STATE_BUSY; /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 8)) == 0U) - { - hhcd->Init.dma_enable = 0U; - } + hhcd->Init.dma_enable = 0U; /* Disable the Interrupts */ __HAL_HCD_DISABLE(hhcd); /* Init the Core (common init.) */ - (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } - /* Force Host Mode*/ - (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + /* Force Host Mode */ + if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } /* Init Host */ - (void)USB_HostInit(hhcd->Instance, hhcd->Init); + if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } hhcd->State = HAL_HCD_STATE_READY; @@ -1201,7 +1206,7 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1417,7 +1422,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; uint32_t num_packets; @@ -1558,7 +1563,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; uint32_t pktcnt; @@ -1624,7 +1629,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0; __IO uint32_t hprt0_dup; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_i2c.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_i2c.c index 30bea1ec6..f2a44238c 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_i2c.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1288,7 +1288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } @@ -1379,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1405,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1426,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1437,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1449,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1472,31 +1486,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -1778,7 +1809,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; xfermode = I2C_RELOAD_MODE; } else @@ -2127,7 +2158,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; xfermode = I2C_RELOAD_MODE; } else @@ -2674,7 +2705,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } @@ -2712,7 +2743,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -3322,22 +3353,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); @@ -4549,7 +4564,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4558,7 +4573,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -4983,7 +5000,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else @@ -5138,7 +5163,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 { if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -5172,7 +5205,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, @@ -5229,9 +5270,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5394,7 +5434,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } xfermode = I2C_RELOAD_MODE; } else @@ -5542,7 +5590,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -5589,7 +5645,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, @@ -5659,9 +5723,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -6260,6 +6323,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ @@ -6347,6 +6411,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -6764,7 +6879,15 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Set the XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } } else { @@ -6875,6 +6998,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { @@ -6986,16 +7115,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -7003,19 +7134,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -7029,12 +7155,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) { @@ -7044,11 +7174,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } /** diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_iwdg.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_iwdg.c index 51d12928d..08550b316 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_iwdg.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_iwdg.c @@ -126,7 +126,8 @@ The timeout value is multiplied by 1000 to be converted in milliseconds. LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_lptim.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_lptim.c index 00a41fc8d..9b5b3d49a 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_lptim.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_lptim.c @@ -388,10 +388,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) } else { - /* Check LPTIM2 Input1 source */ + /* Check LPTIM Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); - /* Configure LPTIM2 Input1 source */ + /* Configure LPTIM Input1 source */ hlptim->Instance->OR = hlptim->Init.Input1Source; } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ltdc.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ltdc.c index 27c55f6f9..aa088a6ef 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ltdc.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ltdc.c @@ -279,24 +279,20 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); /* Set Synchronization size */ - hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); tmp = (hltdc->Init.HorizontalSync << 16U); - hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync)); /* Set Accumulated Back porch */ - hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); tmp = (hltdc->Init.AccumulatedHBP << 16U); - hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP)); /* Set Accumulated Active Width */ - hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); tmp = (hltdc->Init.AccumulatedActiveW << 16U); - hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH)); /* Set Total Width */ - hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); tmp = (hltdc->Init.TotalWidth << 16U); - hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh)); /* Set the background color value */ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); @@ -916,11 +912,12 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx) { uint32_t tmp; uint32_t counter; - uint32_t *pcolorlut = pCLUT; + const uint32_t *pcolorlut = pCLUT; /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -2092,7 +2089,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * the configuration information for the LTDC. * @retval HAL state */ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc) { return hltdc->State; } @@ -2103,7 +2100,7 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @retval LTDC Error Code */ -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc) { return hltdc->ErrorCode; } @@ -2154,9 +2151,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | - LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2)); /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); @@ -2167,8 +2162,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); /* Configure the color frame buffer start address */ - LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress); if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_mmc.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_mmc.c index b977ac3be..6fe2e03c7 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_mmc.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_mmc.c @@ -75,7 +75,7 @@ SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - (#) Initialize the SDMMC peripheral interface with defaullt configuration. + (#) Initialize the SDMMC peripheral interface with default configuration. The initialization process is done at 400KHz. You can change or adapt this frequency by adjusting the "ClockDiv" field. The MMC Card frequency (SDMMC_CK) is computed as follows: @@ -305,7 +305,7 @@ #define MMC_EXT_CSD_S_A_TIMEOUT_POS 8 /* Frequencies used in the driver for clock divider calculation */ -#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */ +#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ #define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ /** * @} @@ -4365,7 +4365,14 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) } else { - Init.ClockDiv = sdmmc_clk/(2U*MMC_HIGH_SPEED_FREQ); + if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ) + { + Init.ClockDiv = 0; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U; + } (void)SDMMC_Init(hmmc->Instance, Init); SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_nand.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_nand.c index d5e378d2b..8da9bd02b 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_nand.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_nand.c @@ -493,7 +493,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ospi.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ospi.c index f92a91efb..bf3e07c3c 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ospi.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_ospi.c @@ -1145,7 +1145,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1238,7 +1239,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -2596,8 +2598,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * #endif /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || + ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { #if defined (OCTOSPIM_CR_MUXEN) diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pcd.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pcd.c index f6c0695f7..fef5e99d1 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pcd.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pcd.c @@ -130,9 +130,6 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { -#if defined (USB_OTG_FS) - USB_OTG_GlobalTypeDef *USBx; -#endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ @@ -144,10 +141,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); -#if defined (USB_OTG_FS) - USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) */ - if (hpcd->State == HAL_PCD_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -183,13 +176,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; -#if defined (USB_OTG_FS) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 8)) == 0U) - { - hpcd->Init.dma_enable = 0U; - } -#endif /* defined (USB_OTG_FS) */ + hpcd->Init.dma_enable = 0U; /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); @@ -201,8 +189,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) return HAL_ERROR; } - /* Force Device Mode*/ - (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) @@ -1930,7 +1922,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1945,7 +1937,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; #if defined (USB_OTG_FS) @@ -2322,9 +2314,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if (gSNPSiD == USB_OTG_CORE_ID_310A) @@ -2369,9 +2361,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if ((gSNPSiD > USB_OTG_CORE_ID_300A) && @@ -2501,7 +2493,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -2622,7 +2613,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2698,7 +2689,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2730,11 +2721,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2784,6 +2775,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2795,10 +2792,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2829,7 +2828,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2857,6 +2856,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2869,10 +2874,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2902,7 +2909,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2911,13 +2918,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - #endif /* defined (USB) */ /** @@ -2925,7 +2931,6 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, */ #endif /* defined (USB) || defined (USB_OTG_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pcd_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pcd_ex.c index 5d7a0bff4..94c487e5d 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pcd_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pcd_ex.c @@ -178,7 +178,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); USBx->GCCFG |= USB_OTG_GCCFG_PDEN; HAL_Delay(50U); @@ -470,7 +470,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -505,7 +504,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } - #endif /* defined (USB) */ /** diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pka.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pka.c index 101d091dc..be900a87c 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pka.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pka.c @@ -277,9 +277,9 @@ /** @defgroup PKA_Private_Functions PKA Private Functions * @{ */ -uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka); -HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart); -uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode); +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka); +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart); +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode); uint32_t PKA_GetBitSize_u8(uint32_t byteNumber); uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb); uint32_t PKA_GetBitSize_u32(uint32_t wordNumber); @@ -787,7 +787,6 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); } @@ -802,7 +801,6 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); } @@ -818,7 +816,6 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); } @@ -833,7 +830,6 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); } @@ -867,7 +863,6 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); } @@ -882,7 +877,6 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); } @@ -1059,7 +1053,6 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1074,7 +1067,6 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1571,12 +1563,11 @@ void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka) void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) { uint32_t mode = PKA_GetMode(hpka); - FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR); - FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR); - FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND); + uint32_t itsource = READ_REG(hpka->Instance->CR); + uint32_t flag = READ_REG(hpka->Instance->SR); /* Address error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET)) + if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR; @@ -1585,7 +1576,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* RAM access error interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET)) + if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR)) { hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR; @@ -1613,7 +1604,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) } /* End Of Operation interrupt occurred */ - if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET)) + if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND)) { /* Clear PROCEND flag */ __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND); @@ -1682,7 +1673,7 @@ __weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval HAL status */ -HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka) +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka) { /* Return PKA handle state */ return hpka->State; @@ -1693,7 +1684,7 @@ HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval PKA error code */ -uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka) +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka) { /* Return PKA handle error code */ return hpka->ErrorCode; @@ -1716,7 +1707,7 @@ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval Return the current mode */ -uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka) +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka) { /* return the shifted PKA_CR_MODE value */ return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); @@ -1729,7 +1720,7 @@ uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka) * @param Tickstart Tick start value * @retval HAL status */ -HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart) +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart) { /* Wait for the end of operation or timeout */ while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL) @@ -1752,7 +1743,7 @@ HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeo * @param mode PKA operating mode * @retval error code */ -uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode) +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode) { uint32_t err = HAL_PKA_ERROR_NONE; @@ -2109,6 +2100,8 @@ void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef * @brief Set input parameters. * @param hpka PKA handle * @param in Input information + * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash + * for example)the hash value should be written at the end of the buffer with zeros padding at beginning. */ void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in) { @@ -2321,7 +2314,6 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) } - /** * @brief Set input parameters. * @param hpka PKA handle @@ -2401,7 +2393,7 @@ void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in) /* Move the input parameters modulus value n to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL)); } /** diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pssi.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pssi.c index eb9c00d87..d6ef96fcb 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pssi.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_pssi.c @@ -53,7 +53,6 @@ (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API. - (#) For PSSI IO operations, two operation modes are available within this driver : *** Polling mode IO operation *** @@ -179,11 +178,12 @@ * @{ */ /* Private functions to handle DMA transfer */ +#if defined(HAL_DMA_MODULE_ENABLED) void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma); void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); void PSSI_DMAError(DMA_HandleTypeDef *hdma); void PSSI_DMAAbort(DMA_HandleTypeDef *hdma); - +#endif /*HAL_DMA_MODULE_ENABLED*/ /* Private functions to handle IT transfer */ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode); @@ -264,6 +264,7 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi) /* Allocate lock resource and initialize it */ hpssi->Lock = HAL_UNLOCKED; +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /* Init the PSSI Callback settings */ hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */ hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */ @@ -277,7 +278,10 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi) /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hpssi->MspInitCallback(hpssi); - +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_PSSI_MspInit(hpssi); +#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/ } hpssi->State = HAL_PSSI_STATE_BUSY; @@ -320,6 +324,7 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi) /* Disable the PSSI Peripheral Clock */ HAL_PSSI_DISABLE(hpssi); +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) if (hpssi->MspDeInitCallback == NULL) { hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ @@ -327,6 +332,10 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi) /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ hpssi->MspDeInitCallback(hpssi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_PSSI_MspDeInit(hpssi); +#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/ hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; hpssi->State = HAL_PSSI_STATE_RESET; @@ -369,6 +378,7 @@ __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi) */ } +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /** * @brief Register a User PSSI Callback * To be used instead of the weak predefined callback @@ -563,6 +573,7 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS return status; } +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} @@ -639,10 +650,13 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u HAL_PSSI_DISABLE(hpssi); /* Configure transfer parameters */ - hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL); + MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL), + (PSSI_CR_OUTEN_OUTPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL))); + +#if defined(HAL_DMA_MODULE_ENABLED) /* DMA Disable */ hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE; +#endif /*HAL_DMA_MODULE_ENABLED*/ /* Enable the selected PSSI peripheral */ HAL_PSSI_ENABLE(hpssi); @@ -696,7 +710,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u /* Increment Buffer pointer */ pbuffer++; transfer_size -= 2U; - } } else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS) @@ -722,7 +735,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u pbuffer++; transfer_size -= 4U; } - } else { @@ -758,7 +770,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u } } - /** * @brief Receives an amount of data in blocking mode. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -792,11 +803,13 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui /* Disable the selected PSSI peripheral */ HAL_PSSI_DISABLE(hpssi); /* Configure transfer parameters */ - hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL); + MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL), + (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL))); +#if defined(HAL_DMA_MODULE_ENABLED) /* DMA Disable */ hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE; +#endif /*HAL_DMA_MODULE_ENABLED*/ /* Enable the selected PSSI peripheral */ HAL_PSSI_ENABLE(hpssi); @@ -846,7 +859,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui *pbuffer = *dr; pbuffer++; transfer_size -= 2U; - } } else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS) @@ -871,7 +883,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui *pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR); pbuffer++; transfer_size -= 4U; - } } else @@ -892,7 +903,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui return HAL_ERROR; } - hpssi->State = HAL_PSSI_STATE_READY; /* Process Unlocked */ @@ -906,6 +916,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Transmit an amount of data in non-blocking mode with DMA * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -949,18 +960,18 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa { /* Configure BusWidth */ - if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) - { - MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, - PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)); - } - else - { - MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, - PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)); - } + if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + { + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)); + } + else + { + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)); + } /* Set the PSSI DMA transfer complete callback */ hpssi->hdmatx->XferCpltCallback = PSSI_DMATransmitCplt; @@ -992,8 +1003,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa if (dmaxferstatus == HAL_OK) { - - /* Update XferCount value */ hpssi->XferCount -= hpssi->XferSize; @@ -1038,7 +1047,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); } - return HAL_OK; } else @@ -1088,19 +1096,18 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat { if (hpssi->hdmarx != NULL) { - /* Configure BusWidth */ - if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) - { - MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); - } - else - { - MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, - PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); - } + if (hpssi->hdmarx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + { + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); + } + else + { + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); + } /* Set the PSSI DMA transfer complete callback */ hpssi->hdmarx->XferCpltCallback = PSSI_DMAReceiveCplt; @@ -1165,7 +1172,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat } else { - /* Process Unlocked */ __HAL_UNLOCK(hpssi); @@ -1181,8 +1187,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat } } - - /** * @brief Abort a DMA process communication with Interrupt. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -1191,7 +1195,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat */ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) { - /* Process Locked */ __HAL_LOCK(hpssi); @@ -1206,7 +1209,6 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) { if (hpssi->State == HAL_PSSI_STATE_BUSY_TX) { - hpssi->Instance->CR &= ~PSSI_CR_DMAEN; if (hpssi->hdmatx != NULL) @@ -1222,12 +1224,10 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); } } - } /* Abort DMA RX transfer if any */ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) { - hpssi->Instance->CR &= ~PSSI_CR_DMAEN; if (hpssi->hdmarx != NULL) @@ -1246,12 +1246,16 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) } else { + /* Call the error callback */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } } - /* Process Unlocked */ __HAL_UNLOCK(hpssi); @@ -1261,8 +1265,8 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); return HAL_OK; - } +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @} @@ -1284,13 +1288,12 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U) { /* Reset handle parameters */ - hpssi->XferCount = 0U; /* Disable all interrupts */ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); - +#if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA TX transfer if any */ if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN) { @@ -1317,7 +1320,6 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); } } - } /* Abort DMA RX transfer if any */ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) @@ -1346,10 +1348,15 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) } else { +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /* Call the corresponding callback to inform upper layer of the error */ hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } } +#endif /*HAL_DMA_MODULE_ENABLED*/ /* If state is an abort treatment on going, don't change state */ if (hpssi->State == HAL_PSSI_STATE_ABORT) @@ -1359,9 +1366,12 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) /* Process Unlocked */ __HAL_UNLOCK(hpssi); +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /* Call the corresponding callback to inform upper layer of End of Transfer */ hpssi->AbortCpltCallback(hpssi); - +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } else { @@ -1370,15 +1380,16 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) /* Process Unlocked */ __HAL_UNLOCK(hpssi); +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /* Call the corresponding callback to inform upper layer of End of Transfer */ hpssi->ErrorCallback(hpssi); - +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } - } } - /** * @brief Tx Transfer complete callback. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -1411,7 +1422,6 @@ __weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi) */ } - /** * @brief PSSI error callback. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -1469,20 +1479,19 @@ __weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi) * the configuration information for the specified PSSI. * @retval HAL state */ -HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi) +HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi) { /* Return PSSI handle state */ return hpssi->State; } - /** * @brief Return the PSSI error code. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains * the configuration information for the specified PSSI. * @retval PSSI Error Code */ -uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi) +uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi) { return hpssi->ErrorCode; } @@ -1507,9 +1516,7 @@ uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi) */ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) { - /* Reset handle parameters */ - hpssi->XferCount = 0U; /* Set new error code */ @@ -1518,7 +1525,7 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) /* Disable all interrupts */ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); - +#if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA TX transfer if any */ if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN) { @@ -1542,7 +1549,6 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); } } - } /* Abort DMA RX transfer if any */ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) @@ -1571,6 +1577,7 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) /*Nothing to do*/ } } +#endif /*HAL_DMA_MODULE_ENABLED*/ /* If state is an abort treatment on going, don't change state */ if (hpssi->State == HAL_PSSI_STATE_ABORT) @@ -1581,9 +1588,11 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->AbortCpltCallback(hpssi); - +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } else { @@ -1594,11 +1603,15 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->ErrorCallback(hpssi); - +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA PSSI slave transmit process complete callback. * @param hdma DMA handle @@ -1611,7 +1624,6 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma) uint32_t tmperror; - /* Disable Interrupts */ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); @@ -1633,12 +1645,12 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->TxCpltCallback(hpssi); - +#else + HAL_PSSI_TxCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } - - } /** @@ -1653,7 +1665,6 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) uint32_t tmperror; - /* Disable Interrupts */ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); @@ -1675,11 +1686,12 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->RxCpltCallback(hpssi); - +#else + HAL_PSSI_RxCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } - - } /** @@ -1703,16 +1715,23 @@ void PSSI_DMAAbort(DMA_HandleTypeDef *hdma) hpssi->State = HAL_PSSI_STATE_READY; /* Call the corresponding callback to inform upper layer of End of Transfer */ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->AbortCpltCallback(hpssi); - +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } else { /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } } +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @brief This function handles PSSI Communication Timeout. @@ -1746,6 +1765,8 @@ static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi } return HAL_OK; } + +#if defined(HAL_DMA_MODULE_ENABLED) void PSSI_DMAError(DMA_HandleTypeDef *hdma) { /* Derogation MISRAC2012-Rule-11.5 */ @@ -1753,7 +1774,6 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma) uint32_t tmperror; - /* Disable the selected PSSI peripheral */ HAL_PSSI_DISABLE(hpssi); @@ -1777,12 +1797,14 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->ErrorCallback(hpssi); - +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } - } - +#endif /*HAL_DMA_MODULE_ENABLED*/ /** diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_qspi.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_qspi.c index 4eb20ad22..44f35e133 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_qspi.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_qspi.c @@ -581,7 +581,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) #if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Clear Busy bit */ - HAL_QSPI_Abort_IT(hqspi); + (void)HAL_QSPI_Abort_IT(hqspi); #endif /* Change state of QSPI */ @@ -626,7 +626,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) #if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - HAL_QSPI_Abort_IT(hqspi); + (void)HAL_QSPI_Abort_IT(hqspi); #endif /* Change state of QSPI */ @@ -2255,7 +2255,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS * @param hqspi QSPI handle * @retval HAL state */ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) +HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) { /* Return QSPI handle state */ return hqspi->State; @@ -2266,7 +2266,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) * @param hqspi QSPI handle * @retval QSPI Error Code */ -uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) +uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) { return hqspi->ErrorCode; } @@ -2446,7 +2446,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ -uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) +uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) { return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); } @@ -2706,6 +2706,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2733,6 +2736,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } @@ -2767,6 +2773,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2796,6 +2805,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc.c index e5a52f81f..a4fe06f44 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc.c @@ -1854,7 +1854,11 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) /* MSI 8Mhz */ latency = FLASH_LATENCY_1; /* 1WS */ } - /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ + else + { + /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ + /* nothing to do */ + } } #endif } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc_ex.c index 738b417e3..6ab96aa46 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rcc_ex.c @@ -675,6 +675,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } + else + { + /* nothing to do */ + } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ @@ -2542,7 +2546,7 @@ void HAL_RCCEx_OCTOSPIDelayConfig(uint32_t Delay1, uint32_t Delay2) (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and sychronization frequencies values + directly reload value with target and synchronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. (+++) Configures CRS registers with synchronization configuration diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng.c index 52a92837b..bccf40f68 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng.c @@ -116,9 +116,9 @@ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x000CAA74U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x00007274U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} @@ -229,7 +229,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -272,12 +272,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng_ex.c index ec6096eb6..61d0317de 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -53,7 +53,7 @@ #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -65,11 +65,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -140,7 +140,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rtc_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rtc_ex.c index d13157fcf..3d52e1e68 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rtc_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_rtc_ex.c @@ -1930,7 +1930,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /* Clear the bits that are going to be configured and leave the others unchanged */ tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); - if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) { tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sai.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sai.c index eca1eca7c..87198fee7 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sai.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sai.c @@ -170,7 +170,7 @@ [..] Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. [..] @@ -185,10 +185,10 @@ [..] By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + reset to the legacy weak functions in the HAL_SAI_Init and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -205,7 +205,7 @@ [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ @@ -1451,6 +1451,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1470,12 +1476,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) (void) HAL_DMA_Abort(hsai->hdmarx); } - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1501,6 +1501,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1528,12 +1534,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - status = HAL_ERROR; - } - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sd.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sd.c index 626212619..a15f8f849 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sd.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sd.c @@ -461,6 +461,12 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) } #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Configure the bus wide with the specified value in the SD_HandleTypeDef */ + if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + /* Initialize the error code */ hsd->ErrorCode = HAL_SD_ERROR_NONE; @@ -3468,11 +3474,6 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) return errorstate; } -#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) - /* Configure SDMMC peripheral interface */ - (void)SDMMC_Init(hsd->Instance, hsd->Init); -#endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - /* All cards are initialized */ return HAL_SD_ERROR_NONE; } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smartcard.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smartcard.c index f871a470d..e0ca90869 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smartcard.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smartcard.c @@ -2524,7 +2524,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus.c index ec68cb2bf..cfbbcb2bb 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus.c @@ -2619,8 +2619,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus_ex.c index 5b66c80d0..56c79eb67 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_smbus_ex.c @@ -6,6 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions * ****************************************************************************** * @attention diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_spi.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_spi.c index 1474176a5..4875c0f02 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_spi.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -818,38 +820,35 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -922,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr ++; hspi->TxXferCount--; } @@ -941,13 +940,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -957,9 +956,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -984,19 +983,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1016,12 +1014,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1031,17 +1032,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1113,9 +1108,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1137,9 +1132,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1156,8 +1151,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1175,8 +1170,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1202,8 +1198,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1229,18 +1226,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1253,8 +1249,8 @@ error : * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1271,14 +1267,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1293,18 +1285,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1316,7 +1310,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1356,7 +1350,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1379,7 +1373,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1410,9 +1404,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1423,13 +1417,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -1454,13 +1448,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -1506,9 +1500,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1522,8 +1516,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -1548,8 +1543,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1565,30 +1561,32 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1599,9 +1597,8 @@ error : * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1609,14 +1606,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1625,7 +1620,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1673,8 +1668,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1687,13 +1681,15 @@ error : */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1704,12 +1700,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1781,8 +1771,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1794,11 +1783,11 @@ error : * @param Size amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1808,16 +1797,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1831,7 +1819,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1892,8 +1880,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1904,9 +1891,8 @@ error : * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1914,25 +1900,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1994,9 +1978,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2006,16 +1990,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2030,15 +2014,17 @@ error : */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -2055,12 +2041,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2138,9 +2118,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2150,16 +2130,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2172,12 +2152,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -2186,26 +2165,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -2214,7 +2192,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2305,9 +2283,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2326,9 +2304,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2337,16 +2315,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2439,7 +2418,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2472,7 +2452,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2727,9 +2708,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -3019,7 +3002,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3031,7 +3014,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3058,7 +3041,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3115,7 +3098,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3232,7 +3215,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3270,7 +3253,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3332,7 +3316,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3350,7 +3334,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3368,7 +3352,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3386,7 +3370,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3409,7 +3393,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3431,7 +3415,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3447,7 +3431,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3497,7 +3482,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3514,7 +3499,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3650,14 +3636,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in packing Bit mode */ if (hspi->TxXferCount >= 2U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3751,7 +3737,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3904,7 +3890,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3930,7 +3916,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -4032,7 +4018,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4387,7 +4373,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4430,7 +4417,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4459,7 +4447,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_spi_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_spi_ex.c index ad50589b8..241ff98a9 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_spi_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_spi_ex.c @@ -76,7 +76,7 @@ * the configuration information for the specified SPI module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) { __IO uint32_t tmpreg; uint8_t count = 0U; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sram.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sram.c index 81bf276a8..dccd6c499 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sram.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_sram.c @@ -1038,6 +1038,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1060,6 +1061,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1082,6 +1084,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim.c index f302ed1f4..2ce0df732 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim.c @@ -3842,7 +3842,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3874,7 +3874,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3904,7 +3904,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3934,7 +3934,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3964,7 +3964,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3973,11 +3973,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Break input event */ - if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -4003,7 +4004,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -4016,7 +4017,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4567,7 +4568,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -6970,6 +6972,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } } /** @@ -7094,7 +7103,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim_ex.c index d4c52fcbf..6ddded092 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_tim_ex.c @@ -837,7 +837,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1083,17 +1083,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1319,7 +1308,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2105,7 +2094,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2547,7 +2535,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2561,7 +2549,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2576,7 +2564,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2591,7 +2579,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -2742,15 +2730,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } else { /* nothing to do */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart.c index a3e3faa83..c5c33c7c3 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart.c @@ -999,10 +999,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -1013,9 +1010,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -1029,10 +1023,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -1043,8 +1034,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -2540,6 +2529,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3554,7 +3565,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) { @@ -4699,6 +4710,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4863,6 +4875,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart_ex.c index 39bdd6066..9d8a60a34 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_uart_ex.c @@ -629,7 +629,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_usart.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_usart.c index 71a3e41b3..2ed5c5302 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_usart.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -236,8 +236,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -249,7 +249,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -327,7 +327,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -672,11 +672,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -3030,7 +3029,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_usart_ex.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_usart_ex.c index 647c80eda..6314dab52 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_usart_ex.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_usart_ex.c @@ -373,7 +373,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_adc.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_adc.c index 8fde353e3..0244f02da 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_adc.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_adc.c @@ -465,11 +465,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Disable ADC instance if not already disabled. */ if (LL_ADC_IsEnabled(ADCx) == 1UL) { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - /* Stop potential ADC conversion on going on ADC group regular. */ if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { @@ -479,11 +474,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) } } - /* Set ADC group injected trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - /* Stop potential ADC conversion on going on ADC group injected. */ if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_comp.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_comp.c index c9b6f6a40..0a8711a04 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_comp.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_comp.c @@ -58,7 +58,7 @@ /* Note: On this STM32 series, comparator input plus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ +/* compatibility with other STM32 series. */ #if defined(COMP_CSR_INPSEL_1) #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ @@ -75,7 +75,7 @@ /* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ +/* compatibility with other STM32 series. */ #if defined(COMP_CSR_INMESEL_1) #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ @@ -92,7 +92,7 @@ ) #else #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_dma2d.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_dma2d.c index 3790c2499..41b56c912 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_dma2d.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_dma2d.c @@ -144,7 +144,7 @@ * - SUCCESS: DMA2D registers are de-initialized * - ERROR: DMA2D registers are not de-initialized */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx) { ErrorStatus status = SUCCESS; @@ -458,7 +458,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -502,7 +502,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -546,7 +546,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -590,7 +590,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_fmc.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_fmc.c index 32bd5f625..8fe8dc4eb 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_fmc.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_fmc.c @@ -59,7 +59,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) \ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -189,7 +189,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -397,7 +397,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -417,22 +417,24 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, /* Set FMC_NORSRAM device timing parameters */ #if defined(FMC_BTRx_DATAHLD) - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; #else /* FMC_BTRx_DATAHLD */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; #endif /* FMC_BTRx_DATAHLD */ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ @@ -459,7 +461,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -618,7 +620,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -651,7 +653,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -665,10 +667,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -682,7 +684,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -696,10 +698,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } @@ -803,7 +805,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -843,7 +845,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui #endif /* FMC_BANK3 */ - /** * @} */ diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_pka.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_pka.c index 910a62021..187b6df64 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_pka.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_pka.c @@ -84,7 +84,7 @@ * - SUCCESS: PKA registers are de-initialized * - ERROR: PKA registers are not de-initialized */ -ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx) +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx) { ErrorStatus status = SUCCESS; diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rcc.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rcc.c index f7f6d0849..36d724f17 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rcc.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rcc.c @@ -1284,7 +1284,7 @@ uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource) switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource)) { case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0UL) { swpmi_frequency = HSI_VALUE; } diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rng.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rng.c index 7fa1d7997..cdfcd300a 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rng.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_rng.c @@ -115,7 +115,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_spi.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_spi.c index 89cc53f83..bbc1e5482 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_spi.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_spi.c @@ -129,7 +129,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -178,8 +178,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_tim.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_tim.c index 1ce1776dd..9d7a8dd81 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_tim.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_tim.c @@ -66,8 +66,8 @@ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) @@ -733,6 +733,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -745,7 +746,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); if (IS_TIM_BKIN2_INSTANCE(TIMx)) @@ -796,8 +796,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -825,8 +823,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -875,8 +875,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -904,8 +902,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -954,8 +954,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -983,8 +981,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1033,8 +1033,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1062,7 +1060,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ @@ -1329,7 +1326,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_usb.c b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_usb.c index e50e78759..117c2ee65 100644 --- a/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_usb.c +++ b/stm32cube/stm32l4xx/drivers/src/stm32l4xx_ll_usb.c @@ -229,9 +229,9 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDe do { - HAL_Delay(1U); - ms++; - } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); } else if (mode == USB_DEVICE_MODE) { @@ -239,16 +239,16 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDe do { - HAL_Delay(1U); - ms++; - } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); } else { return HAL_ERROR; } - if (ms == 50U) + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) { return HAL_ERROR; } @@ -406,7 +406,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -420,7 +420,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -443,7 +443,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -457,7 +457,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -475,7 +475,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -490,7 +490,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) * This parameter can be one of these values: * @arg USBD_FS_SPEED: Full speed mode */ -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t speed; @@ -515,7 +515,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -553,7 +553,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -592,7 +592,7 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -639,7 +639,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -714,17 +714,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (pktcnt << 29)); + } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); @@ -815,7 +815,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; HAL_StatusTypeDef ret = HAL_OK; @@ -875,7 +875,7 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param len Number of bytes to write * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -903,7 +903,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, * @param len Number of bytes to read * @retval pointer to destination buffer */ -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t *pDest = dest; @@ -945,7 +945,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -976,7 +976,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1046,7 +1046,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1061,7 +1061,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1078,7 +1078,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1111,7 +1111,7 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) * @param chnum Channel number * @retval USB Channel Interrupt status */ -uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1127,7 +1127,7 @@ uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1143,7 +1143,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval USB Device IN EP interrupt status */ -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1161,7 +1161,7 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1179,7 +1179,7 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1213,7 +1213,7 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * 0 : Host * 1 : Device */ -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { return ((USBx->GINTSTS) & 0x1U); } @@ -1223,7 +1223,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1241,10 +1241,10 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); UNUSED(psetup); if (gSNPSiD > USB_OTG_CORE_ID_300A) @@ -1277,7 +1277,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1291,7 +1291,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { count++; - if (count > 200000U) + if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } @@ -1375,7 +1375,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1405,7 +1405,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1432,7 +1432,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * 1 : Activate VBUS * @retval HAL status */ -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) { uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0 = 0U; @@ -1730,7 +1730,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe * @param USBx Selected device * @retval HAL state */ -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1744,7 +1744,7 @@ uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; @@ -1828,7 +1828,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t chnum = (uint32_t)ch_num; @@ -1917,7 +1917,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1935,7 +1935,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2212,6 +2212,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -2316,7 +2320,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -2418,9 +2422,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -2452,19 +2456,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -2473,15 +2483,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -2492,18 +2500,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -2547,26 +2545,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/stm32cube/stm32l4xx/release_note.html b/stm32cube/stm32l4xx/release_note.html index 6b65db49d..2ee515d25 100644 --- a/stm32cube/stm32l4xx/release_note.html +++ b/stm32cube/stm32l4xx/release_note.html @@ -11,7 +11,7 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} - + @@ -70,12 +70,585 @@

Purpose

Update History

- +

Main Changes

Maintenance release of STM32CubeL4 Firmware package

  • General updates to fix known defects and implementation enhancements.
    • +
  • General fixes to support GCC12 in all STM32CubeIDE projects.
    • +
  • Upgrade USB Device Lib to use V2.11.3.
    • +
  • Upgrade USB Host Lib to use V3.5.2.
    • +
+

Contents

+
    +
  • HAL/LL Drivers updates +
      +
    • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
      • +
    • LL GENERIC update +
        +
      • Update LL_SYSCFG_SetEXTISource() and LL_SYSCFG_GetEXTISource() APIs to fix CodeSonar Type-Overrun violation.
        • +
      • +
    • LL ADC update +
        +
      • Remove useless action of conversion trigger change in LL_ADC_DeInit() API. Moreover, this action was not compliant with ADC enable state (cf reference manual).
        • +
      • +
    • HAL GPIO update +
        +
      • Replace GPIO_Pin_x with GPIO_PIN_x to be compliant with macros definition.
        • +
      • +
    • HAL/LL CORTEX update +
        +
      • Add missing parenthesis() in LL_MPU_ConfigRegion() API.
        • +
      • Updated HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
        • +
      • Add new HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion() APIs.
        • +
      • +
    • LL DMA update +
        +
      • Fix LL_DMA_SetPeriphRequest() and LL_DMA_GetPeriphRequest() to fix MISRAC2012-Rule-12.2 violation.
        • +
      • +
    • HAL DMA2D update +
        +
      • Fix incorrect word ‘surcharged’ in functions headers.
        • +
      • +
    • HAL RTC update +
        +
      • Complete the check on the tamper trigger configuration in HAL_RTCEx_SetTamper_IT() API to be the same as in HAL_RTCEx_SetTamper().
        • +
      • +
    • HAL HASH update +
        +
      • Code quality enhancement : Fix MISRAC Rules 12.1, 10.7, 10.6, 10.4
        • +
      • Read the last remaining bytes (3 or 2 or 1) of the data in a temporary variable (taking into account swap mode) and enter this variable into the HASH->DIN when the data is not a multiple of 4 bytes.
        • +
      • +
    • HAL IWDG update +
        +
      • Calculate the maximum IWDG Timeout period “HAL_IWDG_DEFAULT_TIMEOUT”, based on a Prescaler=128 at LSI frequency=32kHz (refer to the datasheet).
        • +
      • +
    • HAL PKA update +
        +
      • Remove multiple volatile reads or writes in interrupt handler for better performance.
        • +
      • +
    • HAL PSSI driver +
        +
      • Replace hdmatx by hdmarx in HAL_PSSI_Receive_DMA() API.
        • +
      • Use MODIFY_REG in HAL_PSSI_Transmit() and HAL_PSSI_Receive() APIs.
        • +
      • +
    • HAL/LL TIM update +
        +
      • Assert check for the right channels.
        • +
      • Fix typo in PWM symmetric mode related constants names
        • +
      • Update interrupt flag is cleared when the update event is generated by software.
        • +
      • Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init().
        • +
      • Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() API to fix Break Filter configuration problem with specific TIM instances.
        • +
      • Improve HAL TIM driver’s operational behavior.
        • +
      • Improve period configuration parameter check.
        • +
      • +
    • LL LPTIM update +
        +
      • Remove redundant macro IS_LPTIM_AUTORELOAD().
        • +
      • +
    • HAL/LL RNG update +
        +
      • Update the flag in the check if data register contains valid random data in HAL_RNG_Init() API.
        • +
      • Update the flag in new check to avoid false timeout detection in HAL_RNG_Init() API.
        • +
      • +
    • HAL OSPI update +
        +
      • Fix issue related to second XSPI instance management inside XSPIM. Second instance is wrongly deactivated in case of DQS not use.
        • +
      • +
    • HAL QSPI update +
        +
      • Clear AR register after CCR to avoid new transfer when address is not needed.
        • +
      • +
    • HAL CAN update +
        +
      • Clarify pin configuration in driver header by removing open-drain info.
        • +
      • +
    • HAL SAI update +
        +
      • Improve audio quality (avoid potential glitch).
        • +
      • Fix incorrect word ‘surcharged’ in functions headers.
        • +
      • +
    • HAL UART update +
        +
      • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback()/HAL_UART_UnRegisterRxEventCallback() APIs to allow user Rx Event Callback registration when a transmit is ongoing.
        • +
      • Avoid RTOF flag to be cleared by a transmit process in polling mode.
        • +
      • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() API use with Circular DMA, even if occurring just after TC event.
        • +
      • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.
        • +
      • Correct wrong comment in HAL_UARTEx_DisableFifoMode() API.
        • +
      • Ensure UART Rx buffer is not written beyond boundaries in case of RX FIFO reception in Interrupt mode.
        • +
      • +
    • LL LPUART update +
        +
      • Add LL LPUART API allowing TX FIFO flush request.
        • +
      • +
    • HAL USART driver +
        +
      • Align prescaler value used by default in macro USART_GET_DIV_FACTOR with Reference manual.
        • +
      • Correct wrong comment in HAL_USARTEx_DisableFifoMode() API.
        • +
      • Improve the visibility of the SPI mode support in HAL USART description.
        • +
      • +
    • HAL DSI update +
        +
      • Align DSI Initialization sequence to the recommended ‘Programing procedure overview’ part to avoid DSI read LCD controller register 0x0A error.
        • +
      • +
    • HAL/LL I2C update +
        +
      • Update I2C_Slave_ISR_IT(), I2C_Slave_ISR_DMA() and I2C_ITSlaveCplt() APIs to prevent the call of HAL_I2C_ListenCpltCallback() API twice.
        • +
      • Update I2C_WaitOnRXNEFlagUntilTimeout() to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.
        • +
      • Remove the unusable code in function HAL_I2C_IsDeviceReady() APIs.
        • +
      • Update I2C_WaitOnFlagUntilTimeout() to handle error case.
        • +
      • Update the HAL I2C driver to implement the errata workaround “Last-received byte loss in reload mode”.
        • +
      • Update HAL_I2C_Slave_Transmit() API to check if the received NACK is the good one.
        • +
      • Update LL_I2C_HandleTranfer() API to prevent undefined behavior of volatile usage before updating the CR2 register.
        • +
      • Add a temporary variable to get the value to check before comparison.
        • +
      • Add abort memory management to HAL_I2C_Master_Abort_IT() API.
        • +
      • Move the prefetch process in HAL_I2C_Slave_Transmit() API.
        • +
      • +
    • HAL SMBUS update +
        +
      • Update SMBUS IT processes to flush TXDR just in case of error.
        • +
      • +
    • HAL SDMMC update +
        +
      • Fix issue related to the SD Card initialization with 4-bit bus width.
        • +
      • +
    • HAL SPI update +
        +
      • Update HAL SPI driver to remove “got to” instruction and avoid misplaced __HAL_LOCK() API issue.
        • +
      • +
    • HAL/LL USB update +
        +
      • pcd.c/ll_usb.c: fix device connection in case battery charging used with HS instance linked to internal FS PHY.
        • +
      • ll_usb.c: increase timeout value to allow core reset to complete
        • +
      • ll_usb.c: improve delay management to set core mode.
        • +
      • +
    • LL UTILS update +
        +
      • Fix a note about Ticks parameter.
        • +
      • +
    • +
  • BSP +
      +
    • STM32L4R9I_EVAL and STM32L476G_EVAL +
        +
      • Update EEPROM_I2C_WritePage() API to add waiting EEPROM internal write cycle duration: Add 5ms max delay required by the M24M01 specification to ensure that the previous EEPROM access is finished.
        • +
      • +
    • STM32L496G-Discovery +
        +
      • Update to manage touch screen components (ft6x06 & ft3x67) available on different STM32L496G-Discovery board revisions in dynamic approach.
        • +
      • +
    • +
  • Middlewares +
      +
    • Upgrade USB Device Lib to use V2.11.3.
      • +
    • Upgrade USB Host Lib to use V3.5.2.
      • +
    • +
  • Projects updates +
      +
    • Examples_I2C +
        +
      • Fix wrong check condition on HAL_TIMEOUT: this value is no longer returned by the HAL_I2C_IsDeviceReady() API.
        • +
      • +
    • 32L496GDISCOVERY\Demonstrations +
        +
      • Add binary demo for 32L496GDISCOVERY Rev B06.
        • +
      • +
    • +
  • For the complete list of changes, please refer to the release notes of each firmware component
    • +
+

Components

+

Drivers

+ + + + + + + + + + + + + + + + + + + + + + + + + +
NameVersionRelease notes
CMSISV5.6.0release notes
STM32L4xx CMSISV1.7.4 release notes
STM32L4xx HALV1.13.5 release notes
+


+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameVersionRelease notes
BSP B-L4S5I-IOT01V1.0.2release notes
BSP B-L475E-IOT01V1.1.8release notes
BSP STM32L476G_EVALV2.1.8 release notes
BSP STM32L4R9I_EVALV1.1.3 release notes
BSP STM32L476G-DiscoveryV2.0.7release notes
BSP STM32L496G-DiscoveryV1.1.8 release notes
BSP STM32L4P5G-DiscoveryV1.1.2release notes
BSP STM32L4R9I-DiscoveryV1.1.2release notes
BSP STM32L4xx_NucleoV2.1.8release notes
BSP STM32L4xx_Nucleo_32V1.0.5release notes
BSP STM32L4xx_Nucleo_144V1.0.9release notes
+


+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameVersionRelease notes
BSP Adafruit Shield (reference ID 802)V3.0.6release notes
BSP CommonV5.1.2release notes
BSP cs42l51V1.0.1release notes
BSP cs43l22V2.0.4release notes
BSP cy8c4014lqiV1.0.0release notes
BSP ft3x67V1.0.1release notes
BSP ft6x06V1.0.3release notes
BSP ft5336V1.0.2release notes
BSP hts221V1.0.1release notes
BSP hx8347gV1.1.2release notes
BSP hx8347iV1.0.2release notes
BSP iss66wvh8m8V1.0.1release notes
BSP l3gd20V2.0.1release notes
BSP lis3mdlV1.0.1release notes
BSP lps22hbV1.0.1release notes
BSP ls016b8uyV1.0.1release notes
BSP lsm303cV2.0.1release notes
BSP lsm303dlhcV2.0.1release notes
BSP lsm6dslV1.0.1release notes
BSP m24srV1.1.1release notes
BSP mfxstm32l152V2.0.4release notes
BSP mx25lm51245gV1.0.1release notes
BSP mx25r6435fV1.0.1release notes
BSP n25q128aV1.0.2release notes
BSP n25q256aV1.0.1release notes
BSP ov9655V1.0.2release notes
BSP rk043fn48hV1.0.2release notes
BSP st25dvV1.0.0release notes
BSP st7735V1.1.5release notes
BSP st7789h2V1.1.4release notes
BSP stmpe811V2.0.2release notes
BSP stmpe1600V1.1.1release notes
BSP wm8994V2.3.1release notes
+


+

+

Middlewares

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameVersionRelease notes
STM32 USB Host LibraryV3.5.2 release notes
STM32 USB Device LibraryV2.11.3 release notes
STM32 TouchSensing LibraryV2.2.4release notes
FatFSR0.12cFatFS release notes ST modified 20191011 ST release notes
FreeRTOSV10.3.1FreeRTOS release notes ST modified 20200831 ST release notes
STemWinV5.44release notes
+


+

+

Utilities

+ + + + + + + + + + + + + + + + + + + + + + + + + +
NameVersionRelease notes
CPUV1.1.4release notes
FontsV1.0.3release notes
LogV1.0.4release notes
+


+

+

Known Limitations

+
    +
  • MDK-ARM projects are not provided for STM32L4R9I-EVAL demonstrations.
    • +
  • STM32L4R9I-EVAL STemWin MB1315 Demonstration is compatible only with IAR v7.80.4 version and below
    • +
  • The following projects are not supported with STM32CubeIDE toolchain (Debug and Release): +
      +
    • B-L475E-IOT01A/Applications/Proximity
      • +
    • B-L475E-IOT01A/Examples/BSP
      • +
    • NUCLEO-L476RG/Examples/FIREWALL/FIREWALL_VolatileData_Shared
      • +
    • NUCLEO-L496ZG/Examples/FIREWALL/FIREWALL_VolatileData_Shared
      • +
    • +
  • The following projects are not supported with STM32CubeIDE toolchain (Release): +
      +
    • 32L496GDISCOVERY/Examples/QSPI/QSPI_MemoryMapped
      • +
    • 32L496GDISCOVERY/Examples/QSPI/QSPI_PreInitConfig
      • +
    • +
  • The following projects are not supported with STM32CubeIDE toolchain (Debug): +
      +
    • NUCLEO-L4P5ZG/Examples/PWR/PWR_LPRUN_SRAM1
      • +
    • 32L4P5GDISCOVERY/Examples/HASH/HASH_HMAC_SHA224MD5_IT_DMA_Suspension
      • +
    • +
+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.32 minimum (ARM Compiler 5 (“AC5-like Warnings” selected)) +
      +
    • Note : MDK-ARM 5.38 comes by default with AC6 only. To use it with AC5, please follow the steps available in this AN: +
        +
      • https://developer.arm.com/documentation/ka005073/latest/
        • +
      • +
    • +
  • STM32CubeIDE v1.15.0
    • +
+
+
+
+ +
+

Main Changes

+

Maintenance release of STM32CubeL4 Firmware package

+
    +
  • General updates to fix known defects and implementation enhancements.
  • Deploy the support of STM32CubeIDE toolchain on all projects
    • SW4STM32 toolchain support is discontinued
      • @@ -83,7 +656,7 @@

      Maintenance release
    • Upgrade USB Device Lib to use V2.11.1.
    • Upgrade USB Host Lib to use V3.5.1.

    -

    Contents

    +

    Contents

    • CMSIS
        @@ -307,7 +880,7 @@

        Contents

      • For the complete list of changes, please refer to the release notes of each firmware component
      -

      Components

      +

      Components


      Drivers

      @@ -658,7 +1231,7 @@

      Components


      -

      Known Limitations

      +

      Known Limitations

      • MDK-ARM projects are not provided for STM32L4R9I-EVAL demonstrations.
      • STM32L4R9I-EVAL STemWin MB1315 Demonstration is compatible only with IAR v7.80.4 version and below
        • @@ -680,7 +1253,7 @@

        Known Limitations

      • 32L4P5GDISCOVERY/Examples/HASH/HASH_HMAC_SHA224MD5_IT_DMA_Suspension
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.4 + ST-Link
        @@ -697,8 +1270,8 @@

        Development Toolchains and Compile
        -

        Main Changes

        -

        Maintenance release of STM32CubeL4 Firmware package

        +

        Main Changes

        +

        Maintenance release of STM32CubeL4 Firmware package

        • Update of HAL/LL drivers to include latest corrections
            @@ -706,7 +1279,7 @@

            Maintenance relea

        • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers
        -

        Contents

        +

        Contents

        • HAL/LL Drivers updates
            @@ -791,7 +1364,7 @@

            Contents

            -

            Components

            +

            Components

            Drivers

            @@ -814,15 +1387,15 @@

            Components

            -

            Main Changes

            -

            Maintenance release of STM32CubeL4 Firmware package

            +

            Main Changes

            +

            Maintenance release of STM32CubeL4 Firmware package

            • Update of CMSIS and HAL/LL drivers to include latest corrections
            • Update of FW projects following changes in latest version of HAL/LL and Middlewares


            -

            Contents

            +

            Contents

            • CMSIS Device updates
                @@ -879,7 +1452,7 @@

                Contents

                The components flagged by “” have changed since the previous release. “” are new.


                -

                Components

                +

                Components

                The components flagged by “” have changed since the previous release. “” are new.


                @@ -1241,13 +1814,13 @@

                Components


            -

            Known Limitations

            +

            Known Limitations

            • SW4STM32 project is not provided for STM32L476G-EVAL demonstration.
            • MDK-ARM and SW4STM32 projects are not provided for STM32L4R9I-EVAL demonstrations.
            • STM32L4R9I-EVAL STemWin MB1315 Demonstration is compatible only with IAR v7.80.4 version and below
            -

            Development Toolchains and Compilers

            +

            Development Toolchains and Compilers

            • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.4 + ST-Link
                @@ -1299,15 +1872,15 @@

                Supported Devices and boards

                -

                Main Changes

                -

                Maintenance release of STM32CubeL4 Firmware package

                +

                Main Changes

                +

                Maintenance release of STM32CubeL4 Firmware package

                • Update of CMSIS and HAL/LL drivers to include latest corrections
                • Update of FW projects following changes in latest version of HAL/LL and Middlewares


                -

                Contents

                +

                Contents

                • CMSIS Device updates
                    @@ -1369,7 +1942,7 @@

                    Contents

                    The components flagged by “” have changed since the previous release. “” are new.


                    -

                    Components

                    +

                    Components

                    The components flagged by “” have changed since the previous release. “” are new.


                    @@ -1731,13 +2304,13 @@

                    Components


                    -

                    Known Limitations

                    +

                    Known Limitations

                    • SW4STM32 project is not provided for STM32L476G-EVAL demonstration.
                    • MDK-ARM and SW4STM32 projects are not provided for STM32L4R9I-EVAL demonstrations.
                    • STM32L4R9I-EVAL STemWin MB1315 Demonstration is compatible only with IAR v7.80.4 version and below
                    -

                    Development Toolchains and Compilers

                    +

                    Development Toolchains and Compilers

                    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.4 + ST-Link
                        @@ -1789,8 +2362,8 @@

                        Supported Devices and boards

                        -

                        Main Changes

                        -

                        Maintenance release of STM32CubeL4 Firmware package

                        +

                        Main Changes

                        +

                        Maintenance release of STM32CubeL4 Firmware package

                        • Update of CMSIS and HAL/LL drivers to include latest corrections
                            @@ -1800,7 +2373,7 @@

                            Maintenance relea


                          -

                          Contents

                          +

                          Contents

                          • CMSIS Core updates
                              @@ -1864,7 +2437,7 @@

                              Contents


                              -

                              Components

                              +

                              Components

                              Note: in the tables below, components in bold have changed since previous release

                              @@ -2216,13 +2789,13 @@

                              Components

                              Drivers


                              -

                              Known Limitations

                              +

                              Known Limitations

                              • SW4STM32 project is not provided for STM32L476G-EVAL demonstration.
                              • MDK-ARM and SW4STM32 projects are not provided for STM32L4R9I-EVAL demonstrations.
                              • STM32L4R9I-EVAL STemWin MB1315 Demonstration is compatible only with IAR v7.80.4 version and below
                              -

                              Development Toolchains and Compilers

                              +

                              Development Toolchains and Compilers

                              • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.4 + ST-Link
                                  @@ -2271,13 +2844,13 @@

                                  Supported Devices and boards

                                  -

                                  Main Changes

                                  +

                                  Main Changes

                                  Patch release of STM32CubeL4 Firmware package

                                  • Update of CMIS devices to add bits definitions in OCTOSPI registers
                                  • Update of HAL/LL drivers to include latest corrections of GPIO, I2C, RTC, SDMMC, UTILS drivers
                                  -

                                  Contents

                                  +

                                  Contents

                                  • CMSIS Device updates
                                      @@ -2316,7 +2889,7 @@

                                      Contents


                                      -

                                      Components

                                      +

                                      Components

                                      Note: in the tables below, components in bold have changed since previous release

                                      @@ -2641,13 +3214,13 @@

                                      Components

                                      Drivers


                                      -

                                      Known Limitations

                                      +

                                      Known Limitations

                                      • SW4STM32 project is not provided for STM32L476G-EVAL demonstration.
                                      • MDK-ARM and SW4STM32 projects are not provided for STM32L4R9I-EVAL demonstrations.
                                      • STM32L4R9I-EVAL STemWin MB1315 Demonstration is compatible only with IAR v7.80.4 version and below
                                      -

                                      Development Toolchains and Compilers

                                      +

                                      Development Toolchains and Compilers

                                      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3 + ST-Link
                                          @@ -2695,14 +3268,14 @@

                                          Supported Devices and boards

                                          -

                                          Main Changes

                                          +

                                          Main Changes

                                          Add support of STM32L4P5xx and STM32L4Q5xx devices

                                          • New PKA and PSSI peripherals
                                          • Updated PWR peripheral for finer SRAM2 retention in standby mode
                                          • Updated RNG peripheral to open entropy configuration
                                          -

                                          Contents

                                          +

                                          Contents

                                          • CMSIS Device updates
                                              @@ -2757,7 +3330,7 @@

                                              Contents


                                              -

                                              Components

                                              +

                                              Components

                                              Note: in the tables below, components in bold have changed since previous release

                                              @@ -3082,13 +3655,13 @@

                                              Components

                                              Drivers


                                              -

                                              Known Limitations

                                              +

                                              Known Limitations

                                              • SW4STM32 project is not provided for STM32L476G-EVAL demonstration.
                                              • MDK-ARM and SW4STM32 projects are not provided for STM32L4R9I-EVAL demonstrations.
                                              • STM32L4R9I-EVAL STemWin MB1315 Demonstration is compatible only with IAR v7.80.4 version and below
                                              -

                                              Development Toolchains and Compilers

                                              +

                                              Development Toolchains and Compilers

                                              • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3 + ST-Link
                                                  @@ -3134,13 +3707,13 @@

                                                  Supported Devices and boards

                                                  -

                                                  Main Changes

                                                  +

                                                  Main Changes

                                                  Maintenance release

                                                  • New HAL MMC driver release

                                                  • Demonstrations binaries are no more delivered within the STM32CubeL4 MCU package. They are available for download, in addition to their required media files if any, in a standalone package accessible through each hardware board official webpage. Please refer to the corresponding demonstration binary readme.txt to get webpage for each board.

                                                  -

                                                  Contents

                                                  +

                                                  Contents

                                                  • CMSIS Core updates
                                                      @@ -3199,7 +3772,7 @@

                                                      Contents


                                                    -

                                                    Components

                                                    +

                                                    Components

                                                    Note: in the tables below, components in bold have changed since previous release

                                                    @@ -3514,7 +4087,7 @@

                                                    Components

                                                    Drivers


                                                    -

                                                    Known Limitations

                                                    +

                                                    Known Limitations

                                                    • SW4STM32 project is not provided for STM32L476G-EVAL demonstration nor for NUCLEO-L412RB-P USB Device applications.
                                                    • MDK-ARM and SW4STM32 projects are not provided for STM32L4R9I-EVAL demonstrations.
                                                      • @@ -3522,7 +4095,7 @@

                                                      Known Limitations


                                                    -

                                                    Development Toolchains and Compilers

                                                    +

                                                    Development Toolchains and Compilers

                                                    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1 + ST-Link
                                                        @@ -3563,13 +4136,13 @@

                                                        Supported Devices and boards

                                                        -

                                                        Main Changes

                                                        +

                                                        Main Changes

                                                        Add support of STM32L412xx and STM32L422xx devices

                                                        • New RTC peripheral to improve power consumption performance
                                                        • Updated LPTIM peripheral to make both low power timer instances operational in Stop 2 mode
                                                        -

                                                        Contents

                                                        +

                                                        Contents

                                                        • CMSIS Device updates
                                                            @@ -3941,7 +4514,7 @@

                                                            Projects


                                                          -

                                                          Components

                                                          +

                                                          Components

                                                          Note: in the tables below, components in bold have changed since previous release

                                                          @@ -4231,7 +4804,7 @@

                                                          Components

                                                          Drivers


                                                          -

                                                          Known Limitations

                                                          +

                                                          Known Limitations

                                                          • SW4STM32 project is not provided for STM32L476G-EVAL demonstration nor for NUCLEO-L412RB-P USB Device applications
                                                          • MDK-ARM and SW4STM32 projects are not provided for STM32L4R9I-EVAL and STM32LR49I-Discovery demonstrations
                                                            • @@ -4239,7 +4812,7 @@

                                                            Known Limitations


                                                          -

                                                          Development Toolchains and Compilers

                                                          +

                                                          Development Toolchains and Compilers

                                                          • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link

                                                              @@ -4286,7 +4859,7 @@

                                                              Supported Devices and Boards

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              Maintenance release to add support of HAL callback registration feature

                                                              The feature disabled by default is available for the following HAL drivers:

                                                                @@ -4666,7 +5239,7 @@

                                                                Main Changes

                                                                -

                                                                Main Changes

                                                                +

                                                                Main Changes

                                                                Maintenance release to add support ofexternal SMPS PWR examples for NUCLEO-L4R5ZI-P (MB1312/S) board

                                                                Reduce package size by gathering all Demonstration media files under  "\Utilities\Media" folder

                                                                  @@ -5017,7 +5590,7 @@

                                                                  Main Changes

                                                                  -

                                                                  Main Changes

                                                                  +

                                                                  Main Changes

                                                                  Official release to support STM32L4R9I-EVAL (MB1313) and STM32L4R9I-Discovery (MB1311) boards

                                                                  • Maintenance release of CMSIS Device files, HAL and LL drivers
                                                                    • @@ -5361,7 +5934,7 @@

                                                                    Main Changes

                                                                    -

                                                                    Main Changes

                                                                    +

                                                                    Main Changes

                                                                    Official release to support STM32L4R5xx, STM32L4R7xx,STM32L4R9xx,STM32L4S5xx,STM32L4S7xxandSTM32L4S9xx devices

                                                                    • New DSI, OctoSPI (OSPI), GFXMMU and LTDC peripherals 
                                                                      • @@ -6022,7 +6595,7 @@

                                                                      Main Changes

                                                                      -

                                                                      Main Changes

                                                                      +

                                                                      Main Changes

                                                                      Add support of B-L475E-IOT01 board with project templates, examples and applications

                                                                      CMSIS Device updates

                                                                        @@ -6266,7 +6839,7 @@

                                                                        Main Changes

                                                                        -

                                                                        Main Changes

                                                                        +

                                                                        Main Changes

                                                                        Official release to support STM32L496xx and STM32L4A6xx devices

                                                                        • New DCMI, DMA2D, HASH peripherals 
                                                                          • @@ -6533,7 +7106,7 @@

                                                                          Main Changes

                                                                          -

                                                                          Main Changes

                                                                          +

                                                                          Main Changes

                                                                          Official release to support STM32L451xx, STM32L452xx and STM32L462xx devices

                                                                          CMSIS Device updates

                                                                            @@ -6734,7 +7307,7 @@

                                                                            Main Changes

                                                                            -

                                                                            Main Changes

                                                                            +

                                                                            Main Changes

                                                                            Patch release to fix issues in CMSIS Device STM32L4xx description files

                                                                            • Fix DAC_SR_BWST1 bit definition
                                                                              • @@ -6863,7 +7436,7 @@

                                                                              Main Changes

                                                                              -

                                                                              Main Changes

                                                                              +

                                                                              Main Changes

                                                                              Patch release to fix issues in

                                                                              HAL ADC driver

                                                                                @@ -6896,7 +7469,7 @@

                                                                                Main Changes

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                Maintenance release version for STM32L431/432/433/442/443/471/475/476/485/486 lines

                                                                                CMSIS Device

                                                                                  @@ -7120,7 +7693,7 @@

                                                                                  Main Changes

                                                                                  -

                                                                                  Main Changes

                                                                                  +

                                                                                  Main Changes

                                                                                  Official release to support STM32L431xx,STM32L432xx,STM32L433xx,STM32L442xx andSTM32L443xx devices

                                                                                  CMSIS Device

                                                                                    @@ -7260,7 +7833,7 @@

                                                                                    Main Changes

                                                                                    -

                                                                                    Main Changes

                                                                                    +

                                                                                    Main Changes

                                                                                    Update Low Layer drivers to add some new LL API(s) and minor changes  (release notes)

                                                                                    • Add initialization/de-initialization low level API(s) in new stm32l4xx_ll_ppp.c files (under USE_FULL_LL_DRIVER switch)
                                                                                      • @@ -7413,7 +7986,7 @@

                                                                                      Main Changes

                                                                                      -

                                                                                      Main Changes

                                                                                      +

                                                                                      Main Changes

                                                                                      Main HAL and LL Drivers updates  (release notes)

                                                                                      HAL PWR update (User application code impacted)

                                                                                        @@ -7577,7 +8150,7 @@

                                                                                        Main Changes

                                                                                        -

                                                                                        Main Changes

                                                                                        +

                                                                                        Main Changes

                                                                                        Patch release for all Examples/Applications/Demonstrations projects fine-tuning

                                                                                        • Set Flash prefetch off to match default system configuration (stm32l4xx_hal_conf.h files)
                                                                                          @@ -7613,7 +8186,7 @@

                                                                                          Main Changes

                                                                                          -

                                                                                          Main Changes

                                                                                          +

                                                                                          Main Changes

                                                                                          Add Low Layer drivers under Drivers\STM32L4xx_HAL_Driver

                                                                                          Low Layer drivers allow performance and memory footprint optimization

                                                                                            @@ -7750,7 +8323,7 @@

                                                                                            Main Changes

                                                                                            -

                                                                                            Main Changes

                                                                                            +

                                                                                            Main Changes

                                                                                            • First official release of STM32CubeL4 (STM32Cube for STM32L4 Series) 
                                                                                            diff --git a/stm32cube/stm32l4xx/soc/stm32l412xx.h b/stm32cube/stm32l4xx/soc/stm32l412xx.h index a61a714b2..5b35f36ef 100644 --- a/stm32cube/stm32l4xx/soc/stm32l412xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l412xx.h @@ -821,7 +821,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00008000UL) /*!< maximum SRAM1 size (up to 32 KBytes) */ #define SRAM2_SIZE (0x00002000UL) /*!< SRAM2 size (8 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x80U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l422xx.h b/stm32cube/stm32l4xx/soc/stm32l422xx.h index c1148d525..d42ce9559 100644 --- a/stm32cube/stm32l4xx/soc/stm32l422xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l422xx.h @@ -854,7 +854,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00008000UL) /*!< maximum SRAM1 size (up to 32 KBytes) */ #define SRAM2_SIZE (0x00002000UL) /*!< SRAM2 size (8 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x80U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l431xx.h b/stm32cube/stm32l4xx/soc/stm32l431xx.h index dee80375a..bd516b6ee 100644 --- a/stm32cube/stm32l4xx/soc/stm32l431xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l431xx.h @@ -934,7 +934,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ #define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l432xx.h b/stm32cube/stm32l4xx/soc/stm32l432xx.h index a1b324864..31bb55bae 100644 --- a/stm32cube/stm32l4xx/soc/stm32l432xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l432xx.h @@ -930,7 +930,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ #define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l433xx.h b/stm32cube/stm32l4xx/soc/stm32l433xx.h index 749d99e67..604f3d2fb 100644 --- a/stm32cube/stm32l4xx/soc/stm32l433xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l433xx.h @@ -988,7 +988,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ #define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l442xx.h b/stm32cube/stm32l4xx/soc/stm32l442xx.h index 0cd94c21c..3dbda3d46 100644 --- a/stm32cube/stm32l4xx/soc/stm32l442xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l442xx.h @@ -963,7 +963,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ #define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l443xx.h b/stm32cube/stm32l4xx/soc/stm32l443xx.h index bb91245bc..ab16789fe 100644 --- a/stm32cube/stm32l4xx/soc/stm32l443xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l443xx.h @@ -1021,7 +1021,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ #define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l451xx.h b/stm32cube/stm32l4xx/soc/stm32l451xx.h index 40c33f2a5..d628c3478 100644 --- a/stm32cube/stm32l4xx/soc/stm32l451xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l451xx.h @@ -954,7 +954,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00020000UL) /*!< maximum SRAM1 size (up to 128 KBytes) */ #define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l452xx.h b/stm32cube/stm32l4xx/soc/stm32l452xx.h index 5a878c116..d8c221a7c 100644 --- a/stm32cube/stm32l4xx/soc/stm32l452xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l452xx.h @@ -993,7 +993,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00020000UL) /*!< maximum SRAM1 size (up to 128 KBytes) */ #define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l462xx.h b/stm32cube/stm32l4xx/soc/stm32l462xx.h index 2124f2066..ff8667d0e 100644 --- a/stm32cube/stm32l4xx/soc/stm32l462xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l462xx.h @@ -1026,7 +1026,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00020000UL) /*!< maximum SRAM1 size (up to 128 KBytes) */ #define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l471xx.h b/stm32cube/stm32l4xx/soc/stm32l471xx.h index 2812114da..248e1fb1b 100644 --- a/stm32cube/stm32l4xx/soc/stm32l471xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l471xx.h @@ -1011,7 +1011,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ #define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l475xx.h b/stm32cube/stm32l4xx/soc/stm32l475xx.h index 6d90e548b..b85faa2f6 100644 --- a/stm32cube/stm32l4xx/soc/stm32l475xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l475xx.h @@ -1130,7 +1130,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ #define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l476xx.h b/stm32cube/stm32l4xx/soc/stm32l476xx.h index ace1e1fc2..283eff1db 100644 --- a/stm32cube/stm32l4xx/soc/stm32l476xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l476xx.h @@ -1145,7 +1145,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ #define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l485xx.h b/stm32cube/stm32l4xx/soc/stm32l485xx.h index e1769d760..3a353dbbe 100644 --- a/stm32cube/stm32l4xx/soc/stm32l485xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l485xx.h @@ -1163,7 +1163,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ #define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l486xx.h b/stm32cube/stm32l4xx/soc/stm32l486xx.h index 6c5ad60ec..5201a23ec 100644 --- a/stm32cube/stm32l4xx/soc/stm32l486xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l486xx.h @@ -1178,7 +1178,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ #define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l496xx.h b/stm32cube/stm32l4xx/soc/stm32l496xx.h index 623f5c7d9..123339ef1 100644 --- a/stm32cube/stm32l4xx/soc/stm32l496xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l496xx.h @@ -1218,7 +1218,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00040000UL) /*!< maximum SRAM1 size (up to 256 KBytes) */ #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4a6xx.h b/stm32cube/stm32l4xx/soc/stm32l4a6xx.h index dac4b60c9..1df49081c 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4a6xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4a6xx.h @@ -1276,7 +1276,7 @@ typedef struct #define SRAM1_SIZE_MAX (0x00040000UL) /*!< maximum SRAM1 size (up to 256 KBytes) */ #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4p5xx.h b/stm32cube/stm32l4xx/soc/stm32l4p5xx.h index bdb3c2514..cfbb3ce12 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4p5xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4p5xx.h @@ -1375,7 +1375,7 @@ typedef struct #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ #define SRAM3_SIZE (0x00020000UL) /*!< SRAM3 size (128 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4q5xx.h b/stm32cube/stm32l4xx/soc/stm32l4q5xx.h index 2ce919dfe..71b53345d 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4q5xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4q5xx.h @@ -1422,7 +1422,7 @@ typedef struct #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ #define SRAM3_SIZE (0x00020000UL) /*!< SRAM3 size (128 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4r5xx.h b/stm32cube/stm32l4xx/soc/stm32l4r5xx.h index 1cd82952b..c94d27b2c 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4r5xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4r5xx.h @@ -1249,7 +1249,7 @@ typedef struct #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ #define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4r7xx.h b/stm32cube/stm32l4xx/soc/stm32l4r7xx.h index 3f6133fac..7a02ddd1b 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4r7xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4r7xx.h @@ -1326,7 +1326,7 @@ typedef struct #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ #define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4r9xx.h b/stm32cube/stm32l4xx/soc/stm32l4r9xx.h index 716e619ec..51a3a47cd 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4r9xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4r9xx.h @@ -567,7 +567,7 @@ typedef struct uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ - __IO uint32_t VCCCR; /*!< DSI Host Video ChunksCurrent Configuration Register, Address offset: 0x140 */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ @@ -1406,7 +1406,7 @@ typedef struct #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ #define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4s5xx.h b/stm32cube/stm32l4xx/soc/stm32l4s5xx.h index 4ae1859d4..d7ffcac6b 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4s5xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4s5xx.h @@ -1307,7 +1307,7 @@ typedef struct #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ #define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4s7xx.h b/stm32cube/stm32l4xx/soc/stm32l4s7xx.h index 87be08d9b..863551371 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4s7xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4s7xx.h @@ -1384,7 +1384,7 @@ typedef struct #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ #define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4s9xx.h b/stm32cube/stm32l4xx/soc/stm32l4s9xx.h index 8e8516c44..cf9f98e40 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4s9xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4s9xx.h @@ -568,7 +568,7 @@ typedef struct uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ - __IO uint32_t VCCCR; /*!< DSI Host Video ChunksCurrent Configuration Register, Address offset: 0x140 */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ @@ -1464,7 +1464,7 @@ typedef struct #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ #define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) diff --git a/stm32cube/stm32l4xx/soc/stm32l4xx.h b/stm32cube/stm32l4xx/soc/stm32l4xx.h index 6ddf3bb06..ce3d29b29 100644 --- a/stm32cube/stm32l4xx/soc/stm32l4xx.h +++ b/stm32cube/stm32l4xx/soc/stm32l4xx.h @@ -106,7 +106,7 @@ */ #define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ #define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ From b556aeb85879724660c56147378ade9adb184d3b Mon Sep 17 00:00:00 2001 From: Abram Early Date: Fri, 6 Sep 2024 15:52:32 -0600 Subject: [PATCH 2/2] stm32cube: common_ll: Regeneration after cube updates Re - generate common_ll headers after Cube updates Signed-off-by: Abram Early --- stm32cube/common_ll/README.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stm32cube/common_ll/README.rst b/stm32cube/common_ll/README.rst index a5a9ffad7..a6566c28c 100644 --- a/stm32cube/common_ll/README.rst +++ b/stm32cube/common_ll/README.rst @@ -24,7 +24,7 @@ stm32h7rsxx 1.0.0 stm32h7xx 1.11.2 stm32l0xx 1.12.2 stm32l1xx 1.10.4 -stm32l4xx 1.18.0 +stm32l4xx 1.18.1 stm32l5xx 1.5.1 stm32mp1xx 1.6.0 stm32u0xx 1.1.0