dts: renesas: rx: Add dtc node support on RX26T

Add dtc property node on RX26T dts, and ram section for
dtc_vector_table on RX26T SoC for dtc support

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>

Author: quytranpzz

dts/rx/renesas/rx26t-common.dtsi

@@ -56,6 +56,13 @@
 		};
 	};
 
+	dtc: rx-dtc@82400 {
+		compatible = "renesas,rx-dtc";
+		reg = <0x00082400 0x1c>;
+		clocks = <&iclk MSTPA 28>;
+		status = "okay";
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -471,6 +478,7 @@
 			reg = <0x8A020 0x20>;
 			clocks = <&pclkb MSTPB 30>;
 			channel = <1>;
+			dtc = <&dtc>;
 			status = "disabled";
 
 			uart {
@@ -487,6 +495,7 @@
 					      <&group_irq_bl0 10 1>, <&group_irq_bl0 11 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			channel = <5>;
+			dtc = <&dtc>;
 			status = "disabled";
 
 			uart {
@@ -503,6 +512,7 @@
 			reg = <0x8A0C0 0x20>;
 			clocks = <&pclkb MSTPB 25>;
 			channel = <6>;
+			dtc = <&dtc>;
 			status = "disabled";
 
 			uart {
@@ -519,6 +529,7 @@
 			reg = <0x8B300 0x20>;
 			clocks = <&pclkb MSTPB 4>;
 			channel = <12>;
+			dtc = <&dtc>;
 			status = "disabled";
 
 			uart {

soc/renesas/rx/rx26t/CMakeLists.txt

@@ -8,5 +8,6 @@ zephyr_sources(
 )
 
 zephyr_linker_sources(SECTIONS ofsm.ld)
+zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/rx/linker.ld CACHE INTERNAL "")

soc/renesas/rx/rx26t/ram_sections.ld

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifdef CONFIG_RENESAS_RX_DTC
+SECTION_DATA_PROLOGUE(.dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+#endif