Skip to content

Latest commit

 

History

History
8 lines (6 loc) · 365 Bytes

File metadata and controls

8 lines (6 loc) · 365 Bytes

Architecture of Parallel Computers

Project 1: Accelerating Sorting in Graph Processing Adjacency Lists

Accelerate option: OpenMP, MPI, and Hybrid versions

Project 2: SMP simulator (shared multiprocessor simulator)

Configuration: 4 processor, each processor has 1 private L1 cache
Coherence protocol option: MSI, MESI, Dragon coherence protocol