From ca2a4287d4f0c4c6c85f1fff81c1aab8739752dd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joel=20H=C3=B6ner?= <athre0z@zyantific.com>
Date: Sat, 23 Apr 2022 22:56:53 +0200
Subject: [PATCH] Change `st0` operand visibility as specified by SDM

---
 Data/instructions.json | 904 ++++++++++++++++++++++-------------------
 1 file changed, 486 insertions(+), 418 deletions(-)

diff --git a/Data/instructions.json b/Data/instructions.json
index 302741f..c8a8dfd 100644
--- a/Data/instructions.json
+++ b/Data/instructions.json
@@ -16802,15 +16802,6 @@
       "modrm_reg": "0"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -16818,6 +16809,16 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -16882,15 +16883,6 @@
       "modrm_reg": "0"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -16898,6 +16890,16 @@
         "width16": 8,
         "width32": 8,
         "width64": 8
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -16963,21 +16965,22 @@
     },
     "operands": [
       {
-        "action": "write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
+        "operand_type": "mem",
+        "encoding": "modrm_rm",
+        "element_type": "bcd80",
         "width16": 10,
         "width32": 10,
         "width64": 10
       },
       {
-        "operand_type": "mem",
-        "encoding": "modrm_rm",
-        "element_type": "bcd80",
+        "action": "write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17017,7 +17020,8 @@
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17407,20 +17411,21 @@
     },
     "operands": [
       {
-        "operand_type": "implicit_reg",
-        "register": "st0",
+        "operand_type": "fpr",
+        "encoding": "modrm_rm",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
         "width64": 10
       },
       {
-        "operand_type": "fpr",
-        "encoding": "modrm_rm",
+        "operand_type": "implicit_reg",
+        "register": "st0",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17445,14 +17450,6 @@
       "modrm_reg": "2"
     },
     "operands": [
-      {
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -17460,6 +17457,15 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17485,20 +17491,21 @@
     },
     "operands": [
       {
-        "operand_type": "implicit_reg",
-        "register": "st0",
+        "operand_type": "fpr",
+        "encoding": "modrm_rm",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
         "width64": 10
       },
       {
-        "operand_type": "fpr",
-        "encoding": "modrm_rm",
+        "operand_type": "implicit_reg",
+        "register": "st0",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17523,14 +17530,6 @@
       "modrm_reg": "2"
     },
     "operands": [
-      {
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -17538,6 +17537,15 @@
         "width16": 8,
         "width32": 8,
         "width64": 8
+      },
+      {
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17647,20 +17655,21 @@
     },
     "operands": [
       {
-        "operand_type": "implicit_reg",
-        "register": "st0",
+        "operand_type": "fpr",
+        "encoding": "modrm_rm",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
         "width64": 10
       },
       {
-        "operand_type": "fpr",
-        "encoding": "modrm_rm",
+        "operand_type": "implicit_reg",
+        "register": "st0",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17685,14 +17694,6 @@
       "modrm_reg": "3"
     },
     "operands": [
-      {
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -17700,6 +17701,15 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17725,20 +17735,21 @@
     },
     "operands": [
       {
-        "operand_type": "implicit_reg",
-        "register": "st0",
+        "operand_type": "fpr",
+        "encoding": "modrm_rm",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
         "width64": 10
       },
       {
-        "operand_type": "fpr",
-        "encoding": "modrm_rm",
+        "operand_type": "implicit_reg",
+        "register": "st0",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17763,14 +17774,6 @@
       "modrm_reg": "3"
     },
     "operands": [
-      {
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -17778,6 +17781,15 @@
         "width16": 8,
         "width32": 8,
         "width64": 8
+      },
+      {
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17803,20 +17815,21 @@
     },
     "operands": [
       {
-        "operand_type": "implicit_reg",
-        "register": "st0",
+        "operand_type": "fpr",
+        "encoding": "modrm_rm",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
         "width64": 10
       },
       {
-        "operand_type": "fpr",
-        "encoding": "modrm_rm",
+        "operand_type": "implicit_reg",
+        "register": "st0",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -17994,15 +18007,6 @@
       "modrm_reg": "6"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18010,6 +18014,16 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18074,15 +18088,6 @@
       "modrm_reg": "6"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18090,6 +18095,16 @@
         "width16": 8,
         "width32": 8,
         "width64": 8
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18194,15 +18209,6 @@
       "modrm_reg": "7"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18210,6 +18216,16 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18274,15 +18290,6 @@
       "modrm_reg": "7"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18290,15 +18297,25 @@
         "width16": 8,
         "width32": 8,
         "width64": 8
-      }
-    ],
-    "meta_info": {
-      "category": "X87_ALU",
-      "extension": "X87",
-      "isa_set": "X87"
-    },
-    "affected_flags": {
-      "access": "must_write",
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
+      }
+    ],
+    "meta_info": {
+      "category": "X87_ALU",
+      "extension": "X87",
+      "isa_set": "X87"
+    },
+    "affected_flags": {
+      "access": "must_write",
       "c0": "u",
       "c1": "m",
       "c2": "u",
@@ -18445,15 +18462,6 @@
       "modrm_reg": "0"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18461,6 +18469,16 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18485,15 +18503,6 @@
       "modrm_reg": "0"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18501,6 +18510,16 @@
         "width16": 2,
         "width32": 2,
         "width64": 2
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18525,14 +18544,6 @@
       "modrm_reg": "2"
     },
     "operands": [
-      {
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18540,6 +18551,15 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18564,14 +18584,6 @@
       "modrm_reg": "2"
     },
     "operands": [
-      {
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18579,6 +18591,15 @@
         "width16": 2,
         "width32": 2,
         "width64": 2
+      },
+      {
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18603,14 +18624,6 @@
       "modrm_reg": "3"
     },
     "operands": [
-      {
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18618,6 +18631,15 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18642,14 +18664,6 @@
       "modrm_reg": "3"
     },
     "operands": [
-      {
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18657,6 +18671,15 @@
         "width16": 2,
         "width32": 2,
         "width64": 2
+      },
+      {
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18681,15 +18704,6 @@
       "modrm_reg": "6"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18697,6 +18711,16 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18721,15 +18745,6 @@
       "modrm_reg": "6"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18737,6 +18752,16 @@
         "width16": 2,
         "width32": 2,
         "width64": 2
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18761,15 +18786,6 @@
       "modrm_reg": "7"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18777,6 +18793,16 @@
         "width16": 4,
         "width32": 4,
         "width64": 4
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18801,15 +18827,6 @@
       "modrm_reg": "7"
     },
     "operands": [
-      {
-        "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
-        "element_type": "float80",
-        "width16": 10,
-        "width32": 10,
-        "width64": 10
-      },
       {
         "operand_type": "mem",
         "encoding": "modrm_rm",
@@ -18817,6 +18834,16 @@
         "width16": 2,
         "width32": 2,
         "width64": 2
+      },
+      {
+        "action": "read_write",
+        "operand_type": "implicit_reg",
+        "register": "st0",
+        "element_type": "float80",
+        "width16": 10,
+        "width32": 10,
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -18841,15 +18868,6 @@
       "modrm_reg": "0"
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+        "operand_type": "implicit_reg",
+        "register": "st0",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {
@@ -22144,8 +22211,8 @@
     "operands": [
       {
         "action": "read_write",
-        "operand_type": "implicit_reg",
-        "register": "st0",
+        "operand_type": "fpr",
+        "encoding": "modrm_rm",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
@@ -22153,12 +22220,13 @@
       },
       {
         "action": "read_write",
-        "operand_type": "fpr",
-        "encoding": "modrm_rm",
+        "operand_type": "implicit_reg",
+        "register": "st0",
         "element_type": "float80",
         "width16": 10,
         "width32": 10,
-        "width64": 10
+        "width64": 10,
+        "visible": false
       }
     ],
     "meta_info": {