Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
build		build
toolchain		toolchain
verilog		verilog
xilinx		xilinx
.gitignore		.gitignore
LICENSE		LICENSE
Makefile		Makefile
README.md		README.md
go		go
sim_main.cpp		sim_main.cpp

Repository files navigation

j1

The J1 CPU

About

The J1 CPU

j1-cpu

BSD-3-Clause license

Custom properties

Report repository

Languages

Forth 43.7%
Verilog 31.6%
Makefile 14.8%
Python 6.3%
C++ 3.5%
C 0.1%