GitHub - 3E5F/Verilog_SimpleCalculator: Simple calculator written in Verilog

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ALUFile.v		ALUFile.v
ASM_Chart.png		ASM_Chart.png
CompleteCalculator.ucf		CompleteCalculator.ucf
CompleteCalculator_clkCtrl.ucf		CompleteCalculator_clkCtrl.ucf
ControlUnitTable.png		ControlUnitTable.png
DesignLayout_BlockDiagram.png		DesignLayout_BlockDiagram.png
Encase_Level.ucf		Encase_Level.ucf
Encase_Level.v		Encase_Level.v
FSM_file.v		FSM_file.v
README.txt		README.txt
calc_tb.v		calc_tb.v
calc_toplevel.v		calc_toplevel.v
datapath_toplevel.v		datapath_toplevel.v
mux_1.v		mux_1.v
mux_2.v		mux_2.v
registerFile.v		registerFile.v

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FPGA Verilog code for a small calculator.
Capable of performing ADD, SUBTRACT, AND, and XOR operations.

1) Look at the diagrams to know the layouts of the modules.