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lpc4322_hic: clock enhancements #925

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887c9fb
lpc43xx_hic: remove lpc43xx_cgu.{c|h}
Jan 9, 2022
5ea882a
lpc43xx_hic,uart: replace CGU code with direct register setup
Jan 9, 2022
f1315ba
lpc43xx_hic,system: extract N setup as ndec_new
Jan 9, 2022
ca753ed
lpc43xx_hic,system: extract P setup as pdec_new
Jan 9, 2022
abcbeec
lpc43xx_hic,system: extract M setup as mdec_new
Jan 9, 2022
dd0bb84
lpc43xx_hic,system: extract SELI setup as anadeci_new
Jan 9, 2022
cd0f4ae
lpc43xx_hic,system: extract SELI setup as anadecp_new
Jan 9, 2022
0885a2d
lpc43xx_hic,system: make use of WaitUs
Jan 9, 2022
a3e0b08
lpc43xx_hic,system: use defines where possible
Jan 9, 2022
3026c65
lpc43xx_hic,system: Enable USB0 PHY power
Jan 9, 2022
88d4bda
lpc43xx_hic,board: remove CGU code
Jan 9, 2022
422c5cc
lp43xx: use Driver_USART0 for virtual com port
Feb 15, 2022
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6 changes: 3 additions & 3 deletions source/hic_hal/nxp/lpc4322/RTE_Device.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1010,12 +1010,12 @@
// </e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]

// <e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
#define RTE_USART0 0
#define RTE_USART0 1

// <h> Pin Configuration
// <o> TX <0=>Not used <1=>P2_0 <2=>P6_4 <3=>P9_5 <4=>PF_10
// <i> USART0 Serial Output pin
#define RTE_USART0_TX_ID 0
#define RTE_USART0_TX_ID 1
#if (RTE_USART0_TX_ID == 0)
#define RTE_USART0_TX_PIN_EN 0
#elif (RTE_USART0_TX_ID == 1)
Expand All @@ -1042,7 +1042,7 @@
#endif
// <o> RX <0=>Not used <1=>P2_1 <2=>P6_5 <3=>P9_6 <4=>PF_11
// <i> USART0 Serial Input pin
#define RTE_USART0_RX_ID 0
#define RTE_USART0_RX_ID 1
#if (RTE_USART0_RX_ID == 0)
#define RTE_USART0_RX_PIN_EN 0
#elif (RTE_USART0_RX_ID == 1)
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17 changes: 0 additions & 17 deletions source/hic_hal/nxp/lpc4322/board_LPC43xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,24 +20,7 @@
*/

#include "sdk.h"
#include "lpc43xx_cgu.h"

void sdk_init(void)
{
/* Set core clock to 120MHz */
CGU_Init(120000000);
/* Set up USB0 clock */
/* Disable PLL first */
CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE);

/* the usb core require output clock = 480MHz */
if (CGU_SetPLL0() != CGU_ERROR_SUCCESS) {
while (1);
}

CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
/* Enable PLL after all setting is done */
CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE);
/* Turn on the USB0PHY */
LPC_CREG->CREG0 &= ~(1 << 5);
}
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