Updated trademarks (Xilinx#157)

* Update README.md * Update README.md Updated Trademarks * Update README.md * Updated trademarks Co-authored-by: Shubhekshana <81768495+Shubhekshana@users.noreply.github.com>
AlexandreZhdanov · Dec 21, 2021 · 15023d7 · 15023d7
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diff --git a/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/README.md b/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/README.md
@@ -1,4 +1,4 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
     <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
@@ -7,7 +7,7 @@
  </tr>
 </table>
 
-# Versal™ AI Engine LeNet Tutorial
+# Versal® AI Engine LeNet Tutorial
 
 ***Version: Vitis 2021.2***
 

diff --git a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/README.md b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/README.md
@@ -14,7 +14,7 @@
 
 ## Introduction
 
-Versal™ ACAP AI Core Series are heterogeneous devices containing many domains with compute capabilities. With respect to Digital Signal Processing (DSP), and particularly Finite Impulse Response (FIR) filters, the two domains of interest are:
+Versal® ACAP AI Core Series are heterogeneous devices containing many domains with compute capabilities. With respect to Digital Signal Processing (DSP), and particularly Finite Impulse Response (FIR) filters, the two domains of interest are:
 
 - The Programmable Logic (PL) which is the "classical" domain of Xilinx devices
 - The AI Engine Processor Array which is a new domain within Versal ACAP Xilinx devices
@@ -69,7 +69,7 @@ This tutorial is decomposed into multiple steps:
 
 You should have already read the [AI Engine Detailed Architecture](https://www.xilinx.com/support/documentation/architecture-manuals/am009-versal-ai-engine.pdf), so the purpose of this chapter is simply to highlight the features of the AI Engine that will be useful for this tutorial.
 
-Versal™ Adaptive Compute Acceleration Platforms (ACAPs) combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application.
+Versal® Adaptive Compute Acceleration Platforms (ACAPs) combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application.
 
 ![missing image](./Images/Versal.jpg)
 

diff --git a/...esign_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md b/...esign_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md
@@ -1,4 +1,4 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
     <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
@@ -9,7 +9,7 @@
 
 # Introduction: Packaging and Running the System  
 
-After the AI Engine graph is compiled and linked with the PL kernels, the PS application is compiled, and all the required outputs are generated, the next step in the build process is to package the required files to configure and boot the Versal™ device. This requires the use of the Vitis™ compiler ``--package`` command. For Versal ACAPs, the programmable device image (PDI) file is used to boot and program the hardware device.
+After the AI Engine graph is compiled and linked with the PL kernels, the PS application is compiled, and all the required outputs are generated, the next step in the build process is to package the required files to configure and boot the Versal® device. This requires the use of the Vitis™ compiler ``--package`` command. For Versal ACAPs, the programmable device image (PDI) file is used to boot and program the hardware device.
 
 In this module, you will package the bare-metal system to generate the final bootable image (PDI) for running hardware emulation and for running it on the VCK190 board. Refer to [AI Engine Documentation: Packaging](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/integrate_ai_engine_application.html#ariaid-title8) for more details on this packaging process.
 

diff --git a/...ngine_Development/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md b/...ngine_Development/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md
@@ -1,4 +1,4 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
     <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
@@ -155,7 +155,7 @@ Build the PetaLinux system image with the following command:
 petalinux-build -p build/vck190_linux
 ```
 
-This step generates a device tree DTB file, platform loader and manager firmware (PLM), processing system management firmware (PSM), Arm™ trusted firmware (ATF), U-Boot, the Linux kernel, a root file system image, and the boot script for a Versal™ ACAP. Finally, it generates the necessary boot images. The compilation progress shows on the console when executing this command.  
+This step generates a device tree DTB file, platform loader and manager firmware (PLM), processing system management firmware (PSM), Arm™ trusted firmware (ATF), U-Boot, the Linux kernel, a root file system image, and the boot script for a Versal® ACAP. Finally, it generates the necessary boot images. The compilation progress shows on the console when executing this command.  
 
 When the build finishes, the generated U-Boot and Linux images are stored in the ``build/vck190_petalinux/images/linux`` directory.
 

diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/README.md
@@ -1,4 +1,4 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
     <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
@@ -13,7 +13,7 @@
 
 ## Introduction
 
-The Versal™ adaptive compute acceleration platform (ACAP) is a fully software programmable, heterogeneous compute platform that combines the processing system (PS) (Scalar Engines that include Arm™ processors), programmable logic (PL) (Adaptable Engines that include the programmable logic), and AI Engines which belong in the Intelligent Engine category.
+The Versal® adaptive compute acceleration platform (ACAP) is a fully software programmable, heterogeneous compute platform that combines the processing system (PS) (Scalar Engines that include Arm™ processors), programmable logic (PL) (Adaptable Engines that include the programmable logic), and AI Engines which belong in the Intelligent Engine category.
 
 This tutorial demonstrates the creation of a beamforming system running on the AI Engine, PL, and PS, and the validation of the design running on this heterogeneous domain.
 

diff --git a/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/README.md b/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>

diff --git a/AI_Engine_Development/Design_Tutorials/06-fft2d_AIEvsHLS/README.md b/AI_Engine_Development/Design_Tutorials/06-fft2d_AIEvsHLS/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>
@@ -27,7 +27,7 @@
 
 # Introduction
 
-The Versal™ ACAP is a a fully software programmable, heterogeneous compute platform that combines the following:
+The Versal® ACAP is a a fully software programmable, heterogeneous compute platform that combines the following:
 
 - Scalar Engines (a processor subsystem (PS) that includes Arm® processors)
 - Adaptable Engines (programmable logic (PL) and memory)

diff --git a/AI_Engine_Development/Design_Tutorials/07-firFilter_AIEvsHLS/README.md b/AI_Engine_Development/Design_Tutorials/07-firFilter_AIEvsHLS/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>
@@ -29,7 +29,7 @@
 [Revision History](#revision-history)
 
 # Introduction
-The Xilinx® Versal™ adaptive compute acceleration platform (ACAP) is a fully software-programmable, heterogeneous compute platform that combines the processor system (PS) (Scalar Engines that include the Arm® processors), programmable logic (PL) (Adaptable Engines that include the programmable logic blocks and memory) and the Intelligent Engines comprising of both the AI and DSP Engines.
+The Xilinx® Versal® adaptive compute acceleration platform (ACAP) is a fully software-programmable, heterogeneous compute platform that combines the processor system (PS) (Scalar Engines that include the Arm® processors), programmable logic (PL) (Adaptable Engines that include the programmable logic blocks and memory) and the Intelligent Engines comprising of both the AI and DSP Engines.
 
 This tutorial is one of several to perform two implementations of a system-level design using AI Engines and HLS with DSP Engines in the Versal device plus PL including LUTs, flip-flops (FFs), and block RAMs. In each implementation, the tutorial takes you through hardware emulation and hardware flow in the context of a complete Versal ACAP system design. A makefile is provided so that you can modify it to suit your needs in a different context.
 

diff --git a/...evelopment/Design_Tutorials/08-n-body-simulator/Module_01_python_sims/README.md b/...evelopment/Design_Tutorials/08-n-body-simulator/Module_01_python_sims/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>

diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>

diff --git a/...Development/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md b/...Development/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>

diff --git a/...ent/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md b/...ent/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>

diff --git a/...ent/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md b/...ent/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>

diff --git a/...ne_Development/Design_Tutorials/08-n-body-simulator/Module_07_results/README.md b/...ne_Development/Design_Tutorials/08-n-body-simulator/Module_07_results/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>

diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/README.md
@@ -1,6 +1,6 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal™ ACAP AI Engine Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>Versal® ACAP AI Engine Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
     </td>

diff --git a/AI_Engine_Development/Design_Tutorials/09-post-link-recompile/README.md b/AI_Engine_Development/Design_Tutorials/09-post-link-recompile/README.md
@@ -1,4 +1,4 @@
-<table>
+<table>
  <tr>
    <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>Post-Link Recompile of an AI Engine Application</h1>
    </td>
@@ -24,7 +24,7 @@ This tutorial requires a number of tools and files to be installed:
 
 * Download and install the Vitis™ software platform from [here](https://www.xilinx.com/support/download.html). See the installation instructions [here](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration).
 * Download and install the Vitis Embedded Base Platform [VCK190](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html).
-* Download and install the [common image](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html) for embedded Vitis platforms for Versal™ ACAP.
+* Download and install the [common image](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html) for embedded Vitis platforms for Versal® ACAP.
 
 The AI Engine development documentation is also available [here](https://docs.xilinx.com/search/all?filters=Document_ID~%2522UG1076%2522_%2522UG1079%2522&content-lang=en-US).
 

diff --git a/AI_Engine_Development/Feature_Tutorials/05-AI-engine-versal-integration/README.md b/AI_Engine_Development/Feature_Tutorials/05-AI-engine-versal-integration/README.md
@@ -1,4 +1,4 @@
-<table class="sphinxhide" width="100%">
+<table class="sphinxhide" width="100%">
  <tr width="100%">
     <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
@@ -13,7 +13,7 @@
 
 ## Introduction
 
-Versal™ adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application.
+Versal® adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application.
 
 This tutorial demonstrates creating a system design running on the AI Engine, PS, and Programmable logic. The AI Engine domain contains a simple graph consisting of 3 kernels. These kernels are connected by both windows and streams. The PL domain contains data movers that provide input and capture output from the AI Engine. The PS domain contains a host application that controls the entire system. You'll validate the design running on these heterogeneous domains by first emulating the hardware and then running on actual hardware. 
 

diff --git a/...velopment/Feature_Tutorials/06-versal-system-design-clocking-tutorial/README.md b/...velopment/Feature_Tutorials/06-versal-system-design-clocking-tutorial/README.md
@@ -2,7 +2,7 @@
  <tr width="100%">
     <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>AI Engine Development</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
-    <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis-AI™ Development Environment on xilinx.com</a>
+    <a href="https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html">See Vitis AI Development Environment on xilinx.com</a>
     </td>
  </tr>
 </table>

diff --git a/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md b/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md
@@ -20,7 +20,7 @@ The purpose of this set of examples is to understand floating-point vector compu
 
 Before starting to explore these examples, refer to the following documents:
 
-- Versal™ ACAP AI Engine architecture documentation
+- Versal® ACAP AI Engine architecture documentation
   - **[AI Engine Architecture](https://www.xilinx.com/support/documentation/architecture-manuals/am009-versal-ai-engine.pdf)**
   - **[Versal ACAP AI Engines for Dummies](https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Versal-ACAP-AI-Engines-for-Dummies/ba-p/1132493)**
   - **[Architecture Details Summary](Details.md)**