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Achievement: QuickdrawAchievement: Pull Shark

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Ali-975/README.md

⚡ RTL Design & Verification Engineer ⚡

Exploring the world of RTL Design, FPGA Prototyping, and ASIC Flows. Proficient in SystemVerilog, Verilog, RISC-V Assembly, and C++, I love bringing silicon ideas to life with SystemVerilog, RISC-V, and FPGA tools.

Profile views Followers

  • 🔭 I’m currently working on RISC-V SoC Design, Verification & FPGA Prototyping

  • 🌱 Learning SystemVerilog | UVM | ASIC Physical Design

  • 👯 Open to collaborate on RISC-V & Custom EDA Projects

  • 💬 Ask me about RTL, FPGA, Verilog, SystemVerilog

  • 📫 Reach me at muddassiraliofficial@gmail.com

【C O N N E C T】



LinkedIn Gmail GitHub

【L A N G U A G E S & T O O L S】

【S T A T S】



GitHub Stats

GitHub Streak 		Top Languages

Ali-975

【G R A P H】



𝚐𝚒𝚝𝚑𝚞𝚋 𝚐𝚛𝚊𝚙𝚑


【A C T I V I T Y】





【Q U O T E S】

Quotes

github contribution grid snake animation

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  1. DV_Training_NCDC DV_Training_NCDC Public

    Design Verification (DV) Engineer Training at NCDC, Islamabad — covering C programming, Assembly, RISC-V ISA, SystemVerilog, Computer Architecture, UVM Methodology, and other verification concepts.

    Tcl

  2. GSoC_24-Final-Submission-Report GSoC_24-Final-Submission-Report Public

    This repository contains the final report for my Google Summer of Code (GSoC) 2024 project with Chips Alliance. The project involved implementing a GDS reader/writer in OpenROAD using OpenDB. The r…

    1

  3. merledu/rv-thunder merledu/rv-thunder Public

    RISC-V 32-bit CPU written in amaranth (python-lib)

    Verilog 11 5

  4. sscs-ose/sscs-ose-code-a-chip.github.io sscs-ose/sscs-ose-code-a-chip.github.io Public

    IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)

    Jupyter Notebook 188 100

  5. VGA-controller VGA-controller Public

    Forked from Abdul-muheet-ghani/VGA-controller

    Basics of VGA, Graphics of screen, Image and Video formation...

    F# 1

  6. OpenLane OpenLane Public

    Forked from The-OpenROAD-Project/OpenLane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Python 1