Upload Lab 5 materials

lab5/bench.sv

@@ -0,0 +1,121 @@
+`include "src/top.sv"
+`include "src/utils.sv"
+
+module bench();
+
+	timeunit 10ns;
+	timeprecision 1ns;
+
+	logic Run = 1, Continue = 1, Clk = 0;
+	logic [9:0] SW, LED;
+	`TOGGLE_INTERNAL
+	logic [15:0] hexval, R0, R1, R2, R3, R4, R5, R6, R7;
+
+	assign R0 = REG[0];
+	assign R1 = REG[1];
+	assign R2 = REG[2];
+	assign R3 = REG[3];
+	assign R4 = REG[4];
+	assign R5 = REG[5];
+	assign R6 = REG[6];
+	assign R7 = REG[7];
+
+	SLC3TopSim subject(.*);
+
+`define NUM1  10'h3EC
+`define NUM2  10'h0EB
+`define NUM3  10'h2CA
+`define NUM4  10'h1FE
+`define TICK  #80
+`define RUN   `TICK Run = 0; `TICK Run = 1;
+`define CONT  `TICK Continue = 0; `TICK Continue = 1;
+`define RESET `TICK Run = 0; Continue = 0; `TICK Run = 1; Continue = 1;
+`define SETSW(val) `TICK SW = val;
+
+	initial begin: CLOCK_INIT
+		Clk = 0;
+	end
+
+	always begin: CLOCK_GEN
+		#1 Clk = ~Clk;
+	end
+
+	initial begin: TEST_VECT
+
+`ifdef FETCH_DEMO
+
+		`RESET
+		`RUN
+		for (int i = 0; i < 80; i++) begin
+			`CONT
+		end
+
+`else
+
+		// I/O 1
+		`RESET
+		`SETSW(10'h03)
+		`RUN
+		`SETSW(`NUM1)
+		`SETSW(`NUM2)
+		`SETSW(`NUM3)
+		`SETSW(`NUM4)
+
+		// I/O 2
+		`RESET
+		`SETSW(10'h06)
+		`RUN
+		`SETSW(`NUM1) `CONT
+		`SETSW(`NUM2) `CONT
+		`SETSW(`NUM3) `CONT
+		`SETSW(`NUM4) `CONT
+
+		// Self-mod
+		`RESET
+		`SETSW(10'h0B)
+		`RUN
+		for (int i = 0; i < 16; i++) begin
+			`CONT
+		end
+
+		// XOR
+		`RESET
+		`SETSW(10'h14)
+		`RUN
+		`SETSW(`NUM1) `CONT
+		`SETSW(`NUM2) `CONT
+		`CONT
+		`SETSW(`NUM3) `CONT
+		`SETSW(`NUM4) `CONT
+		`CONT
+
+		// Mult
+		`RESET
+		`SETSW(10'h31)
+		`RUN
+		`SETSW(`NUM1) `CONT
+		`SETSW(`NUM2) `CONT
+		`TICK `CONT
+		`SETSW(`NUM3) `CONT
+		`SETSW(`NUM4) `CONT
+		`TICK `CONT
+
+		// Sort
+		`RESET
+		`SETSW(10'h5A)
+		`RUN
+		`SETSW(10'h3) `CONT
+		for (int i = 0; i < 16; i++) begin
+			`CONT
+		end
+		`SETSW(10'h2) `CONT
+		`SETSW(10'h3) `CONT
+		for (int i = 0; i < 16; i++) begin
+			`CONT
+		end
+
+`endif
+
+	end
+
+endmodule

lab5/ece385lab5.out.sdc

@@ -0,0 +1,7 @@
+set_time_format -unit ns -decimal_places 3
+create_clock -name {Clk} -period 10.000 -waveform { 0.000 10.000 } [get_ports {Clk}]
+set_input_delay -add_delay -rise -clock [get_clocks {Clk}] 0.500 [get_ports {Run}]
+set_input_delay -add_delay -rise -clock [get_clocks {Clk}] 0.500 [get_ports {Continue}]
+set_input_delay -add_delay -rise -clock [get_clocks {Clk}] 0.000 [get_ports {SW*}]
+set_output_delay -add_delay -rise -clock [get_clocks {Clk}] 0.000 [get_ports {LED*}]
+set_output_delay -add_delay -rise -clock [get_clocks {Clk}] 0.000 [get_ports {HEX*}]

lab5/ece385lab5.qpf

@@ -0,0 +1,6 @@
+QUARTUS_VERSION = "18.1"
+DATE = "10:00:00  February 18, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "ece385lab5"

lab5/ece385lab5.qsf

@@ -0,0 +1,103 @@
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name TOP_LEVEL_ENTITY SLC3Top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:00:00  FEBRUARY 18, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SYSTEMVERILOG_FILE src/top.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/topsim.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/topsynth.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/slc3.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/slc3isdu.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/slc3pkg.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/memsim.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/memsynth.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/mem2io.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/utils.sv
+set_global_assignment -name QIP_FILE ram/ram.qip
+set_global_assignment -name SDC_FILE ece385lab5.out.sdc
+set_location_assignment PIN_P11 -to Clk
+set_location_assignment PIN_A7 -to Run
+set_location_assignment PIN_B8 -to Continue
+set_location_assignment PIN_C10 -to SW[0]
+set_location_assignment PIN_C11 -to SW[1]
+set_location_assignment PIN_D12 -to SW[2]
+set_location_assignment PIN_C12 -to SW[3]
+set_location_assignment PIN_A12 -to SW[4]
+set_location_assignment PIN_B12 -to SW[5]
+set_location_assignment PIN_A13 -to SW[6]
+set_location_assignment PIN_A14 -to SW[7]
+set_location_assignment PIN_B14 -to SW[8]
+set_location_assignment PIN_F15 -to SW[9]
+set_location_assignment PIN_A8 -to LED[0]
+set_location_assignment PIN_A9 -to LED[1]
+set_location_assignment PIN_A10 -to LED[2]
+set_location_assignment PIN_B10 -to LED[3]
+set_location_assignment PIN_D13 -to LED[4]
+set_location_assignment PIN_C13 -to LED[5]
+set_location_assignment PIN_E14 -to LED[6]
+set_location_assignment PIN_D14 -to LED[7]
+set_location_assignment PIN_A11 -to LED[8]
+set_location_assignment PIN_B11 -to LED[9]
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_B20 -to HEX2[0]
+set_location_assignment PIN_A20 -to HEX2[1]
+set_location_assignment PIN_B19 -to HEX2[2]
+set_location_assignment PIN_A21 -to HEX2[3]
+set_location_assignment PIN_B21 -to HEX2[4]
+set_location_assignment PIN_C22 -to HEX2[5]
+set_location_assignment PIN_B22 -to HEX2[6]
+set_location_assignment PIN_F21 -to HEX3[0]
+set_location_assignment PIN_E22 -to HEX3[1]
+set_location_assignment PIN_E21 -to HEX3[2]
+set_location_assignment PIN_C19 -to HEX3[3]
+set_location_assignment PIN_C20 -to HEX3[4]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_E17 -to HEX3[6]
+set_location_assignment PIN_F18 -to HEX4[0]
+set_location_assignment PIN_E20 -to HEX4[1]
+set_location_assignment PIN_E19 -to HEX4[2]
+set_location_assignment PIN_J18 -to HEX4[3]
+set_location_assignment PIN_H19 -to HEX4[4]
+set_location_assignment PIN_F19 -to HEX4[5]
+set_location_assignment PIN_F20 -to HEX4[6]
+set_location_assignment PIN_J20 -to HEX5[0]
+set_location_assignment PIN_K20 -to HEX5[1]
+set_location_assignment PIN_L18 -to HEX5[2]
+set_location_assignment PIN_N18 -to HEX5[3]
+set_location_assignment PIN_M20 -to HEX5[4]
+set_location_assignment PIN_N19 -to HEX5[5]
+set_location_assignment PIN_N20 -to HEX5[6]
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH bench -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME bench -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id bench
+set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 us" -section_id bench
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME bench -section_id bench
+set_global_assignment -name EDA_TEST_BENCH_FILE bench.sv -section_id bench
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

lab5/filename_map.md

@@ -0,0 +1,12 @@
+| New Filename | Old Filename |
+| - | - |
+| `top.sv` | |
+| `topsim.sv` | `slc3_testtop.sv` |
+| `topsynth.sv` | `slc3_sramtop.sv` |
+| `slc3.sv` | `slc3.sv` |
+| `slc3isdu.sv` | `ISDU.sv` |
+| `slc3pkg.sv` | `SLC3_2.sv` |
+| `mem2io.sv` | `Mem2IO.sv` |
+| `memsim.sv` | `test_memory.sv` <br> `memory_contents.sv` |
+| `memsynth.sv` | `Instantiateram.sv` |
+| `utils.sv` | `synchronizers.sv` |

lab5/ram/ram.bsf

@@ -0,0 +1,129 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 216 128)
+	(text "ram" (rect 91 0 116 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 4 14 76 31)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 88 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "wren" (rect 4 30 35 47)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 88 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "address[9..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
+		(text "address[9..0]" (rect 4 46 93 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 88 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "rden" (rect 0 0 25 14)(font "Arial" (font_size 8)))
+		(text "rden" (rect 4 62 33 79)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 88 80))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 94 39 111)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 144 112))
+	)
+	(port
+		(pt 216 32)
+		(output)
+		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[15..0]" (rect 161 14 211 31)(font "Arial" (font_size 8)))
+		(line (pt 216 32)(pt 160 32)(line_width 3))
+	)
+	(drawing
+		(text "16 bits" (rect 105 32 201 177)(font "Arial" )(vertical))
+		(text "1024 words" (rect 120 16 231 207)(font "Arial" )(vertical))
+		(text "Block type: M9K" (rect 48 110 196 235)(font "Arial" ))
+		(line (pt 104 24)(pt 136 24))
+		(line (pt 136 24)(pt 136 96))
+		(line (pt 136 96)(pt 104 96))
+		(line (pt 104 96)(pt 104 24))
+		(line (pt 118 58)(pt 123 63))
+		(line (pt 118 62)(pt 123 57))
+		(line (pt 88 27)(pt 96 27))
+		(line (pt 96 27)(pt 96 39))
+		(line (pt 96 39)(pt 88 39))
+		(line (pt 88 39)(pt 88 27))
+		(line (pt 88 34)(pt 90 36))
+		(line (pt 90 36)(pt 88 38))
+		(line (pt 80 36)(pt 88 36))
+		(line (pt 96 32)(pt 104 32)(line_width 3))
+		(line (pt 152 27)(pt 160 27))
+		(line (pt 160 27)(pt 160 39))
+		(line (pt 160 39)(pt 152 39))
+		(line (pt 152 39)(pt 152 27))
+		(line (pt 152 34)(pt 154 36))
+		(line (pt 154 36)(pt 152 38))
+		(line (pt 144 36)(pt 152 36))
+		(line (pt 136 32)(pt 152 32)(line_width 3))
+		(line (pt 88 43)(pt 96 43))
+		(line (pt 96 43)(pt 96 55))
+		(line (pt 96 55)(pt 88 55))
+		(line (pt 88 55)(pt 88 43))
+		(line (pt 88 50)(pt 90 52))
+		(line (pt 90 52)(pt 88 54))
+		(line (pt 80 52)(pt 88 52))
+		(line (pt 96 48)(pt 104 48))
+		(line (pt 88 59)(pt 96 59))
+		(line (pt 96 59)(pt 96 71))
+		(line (pt 96 71)(pt 88 71))
+		(line (pt 88 71)(pt 88 59))
+		(line (pt 88 66)(pt 90 68))
+		(line (pt 90 68)(pt 88 70))
+		(line (pt 80 68)(pt 88 68))
+		(line (pt 96 64)(pt 104 64)(line_width 3))
+		(line (pt 88 75)(pt 96 75))
+		(line (pt 96 75)(pt 96 87))
+		(line (pt 96 87)(pt 88 87))
+		(line (pt 88 87)(pt 88 75))
+		(line (pt 88 82)(pt 90 84))
+		(line (pt 90 84)(pt 88 86))
+		(line (pt 80 84)(pt 88 84))
+		(line (pt 96 80)(pt 104 80))
+		(line (pt 80 112)(pt 80 36))
+		(line (pt 144 112)(pt 144 36))
+		(line (pt 0 0)(pt 217 0))
+		(line (pt 217 0)(pt 217 130))
+		(line (pt 0 130)(pt 217 130))
+		(line (pt 0 0)(pt 0 130))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)