first commit

.vscode/settings.json

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+{
+    "editor.semanticTokenColorCustomizations": {
+        "rules": {
+            "*.deprecated": {
+                "foreground": "#808080",
+                "italic": true
+            }
+        }
+    }
+}

aurel/Memo Cache Design (1).vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_unsigned.all;
+
+
+entity Cache is
+
+  port (
+      clk    : in  std_logic;
+      w : in  std_logic;
+      e      : in std_logic_vector (7 downto 0):= (others => '0');
+      s      : out std_logic_vector (7 downto 0):= (others => '0')
+  );
+  -- e : entrée , s : sortie , w(write) : entrée pour choisir de modifier le contenu du cache ou le lire    
+end  Cache;
+
+architecture Cache_Arch of Cache is
+   signal data : std_logic_vector (7 downto 0):= (others => '0');
+begin
+	arch_process : process (clk, w, e)
+    begin
+        if clk = '1' then
+            if w = '1' then
+                data <= e;
+            else
+                s <= data; 
+            end if ;
+        else
+            s <= (others => '0');
+        end if ;
+    end process;
+end Cache_Arch;
+

aurel/Memo Cache TB (1).vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity Cache_TB is 
+end Cache_TB;
+
+architecture Cache_ArchTB of Cache_TB is
+
+
+    component Cache is
+
+      port (
+          clk    : in  std_logic;
+          w : in  std_logic;
+          e      : in std_logic_vector (7 downto 0):= (others => '0');
+          s      : out std_logic_vector (7 downto 0):= (others => '0')
+      );
+    end  component;
+
+    constant PERIOD : time := 100 us ;
+
+   	signal clk_sim, w_sim : std_logic := '0'; 
+	  signal s_sim, e_sim : std_logic_vector (7 downto 0) := (others => '0');
+
+  begin
+
+	  Cache_underTest : Cache
+
+      port map (
+			  clk => clk_sim,
+        w => w_sim,
+        s => s_sim,
+        e => e_sim
+      );
+
+
+      MyStimulus_Proc : process
+
+      begin
+          clk_sim <= '1';
+          w_sim <= '1';
+          e_sim <= "00000100";      
+        wait for PERIOD;
+          report  " W = " & std_logic'image(w_sim) & " E = " & integer'image(to_integer(unsigned(e_sim))) & " S = " & integer'image(to_integer(unsigned(s_sim)));
+
+          clk_sim <= '0';
+          w_sim <= '0';
+        wait for PERIOD;
+          report  " W = " & std_logic'image(w_sim) & " E = " & integer'image(to_integer(unsigned(e_sim))) & " S = " & integer'image(to_integer(unsigned(s_sim)));
+
+          clk_sim <= '1';
+          w_sim <= '0';       
+        wait for PERIOD;
+          report  " W = " & std_logic'image(w_sim) & " E = " & integer'image(to_integer(unsigned(e_sim))) & " S = " & integer'image(to_integer(unsigned(s_sim)));
+
+
+          clk_sim <= '0';
+        wait for PERIOD;
+          report  " W = " & std_logic'image(w_sim) & " E = " & integer'image(to_integer(unsigned(e_sim))) & " S = " & integer'image(to_integer(unsigned(s_sim)));
+        wait;
+      end process ;
+
+  end Cache_ArchTB;

aurel/Memo_InstruDesign.vhd

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+-- Code your design here
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;		 
+use ieee.std_logic_unsigned.all;
+
+entity instruction_memo is
+port(	
+    clk   : in std_logic;
+	reset	: in std_logic;	
+	sel_fct: out std_logic_vector(3 downto 0);
+    sel_route: out std_logic_vector(3 downto 0);
+    sel_out: out std_logic_vector(1 downto 0)
+);
+end instruction_memo;
+
+--------------------------------------------------------------
+
+architecture instruction_memo_Arch of instruction_memo is
+
+    type ROM_Array is array (0 to 127) of std_logic_vector(3 downto 0);
+
+    constant MEMORY: ROM_Array := (
+        0 => "0001",		 
+        1 => "0010",		
+        2 => "0101",		
+        3 => "0100",       		
+        4 => "0101",		
+        5 => "0110",       	
+	    OTHERS => "0000"
+	);       
+
+    constant limit : integer := 4;
+
+
+begin
+    process(clk, reset) is 
+    	variable pointer : integer := 0;
+    begin
+        if (clk = '1') then
+        	sel_fct <= MEMORY(pointer);
+            if pointer = limit then
+            	pointer := 0;
+            else
+        		pointer := pointer + 1 ;
+            end if;
+        end if ;
+    end process;
+end instruction_memo_Arch;
+
+--------------------------------------------------------------

aurel/Memo_InstruTB.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity instruction_memo_TB is 
+end instruction_memo_TB;
+
+architecture instruction_memo_ArchTB of instruction_memo_TB is
+
+
+      component instruction_memo is
+
+        port(	
+          clk   : in std_logic;
+          reset	: in std_logic;	
+          sel_fct: out std_logic_vector(3 downto 0);
+          sel_route: out std_logic_vector(3 downto 0);
+          sel_out: out std_logic_vector(1 downto 0)
+        );
+      end  component;
+
+    constant PERIOD : time := 100 us ;
+
+   	signal clk_sim, reset_sim : std_logic := '0';
+    signal sel_out_sim : std_logic_vector(1 downto 0) := (others => '0');  
+	signal sel_fct_sim, sel_route_sim : std_logic_vector (3 downto 0) := (others => '0');
+
+begin
+
+	  instruction_memo_underTest : instruction_memo
+
+      port map (
+			clk => clk_sim,
+            reset => reset_sim,
+            sel_out => sel_out_sim,
+            sel_fct => sel_fct_sim,
+            sel_route => sel_route_sim
+      );
+
+
+      MyStimulus_Proc : process
+
+      begin
+        clk_sim <= '1';      
+      	wait for PERIOD;
+          report " Fonction = " & integer'image(to_integer(unsigned(sel_fct_sim)));
+
+        clk_sim <= '0';
+		wait for PERIOD;
+          report " Fonction = " & integer'image(to_integer(unsigned(sel_fct_sim)));
+        clk_sim <= '1';      
+      	wait for PERIOD;
+          report " Fonction = " & integer'image(to_integer(unsigned(sel_fct_sim)));
+
+        clk_sim <= '0';
+		wait for PERIOD;
+          report " Fonction = " & integer'image(to_integer(unsigned(sel_fct_sim)));
+        clk_sim <= '1';      
+      	wait for PERIOD;
+          report " Fonction = " & integer'image(to_integer(unsigned(sel_fct_sim)));
+
+        clk_sim <= '0';
+		wait for PERIOD;
+          report " Fonction = " & integer'image(to_integer(unsigned(sel_fct_sim)));
+
+
+        wait;
+      end process ;
+
+
+
+
+end instruction_memo_ArchTB;

aurel/UAL Vital.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_unsigned.all;
+
+
+
+entity UAL is
+
+  port (
+      e_a    : in std_logic_vector (3 downto 0):= (others => '0');
+      e_b    : in std_logic_vector (3 downto 0):= (others => '0');
+      sr_in  : in std_logic_vector (1 downto 0):= (others => '0');
+      sel_fct: in std_logic_vector (3 downto 0):= (others => '0');
+      sr_out : out std_logic_vector (1 downto 0):= (others => '0');
+      s      : out std_logic_vector (7 downto 0):= (others => '0')
+  );
+end  UAL;
+
+architecture UAL_Arch of UAL is
+begin
+	arch_process : process (e_a, e_b, sr_in, sel_fct)
+    begin
+    	--nop (no operation) s = 0 | sr_out_L = 0 et sr_out_R = 0
+        if (sel_fct = "0000") then
+            s <= (others =>'0');
+            sr_out <= "00";
+		--S = Déc. droite e_a sur 4 bits (avec sr_in_L) | sr_in_L pour le bit entrant et sr_out_R pour le bit sortant
+        elsif (sel_fct = "0001") then
+            s(7 downto 4) <= (others => '0'); 
+            s(3) <= sr_in(1); 
+            s(2 downto 0) <= e_a(3 downto 1);
+            sr_out(1) <= '0'; 
+            sr_out(0) <= e_a(0);
+
+        --S = Déc. gauche e_a sur 4 bits (avec sr_in_R) | sr_in_R pour le bit entrant et sr_out_L pour le bit sortant
+        elsif (sel_fct="0010") then 
+            s(7 downto 4) <= (others => '0'); 
+            s(3 downto 1) <= e_a(2 downto 0); 
+            s(0) <= sr_in(0);
+            sr_out(1) <= e_a(3); 
+            sr_out(0) <= '0';
+
+        --S = Déc. droite B sur 4 bits (avec sr_in_L) | sr_in_L pour le bit entrant et sr_out_R pour le bit sortant
+        elsif (sel_fct = "0011") then
+            s(7 downto 4) <= (others => '0');
+            s(3) <= sr_in(1); 
+            s(2 downto 0) <= e_b(3 downto 1);
+            sr_out(1) <= '0'; 
+            sr_out(0) <= e_b(0);
+
+        --S = Déc. gauche B sur 4 bits (avec sr_in_R) | sr_in_R pour le bit entrant et sr_out_L pour le bit sortant
+        elsif (sel_fct = "0100") then 
+            s(7 downto 4) <= (others => '0'); 
+            s(3 downto 1) <= e_b(2 downto 0); 
+            s(0) <= sr_in_R;
+            sr_out(1) <= e_b(3);
+            sr_out(0)) <= '0';
+
+        --S = A * B multiplication binaire | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "0101") then							
+            s <= a * b;
+            sr_out <= "00";
+
+        --S = A + B addition binaire avec sr_in_R comme retenue d’entrée | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "0110") then						            
+            s(7 downto 5) <= (others => '0');
+            s(4 downto 0) <= ('0' & a) + ('0' & b) +('0000' & sr_in(0));
+            sr_out <= "00";
+
+        --S = A + B addition binaire sans retenue d’entrée | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "0111") then							
+            s(7 downto 5) <= (others => '0');
+            s(4 downto 0) <= ('0' & a) + ('0' & b);
+            sr_out <= "00";
+
+        --S = A – B soustraction binaire | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "1000") then							
+            s(7 downto 4) <= (others => '0');
+            s(3 downto 0) <= a - b;
+            sr_in <= "00";
+            sr_out <= "00";
+
+        --S = A | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "1001") then							
+            s <= a;
+            sr_out <= "00";
+
+        --S = B | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "1010") then							
+            s <= b;
+            sr_out <= "00";
+
+        --S = not A | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "1011") then							
+            s <= not(a);
+            sr_out <= "00";
+
+        --S = not B | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "1100") then							
+            s <= not(b);
+            sr_out <= "00";
+
+        --S = A and B | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "1101") then							
+            s <= a and b;
+            sr_out <= "00";
+
+        --S = A or B | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "1110") then							
+            s <= a or b;
+            sr_out <= "00";
+
+        --S = A xor B | sr_out_L = 0 et sr_out_R = 0
+        elsif (sel_fct = "1111") then							
+            s <= a xor b;
+
+        else
+          s <= (others =>'0');
+          sr_out <= (others =>'0');
+        end if;
+    end process;
+end UAL_Arch;