Welcome! This repository showcases my hands-on exploration of full-custom CMOS VLSI design using open-source tools like Magic VLSI, Xschem, ngspice, and netgen.
After completing a digital systems design course at Case Western Reserve University, I became fascinated by the chip design process—but quickly realized how scarce beginner-friendly resources were. This repo is both my portfolio and a resource for other students or engineers exploring VLSI.
My goal is to keep each subproject well-documented and approachable, balancing technical depth with clarity—for everyone from ECSE students to recruiters.
| Tool | Purpose |
|---|---|
| Xschem | Schematic capture and SPICE netlist generation |
| Magic | Full-custom layout (diffusion, poly, metal) + layout extraction |
| Netgen | Layout vs. Schematic (LVS) validation |
| ngspice | SPICE simulations (transient, DC, delay, switching behavior) |
- All tools installed via
apt-geton Ubuntu - Technology: 2002a node from OpenCircuitDesign (will migrate to sky130A)
The "Hello World" of VLSI
- Designed and simulated a CMOS inverter.
- Validated DRC and LVS using Magic + Netgen.
- Simulated transient behavior with ngspice.
Full-custom layout and SPICE simulation of basic gates
- Gates: NAND, NOR, AND, OR.
- Designed schematics in Xschem, laid out in Magic.
- Performed LVS and transient simulations.
- Measured propagation delay for each gate.
Sequential elements from the transistor level up
- SR latch and D flip-flop (schematic + layout).
- Create and lay out a single SRAM cell.
- Simulations to identify setup and hold times.
- Foundation for more complex memory blocks.
First Analog Subproject using CMOS technology
- Design a two-stage operational amplifier using the Miller compensation technique.
- Analyze the bandwidth, gain, and the output impedance of the operational amplifier.
- Explores analog CMOS design and layout.
- Explore digital, analog, and mixed signal layouts and schematics.
- Migrate from the 2002a node to the Sky130A PDK to potentially have chips manufactured.
- Build a reusable standard cell library and small datapath.
- Create a beginner-friendly write-up series on each block.
Feel free to explore each subfolder for detailed READMEs, layout screenshots, and simulation plots!