Merge branch 'master' into tweak_marble_family

.gitlab-ci.yml

@@ -8,8 +8,7 @@ stages:
 variables:
   XILINX_VIVADO: /non-free/Xilinx/Vivado/2020.2
   CI_REGISTRY: mohs.dhcp.lbl.gov
-  CONTAINER_IMAGE: $CI_REGISTRY/testing_base_bookworm
-  # CONTAINER_IM_IMAGE: $CI_REGISTRY/riscv_bloat
+  CONTAINER_IMAGE: $CI_REGISTRY/bedrock_testing_base_bookworm
   DOCKER_HOST: tcp://docker:2375/
   DOCKER_DRIVER: overlay2
 
@@ -19,7 +18,6 @@ services:
   - name: mohs.dhcp.lbl.gov/docker:20.10.12-dind
     command: ["--insecure-registry", "mohs.dhcp.lbl.gov"]
     alias: docker
-#    entrypoint: ["dockerd-entrypoint.sh"]
 
 include:
   - local: .gitlab/ci/badger.gitlab-ci.yml

.gitlab/ci/badger.gitlab-ci.yml

@@ -25,4 +25,4 @@ badger_ac701_run:
   dependencies:
     - badger_ac701
   script:
-    - cd badger/tests && test -r ac701_rgmii_vtest.bit && sh teststand_ac701.sh
+    - cd badger/tests && test -r ac701_rgmii_vtest.bit && SERIAL_NUM_OPT="-s 210203356870" sh teststand_ac701.sh

.gitlab/ci/build.gitlab-ci.yml

@@ -15,6 +15,7 @@ build:
         -t $CONTAINER_IMAGE:$CI_PROJECT_NAME-$CI_COMMIT_SHORT_SHA \
         -t $CONTAINER_IMAGE:latest \
         .
+    docker run --rm $CONTAINER_IMAGE bash -c 'echo -n "Debian version: "; cat "/etc/debian_version"'
     docker push $CONTAINER_IMAGE:$CI_COMMIT_REF_NAME
     docker push $CONTAINER_IMAGE:$CI_PROJECT_NAME-$CI_COMMIT_SHORT_SHA
     docker push $CONTAINER_IMAGE:latest

.gitlab/ci/comms_top.gitlab-ci.yml

@@ -40,4 +40,4 @@ gige_sfp_ac701_run:
   dependencies:
     - gige_sfp_ac701
   script:
-    - cd projects/comms_top/gige_eth && make hwload_ac701 && make hwtest_ac701
+    - cd projects/comms_top/gige_eth && make hwload_ac701 SERIAL_NUM_OPT="-s 210203356870" && sleep 7 && make hwtest_ac701

.gitlab/ci/oscope.gitlab-ci.yml

@@ -5,6 +5,20 @@ oscope_top_test:
   script:
     - make Voscope_top_tb && make Voscope_top_leep && make clean
 
+# We know the design doesn't yet get evaluated as CDC-clean, at least in part
+# due to Verilog inout ports being poorly supported by our tools.
+# Please take out the error bypass (echo) if this ever gets fixed.
+oscope_cdc:
+  before_script:
+    - cd projects/oscope/marble_family
+  stage: test
+  script:
+    - make dep && make oscope_prep_yosys.json && (make oscope_prep_cdc.txt || echo "Found CDC violation, as expected; continuing")
+  artifacts:
+    expire_in: 1 week
+    paths:
+      - projects/oscope/marble_family/oscope_prep_cdc.txt
+
 oscope_top_bmb7:
   before_script:
     - cd projects/oscope/bmb7_cu && ls /non-free
@@ -29,17 +43,15 @@ oscope_top_marble:
     paths:
       - projects/oscope/marble_family/oscope_top.bit
 
+# LITEX_INSTALL_PATH is defined in the Docker image
 marble_ddr3_test:
   stage: synthesis
   before_script:
-    - apt-get update && apt-get install -y ninja-build && pip3 install meson==0.64.1
-    - mkdir /litex_setup_dir
-    - (BD=$PWD && cd /litex_setup_dir && sh $BD/build-tools/litex_meta.sh)
-    - cd /litex_setup_dir/litex-boards/litex_boards/targets
+    - cd $LITEX_INSTALL_PATH/litex-boards/litex_boards/targets
   script:
     - XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE PATH=$XILINX_VIVADO/bin:$PATH && python3 berkeleylab_marble.py --build
     - echo $CI_PROJECT_DIR
-    - cp /litex_setup_dir/litex-boards/litex_boards/targets/build/berkeleylab_marble/gateware/berkeleylab_marble.bit $CI_PROJECT_DIR/
+    - cp $LITEX_INSTALL_PATH/litex-boards/litex_boards/targets/build/berkeleylab_marble/gateware/berkeleylab_marble.bit $CI_PROJECT_DIR/
   artifacts:
     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
     expire_in: 1 week
@@ -50,9 +62,6 @@ marble_ddr3_test:
 litex_trigger_capture:
   stage: synthesis
   before_script:
-    - apt-get update && apt-get install -y ninja-build && pip3 install meson==0.64.1
-    - mkdir /litex_setup_dir
-    - (BD=$PWD && cd /litex_setup_dir && sh $BD/build-tools/litex_meta.sh)
     - cd projects/trigger_capture
   script:
     XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE PATH=$XILINX_VIVADO/bin:$PATH && make marble.bit

Dockerfile

@@ -1,4 +1,4 @@
-FROM debian:bookworm-slim as testing_base_bookworm
+FROM debian:12.8-slim AS testing_base_bookworm
 
 # Vivado needs libtinfo5, at least for Artix?
 RUN apt-get update && \
@@ -114,3 +114,33 @@ RUN apt-get update && \
         libidn12 && \
     rm -rf /var/lib/apt/lists/* && \
     ln -s libidn.so.12 /usr/lib/x86_64-linux-gnu/libidn.so.11
+
+# Install litex
+RUN apt-get update && \
+    apt-get install -y \
+        ninja-build \
+        gcc-aarch64-linux-gnu \
+        ghdl && \
+    rm -rf /var/lib/apt/lists/* && \
+    pip3 install \
+        meson
+
+COPY build-tools/litex_meta.sh /
+
+ENV LITEX_INSTALL_PATH=/litex
+
+RUN mkdir ${LITEX_INSTALL_PATH} && \
+    cd ${LITEX_INSTALL_PATH} && \
+    sh /litex_meta.sh
+
+# Install sv2v
+RUN apt-get update && \
+    apt-get install -y \
+        haskell-stack && \
+    rm -rf /var/lib/apt/lists/* && \
+    git clone https://github.com/zachjs/sv2v /sv2v && \
+    cd /sv2v && \
+    git checkout 7808819c48c167978aeb5ef34c6e5ed416e90875 && \
+    make && \
+    rm -rf $HOME/.stack && \
+    cp bin/sv2v /usr/local/bin/

badger/tests/kc705/ODDR.v

@@ -1,5 +1,5 @@
 // pathetic model of Xilinx DDR output cell
-// ignores set and reset inputs
+// ignores set and reset inputs, and the SRTYPE and DDR_CLK_EDGE parameters
 module ODDR (
 	input S,
 	input R,
@@ -14,10 +14,11 @@ parameter DDR_CLK_EDGE = "SAME_EDGE";
 parameter INIT = 0;
 parameter SRTYPE = "SYNC";
 
-reg qx=INIT, hold=INIT;
-always @(posedge C) if (CE) qx <= D1;
-always @(posedge C) if (CE) hold <= D2;
-always @(negedge C) qx <= hold;
-assign Q = qx;
+reg hold1=INIT, hold2=INIT;
+always @(posedge C) if (CE) begin
+	hold1 <= D1;
+	hold2 <= D2;
+end
+assign Q = C ? hold1 : hold2;
 
 endmodule

badger/tests/teststand_ac701.sh

@@ -4,7 +4,7 @@
 # Tested useful for the CI test stand (mohs) at LBNL.
 # Can also act as a template for other use cases.
 set -e
-xc3sprog -c jtaghs1_fast ac701_rgmii_vtest.bit
+xc3sprog -c jtaghs1_fast $SERIAL_NUM_OPT ac701_rgmii_vtest.bit
 echo "So far so good"
 sleep 8
 echo "Hope links are up"

board_support/zest/zest_if.sv

@@ -35,7 +35,8 @@ interface zest_if (
    assign {U2_D1NA, U2_D1NB, U2_D1NC, U2_D1ND} = {U2[14], U2[4],  U2[26], U2[11]};
    assign {U2_D1PA, U2_D1PB, U2_D1PC, U2_D1PD} = {U2[17], U2[8],  U2[5],  U2[12]};
    assign {U2_DCON, U2_DCOP, U2_FCON, U2_FCOP} = {U2[9],  U2[15], U2[10], U2[6]};
-   assign {U3[10], U2[22], U4[26]} = {U2_PDWN, U2_CSB, U2_SCLK};
+   assign {U2[22], U4[26]} = {U2_CSB, U2_SCLK};
+   // don't set U3[10] to U2_PDWN, since it's set to U3_PDWN below
 
    wire U3_D0NA, U3_D0NB, U3_D0NC, U3_D0ND, U3_D0PA, U3_D0PB, U3_D0PC, U3_D0PD,
         U3_D1NA, U3_D1NB, U3_D1NC, U3_D1ND, U3_D1PA, U3_D1PB, U3_D1PC, U3_D1PD,
@@ -77,9 +78,9 @@ interface zest_if (
    wire U18_DOUT_RDY = U18[1];
    assign {U18[0], U18[2], U18[3], U18[4]} = {U18_CLK, U18_CS, U18_DIN, U18_SCLK};
 
-   // NOTE: Semantics of PMOD and HDMI connectors are application-dependent and
+   // NOTE: Semantics of Pmod and HDMI connectors are application-dependent and
    //       thus not handled here
-   // PMOD - J18, J17
+   // Pmod - J18, J17
    // J19: HDMI
 
    // U33U1: TPS62110 DC-DC converter

board_support/zest_soc/vita_57.1_pinout.txt

@@ -1,6 +1,6 @@
-#from https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html
-#  compactible with KC705 UG810 Appendix B
-#  compactible with FMC116_112_user_manual.pdf Table 8.
+# from https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html
+#  compatible with KC705 UG810 Appendix B
+#  compatible with FMC116_112_user_manual.pdf Table 8
 
 CLK0_M2C_N      H5
 CLK0_M2C_P      H4

board_support/zest_soc/zest.v

@@ -245,7 +245,7 @@ assign PWR_EN       = ~pwr_en_b;
 
 // ADC0_DIV, ADC1_DIV, DAC_DCO
 wire signed [PH_DIFF_DW-1:0] phdiff [N_ADC:0];
-wire [N_ADC:0] phdiff_val;
+wire [N_ADC:0] phdiff_err;
 // DSP_CLK, ADC0_DIV, ADC1_DIV, DAC_DCO
 wire [27:0] f_clks [N_ADC+1:0];
 wire pll_locked;
@@ -318,14 +318,13 @@ generate for (ix=0; ix<N_ADC; ix=ix+1) begin: ic_map
         .clk_div_buf  (clk_div_buf[ix])
     );
 
-    phase_diff #(.adv(PH_DIFF_ADV), .dw(PH_DIFF_DW+1)) phase_diff_i (
+    phase_diff #(.adv(PH_DIFF_ADV), .dw(PH_DIFF_DW+1), .delta(33)) phase_diff_i (
         .uclk1      (dsp_clk_out),
-        .ext_div1   (1'b0),
         .uclk2      (clk_div[ix]),
-        .ext_div2   (1'b0),
+        .uclk2g     (1'b1),
         .sclk       (clk_200),
         .rclk       (clk),
-        .dval       (phdiff_val[ix]),
+        .err        (phdiff_err[ix]),
         .phdiff_out (phdiff[ix])
     );
 
@@ -403,15 +402,15 @@ phase_diff #(
     .adv            (PH_DIFF_ADV),
     .dw             (PH_DIFF_DW+1),
     .order1         (2),
-    .order2         (1)
+    .order2         (1),
+    .delta          (33)
 ) phase_diff_dac (
     .uclk1      (dac_dco_clk),
-    .ext_div1   (1'b0),
     .uclk2      (dsp_clk_out),
-    .ext_div2   (1'b0),
+    .uclk2g     (1'b1),
     .sclk       (clk_200),
     .rclk       (clk),
-    .dval       (phdiff_val[2]),
+    .err        (phdiff_err[2]),
     .phdiff_out (phdiff[2])
 );
 

build-tools/parser.py

@@ -416,6 +416,7 @@ def parse_vfile_yosys(self, stack, fin, fd, dlist, clk_domain, cd_indexed):
 
         for port, (net_info, port_info) in parsed_mod['external_nets'].items():
             signal_type = net_info['attributes']['signal_type'] if 'signal_type' in net_info['attributes'] else None
+            port_cd = net_info['attributes']['cd'] if 'cd' in net_info['attributes'] else clk_domain
             signed = 'signed' if 'signed' in net_info else None
             direction = port_info['direction'] if 'direction' in port_info else None
             p = Port(port,
@@ -425,7 +426,7 @@ def parse_vfile_yosys(self, stack, fin, fd, dlist, clk_domain, cd_indexed):
                      signed,
                      this_mod,
                      signal_type,
-                     clk_domain,
+                     port_cd,
                      cd_indexed,
                      port_info != {},
                      **attributes)
@@ -441,7 +442,7 @@ def parse_vfile_yosys(self, stack, fin, fd, dlist, clk_domain, cd_indexed):
                          None,
                          this_mod,
                          'plus-we-VOID',
-                         clk_domain,
+                         port_cd,
                          cd_indexed,
                          port_info != {},
                          **attributes)

dsp/phase_diff.gtkw

@@ -0,0 +1,33 @@
+[timestart] 0
+[size] 1150 707
+[pos] -1 -1
+*-23.233957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] phase_diff_tb.
+[treeopen] phase_diff_tb.track.
+[sst_width] 269
+[signals_width] 219
+[sst_expanded] 1
+[sst_vpaned_height] 191
+@8024
+phase_diff_tb.phase_diff[15:0]
+@20000
+-
+@420
+phase_diff_tb.vfreq_out[16:0]
+@200
+-trackers
+@8024
+phase_diff_tb.track.phaset_out1[16:0]
+@20000
+-
+@28
+phase_diff_tb.track.fault1
+@8024
+phase_diff_tb.track.phaset_out2[16:0]
+@20000
+-
+@28
+phase_diff_tb.track.fault2
+phase_diff_tb.track.tick
+[pattern_trace] 1
+[pattern_trace] 0