Maintainance - mostly Verilog preprocessor hygiene

Also realign cmoc_top.v with marble_base() port changes and marble_top.v

cmoc/cryomodule.v

@@ -66,6 +66,7 @@ module cryomodule(
 	input lb_read,
 	output [31:0] lb_out
 );
+`undef AUTOMATIC_self
 
 // Note that the following five parameters should all be in the range 0 to 255,
 // in order to be properly read out via config_data0, below.
@@ -104,8 +105,7 @@ wire lb2_clk = clk1x;
 
 parameter n_cycles = n_mech_modes * 2;
 parameter interp_span = 4;  // ceil(log2(n_cycles))
-`define SLOW_SR_LEN 4*8
-parameter sr_length = `SLOW_SR_LEN;
+parameter sr_length = 4*8;
 
 `ifndef SIMPLE_DEMO
 // Transfer local bus to clk2x domain
@@ -239,13 +239,13 @@ generate for (cavity_n=0; cavity_n < cavity_count; cavity_n=cavity_n+1) begin: c
    assign slow_data_ready[cavity_n] = circle_data_ready[cavity_n] & ~slow_invalid;  // XXX mixes domains, simulate to make sure it's glitch-free
    // Make our own additions to slow shift register
    // equivalence circle_stat: circle_fault 1, circle_wrap 1, circle_addr 14
-`define SLOW_SR_DATA { circle_count, circle_stat }
+   wire [sr_length-1:0] slow_sr_data = { circle_count, circle_stat };
    // TODO: These `we_*` wires below, are taken from the decode signals that are auto generated
    wire [7:0] slow_shell_out;
 
    reg [sr_length-1:0] slow_read=0;
    always @(posedge clk1x) if (slow_op) begin
-      slow_read <= slow_snap ? `SLOW_SR_DATA : {slow_read[sr_length-9:0],slow_shell_out};
+      slow_read <= slow_snap ? slow_sr_data : {slow_read[sr_length-9:0],slow_shell_out};
    end
    assign slow_out = slow_read[sr_length-1:sr_length-8];
 

cmoc/fdbk_core.v

@@ -33,6 +33,7 @@ module fdbk_core(
 	input [1:0] coarse_scale,  // external
 	`AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 // Knobs to use/bypass CORDIC multiplexer, Magnitude/Phase processor (slow),
 // and Low-Latency Processor (bypassing conversion to polar coordinates)

cmoc/llrf_shell.v

@@ -56,6 +56,7 @@ module llrf_shell(
 
 	`AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 `AUTOMATIC_decode
 
@@ -103,13 +104,12 @@ timestamp ts(.clk(clk), .aux_trig(1'b0), .slow_op(slow_op), .slow_snap(slow_snap
 // changing other controls. tag_now shows the value of tag at the end-time of
 // the buffer, tag_old shows it at the begin-time of the buffer.  Not perfect
 // because of non-boxcar filtering and sloppy pipelining.
-`define SLOW_SR_LEN 7*16
-`define SLOW_SR_DATA { adc1_min, adc1_max, adc2_min, adc2_max, adc3_min, adc3_max, tag_now, tag_old }
-parameter sr_length = `SLOW_SR_LEN;
-reg [sr_length-1:0] slow_read=0;
 reg [7:0] tag_old=0;
+parameter sr_length = 7*16;
+wire [sr_length-1:0] slow_sr_data = { adc1_min, adc1_max, adc2_min, adc2_max, adc3_min, adc3_max, tag_now, tag_old };
+reg [sr_length-1:0] slow_read=0;
 always @(posedge clk) if (slow_op) begin
-	slow_read <= slow_snap ? `SLOW_SR_DATA : {slow_read[sr_length-9:0],timestamp_out};
+	slow_read <= slow_snap ? slow_sr_data : {slow_read[sr_length-9:0],timestamp_out};
 	if (slow_snap) tag_old <= tag_now;
 end
 assign slow_out = slow_read[sr_length-1:sr_length-8];

cmoc/piezo_control.v

@@ -23,6 +23,7 @@ module piezo_control(
 	output [6:0] trace_en_addr  // external address for trace_en
 	//`AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 // Non-zero placeholder
 // Eventually intend to use reg_mac2 or similar;

cmoc/rf_controller.v

@@ -69,6 +69,7 @@ module rf_controller (
 	input [7:0] tag, // external
 	`AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 `AUTOMATIC_decode
 

dsp/hosted/lp_2notch.v

@@ -13,6 +13,7 @@ module lp_2notch(
 	output signed [19:0] y,
 	`AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 `AUTOMATIC_decode
 

dsp/hosted/lp_notch.v

@@ -16,6 +16,7 @@ module lp_notch(
 	output signed [19:0] y,
 	`AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 `AUTOMATIC_decode
 

dsp/timestamp.v

@@ -101,8 +101,8 @@ assign shift_in2 = aux_reg ? (apost8 ? ashiftd : axmit ? asnap_out : 0) : shift_
 // Making an explicit copy like this avoids a warning when dw != 8
 assign shift_out=snap_out;
 
-// More-or-less equivalent to
-// define SLOW_SR_DATA { time1, time2, time3, time4, atime1, atime2, atime3, atime4 }
-// but uses far fewer resources
+// More-or-less equivalent to adding
+//   { time1, time2, time3, time4, atime1, atime2, atime3, atime4 }
+// to slow_sr_data, but uses far fewer resources
 
 endmodule

fpga_family/mgt/qgt_wrap_stub.vh

@@ -151,6 +151,9 @@
               `ifdef GT1_ENABLE gt1_txresetdone & gt1_rxresetdone, `else 1'b0, `endif
               `ifdef GT0_ENABLE gt0_txresetdone & gt0_rxresetdone `else 1'b0 `endif };
 
+   // practice good preprocessor hygiene
+   `undef Q_GT_MODULE
+
 `else // SIMULATE
 
    // Instantiate dummy components to help dependency generation and basic syntax checking

projects/cmoc_top/marblemini/cmoc_top.v

@@ -3,33 +3,35 @@ module cmoc_top(
 	input       GTPREFCLK_N,
 	input       SYSCLK_P,
 
-	// RGMII
+	// RGMII Tx port
 	output [3:0] RGMII_TXD,
 	output       RGMII_TX_CTRL,
 	output       RGMII_TX_CLK,
+
+	// RGMII Rx port
 	input [3:0]  RGMII_RXD,
 	input       RGMII_RX_CTRL,
 	input       RGMII_RX_CLK,
 
 	// SPI boot flash programming port
 	// BOOT_CCLK treated specially in 7-series
-	output       BOOT_CS_B,
+	output      BOOT_CS_B,
 	input       BOOT_MISO,
-	output       BOOT_MOSI,
-	output       CFG_D02, // hope R209 is DNF
+	output      BOOT_MOSI,
+	output      CFG_D02, // hope R209 is DNF
 
-	// One I2C bus, everything gatewayed through a TCA9548
-	output       TWI_SCL,
+	// One I2C bus, with everything gatewayed through a TCA9548
+	output      TWI_SCL,
 	inout       TWI_SDA,
-	output       TWI_RST,
+	output      TWI_RST,
 	input       TWI_INT,
 
 	// SPI pins connected to microcontroller
 	input       SCLK,
 	input       CSB,
 	input       MOSI,
-	output       MISO,
-	output       MMC_INT,
+	output      MISO,
+	output      MMC_INT,
 
 	// White Rabbit DAC
 	output       WR_DAC_SCLK,
@@ -61,7 +63,7 @@ BUFG passg_125(.I(gtpclk0), .O(gtpclk));
 
 parameter in_phase_tx_clk = 1;
 // Standardized interface, hardware-dependent implementation
-wire tx_clk, tx_clk90;
+wire tx_clk, tx_clk90, clk62;
 wire clk_locked;
 wire pll_reset = 0;  // or RESET?
 
@@ -92,6 +94,7 @@ gmii_clock_handle clocks(
 	.clk_locked(clk_locked)
 );
 `endif
+assign clk62 = 0;  // Ignore dna primitive at least for now
 
 // Double-data-rate conversion
 wire vgmii_tx_clk, vgmii_tx_clk90, vgmii_rx_clk;
@@ -121,9 +124,11 @@ gmii_to_rgmii #(.in_phase_tx_clk(in_phase_tx_clk)) gmii_to_rgmii_i(
 );
 
 wire BOOT_CCLK;
+wire cfg_clk;  // Just for fun, so we can measure its frequency
 `ifndef SIMULATE
-STARTUPE2 set_cclk(.USRCCLKO(BOOT_CCLK), .USRCCLKTS(1'b0));
+STARTUPE2 set_cclk(.USRCCLKO(BOOT_CCLK), .USRCCLKTS(1'b0), .CFGMCLK(cfg_clk));
 `else // !`ifndef SIMULATE
+   assign cfg_clk = 0;
    assign BOOT_CCLK = tx_clk;
 `endif // !`ifndef SIMULATE
 
@@ -139,6 +144,15 @@ wire [33:0] FMC1_LA_P;
 wire [33:0] FMC1_LA_N;
 wire [33:0] FMC2_LA_P;
 wire [33:0] FMC2_LA_N;
+wire [1:0] FMC1_CK_P;
+wire [1:0] FMC1_CK_N;
+wire [1:0] FMC2_CK_P;
+wire [1:0] FMC2_CK_N;
+wire [23:0] FMC2_HA_P;
+wire [23:0] FMC2_HA_N;
+
+// vestiges of CERN FMC tester support
+wire old_scl1, old_scl2, old_sda1, old_sda2;
 
 // Real, portable implementation
 // Consider pulling 3-state drivers out of this
@@ -151,11 +165,12 @@ marble_base #(.USE_I2CBRIDGE(1)) base(
 	.boot_clk(BOOT_CCLK), .boot_cs(BOOT_CS_B),
 	.boot_mosi(BOOT_MOSI), .boot_miso(BOOT_MISO),
 	.cfg_d02(CFG_D02), .mmc_int(MMC_INT), .ZEST_PWR_EN(ZEST_PWR_EN),
-	.aux_clk(SYSCLK_P), .GPS(4'b0),
+	.aux_clk(SYSCLK_P), .clk62(clk62), .cfg_clk(cfg_clk),
+	.GPS(4'b0),
 	.SCLK(SCLK), .CSB(CSB), .MOSI(MOSI), .MISO(MISO),
 	.FPGA_RxD(FPGA_RxD), .FPGA_TxD(FPGA_TxD),
-	.twi_scl({dum_scl, FMC2_LA_P[2] , FMC1_LA_P[2], TWI_SCL}),
-	.twi_sda({dum_sda, FMC2_LA_N[2], FMC1_LA_N[2], TWI_SDA}),
+	.twi_scl({dum_scl, old_scl1, old_scl2, TWI_SCL}),
+	.twi_sda({dum_sda, old_sda1, old_sda2, TWI_SDA}),
 	.TWI_RST(TWI_RST), .TWI_INT(TWI_INT),
 	.lb_clk(lb_clk),
 	.lb_addr(lb_addr),
@@ -166,10 +181,8 @@ marble_base #(.USE_I2CBRIDGE(1)) base(
 	.lb_data_out(lb_data_out),
 	.lb_data_in(lb_din),
 	.fmc_test({
-		FMC2_LA_P[33:3], FMC2_LA_P[1:0],
-		FMC2_LA_N[33:3], FMC2_LA_N[1:0],
-		FMC1_LA_P[33:3], FMC1_LA_P[1:0],
-		FMC1_LA_N[33:3], FMC1_LA_N[1:0]}),
+		FMC2_HA_P, FMC2_HA_N, FMC2_CK_P, FMC2_CK_N, FMC2_LA_P, FMC2_LA_N,
+		FMC1_CK_P, FMC1_CK_N, FMC1_LA_P, FMC1_LA_N}),
 	.WR_DAC_SCLK(WR_DAC_SCLK), .WR_DAC_DIN(WR_DAC_DIN),
 	.WR_DAC1_SYNC(WR_DAC1_SYNC), .WR_DAC2_SYNC(WR_DAC2_SYNC),
 	.LED(LED)

projects/oscope/common/digitizer_slowread.v

@@ -67,15 +67,14 @@ timestamp ts(.clk(adc_clk), .aux_trig(1'b0), .slow_op(slow_op), .slow_snap(slow_
 // the buffer, tag_old shows it at the begin-time of the buffer.  Not perfect
 // because of non-boxcar filtering and sloppy pipelining.
 reg [7:0] tag_old=0;
-`define SLOW_SR_LEN 17*16
-`define SLOW_SR_DATA { \
-	U3DA_min, U3DA_max, U3DB_min, U3DB_max, U3DC_min, U3DC_max, U3DD_min, U3DD_max, \
-	U2DA_min, U2DA_max, U2DB_min, U2DB_max, U2DC_min, U2DC_max, U2DD_min, U2DD_max, \
+parameter sr_length = 17*16;
+wire [sr_length-1:0] slow_sr_data = {
+	U3DA_min, U3DA_max, U3DB_min, U3DB_max, U3DC_min, U3DC_max, U3DD_min, U3DD_max,
+	U2DA_min, U2DA_max, U2DB_min, U2DB_max, U2DC_min, U2DC_max, U2DD_min, U2DD_max,
 	tag_now, tag_old }
-parameter sr_length = `SLOW_SR_LEN;
 reg [sr_length-1:0] slow_read=0;
 always @(posedge adc_clk) if (slow_op) begin
-	slow_read <= slow_snap ? `SLOW_SR_DATA : {slow_read[sr_length-9:0],timestamp_out};
+	slow_read <= slow_snap ? slow_sr_data : {slow_read[sr_length-9:0],timestamp_out};
 	if (slow_snap) tag_old <= tag_now;
 end
 

rtsim/cav_elec.v

@@ -61,6 +61,7 @@ module cav_elec(
 	input [11:0] modulo,  // external
 	`AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 `AUTOMATIC_decode
 `AUTOMATIC_map

rtsim/cav_mech.v

@@ -17,6 +17,7 @@ module cav_mech(
   output res_clip,
   `AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 `AUTOMATIC_decode
 
@@ -62,4 +63,5 @@ always @(posedge clk) begin
 end
 assign environment = noise_out;
 
+`undef AUTOMATIC_prng
 endmodule // cav_mech

rtsim/cav_mode.v

@@ -62,6 +62,7 @@ module cav_mode(
 	input signed [17:0] bw,  // external
 	`AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 `AUTOMATIC_decode
 

rtsim/station.v

@@ -57,6 +57,7 @@ module station(
   // Local Bus for simulator configuration
   `AUTOMATIC_self
 );
+`undef AUTOMATIC_self
 
 `AUTOMATIC_decode
 
@@ -128,4 +129,5 @@ adc_em #(.del(1)) a_for // auto
 adc_em #(.del(1)) a_rfl // auto
 	(.clk(clk), .strobe(iq), .in(reflect), .rnd(rndb[12: 0]), .adc(a_reflect), `AUTOMATIC_a_rfl);
 
+`undef AUTOMATIC_prng
 endmodule