minor test bench maintenance

chitchat_txrx_wrap_tb.v: clean up tx_valid{0,1} signals, to not abuse flag_xdomain
serial_io/patt_gen_tb.v: don't try to test pgen_rate = 1, to not abuse flag_xdomain

serial_io/chitchat/chitchat_txrx_wrap_tb.v

@@ -113,8 +113,8 @@ module chitchat_txrx_wrap_tb;
       if (tx_transmit_en)
          val_cnt <= val_cnt + 1;
    end
-   assign tx_valid0 = (val_cnt!=0 & (val_cnt % valid_period)==0);
-   assign tx_valid1 = (val_cnt!=0 & (val_cnt % valid_period)==5);
+   assign tx_valid0 = (val_cnt!=0) & ((val_cnt % valid_period)==0) & tx_transmit_en;
+   assign tx_valid1 = (val_cnt!=0) & ((val_cnt % valid_period)==5) & tx_transmit_en;
 
 
    reg  [7:0]  tx_data=0;

serial_io/patt_gen_tb.v

@@ -57,7 +57,7 @@ module patt_gen_tb;
    // ----------------------
    // Generate stimulus
    // ----------------------
-   wire [4:0]  pgen_rate;
+   wire [4:0]  pgen_rate_maybe, pgen_rate;
    wire        pgen_test_mode;
    wire [2:0]  pgen_inc_step;
    wire [15:0] pgen_usr_data;
@@ -89,7 +89,9 @@ module patt_gen_tb;
       end
    end
 
-   assign {pgen_rate, pgen_test_mode, pgen_inc_step, pgen_usr_data} = rand_setup;
+   assign {pgen_rate_maybe, pgen_test_mode, pgen_inc_step, pgen_usr_data} = rand_setup;
+   // pgen_rate = 1 is invalid
+   assign pgen_rate = (pgen_rate_maybe == 1) ? 2 : pgen_rate_maybe;
 
    flag_xdomain i_flag_xdomain (
       .clk1 (tx_clk), .flagin_clk1 (rx_valid),
@@ -131,6 +133,12 @@ module patt_gen_tb;
    reg        rx_valid_dly       [DELAY_DATA-1:0];
    reg [15:0] rx_data_dly        [DELAY_DATA-1:0];
 
+   // Initialize delay pipe so simulation doesn't start with a bunch of Xs
+   integer ix;
+   initial begin
+      for (ix=0; ix<DELAY_DATA; ix=ix+1) rx_valid_dly[ix] = 0;
+   end
+
    integer i;
    always @(posedge cc_clk) begin
       pgen_disable_dly[0]   <= pgen_disable;