Keeping current with master

.github/workflows/build.yml

@@ -18,10 +18,10 @@ jobs:
       fail-fast: false
 
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
 
       - name: Setup python
-        uses: actions/setup-python@v2
+        uses: actions/setup-python@v5
         with:
             python-version: '3.8'
 
@@ -49,13 +49,13 @@ jobs:
           make -C doc html
 
       - name: Deploy gh-pages
-        uses: peaceiris/actions-gh-pages@v3
+        uses: peaceiris/actions-gh-pages@v4
         with:
           github_token: ${{ secrets.GITHUB_TOKEN }}
           publish_dir: ./doc/_build/html
 
       - name: Upload artifacts
-        uses: actions/upload-artifact@v2
+        uses: actions/upload-artifact@v4
         with:
           name: badger-doc
           path: badger/doc/*.svg

.gitlab-ci.yml

@@ -8,8 +8,7 @@ stages:
 variables:
   XILINX_VIVADO: /non-free/Xilinx/Vivado/2020.2
   CI_REGISTRY: mohs.dhcp.lbl.gov
-  CONTAINER_IMAGE: $CI_REGISTRY/testing_base_bookworm
-  # CONTAINER_IM_IMAGE: $CI_REGISTRY/riscv_bloat
+  CONTAINER_IMAGE: $CI_REGISTRY/bedrock_testing_base_bookworm
   DOCKER_HOST: tcp://docker:2375/
   DOCKER_DRIVER: overlay2
 
@@ -19,7 +18,6 @@ services:
   - name: mohs.dhcp.lbl.gov/docker:20.10.12-dind
     command: ["--insecure-registry", "mohs.dhcp.lbl.gov"]
     alias: docker
-#    entrypoint: ["dockerd-entrypoint.sh"]
 
 include:
   - local: .gitlab/ci/badger.gitlab-ci.yml
@@ -38,11 +36,12 @@ include:
   - local: .gitlab/ci/cdc_check.gitlab-ci.yml
   - local: .gitlab/ci/localbus.gitlab-ci.yml
   - local: .gitlab/ci/ctrace.gitlab-ci.yml
+  - local: .gitlab/ci/leep.gitlab-ci.yml
   - local: .gitlab/ci/axi.gitlab-ci.yml
 
 leep_test:
   script:
-    - cd projects/common && python3 -m unittest -v
+    - cd projects/common && PYTHONPATH=../../build-tools python3 -m unittest -v
 
 flake8:
   stage: test

.gitlab/ci/badger.gitlab-ci.yml

@@ -25,4 +25,4 @@ badger_ac701_run:
   dependencies:
     - badger_ac701
   script:
-    - cd badger/tests && test -r ac701_rgmii_vtest.bit && sh teststand_ac701.sh
+    - cd badger/tests && test -r ac701_rgmii_vtest.bit && SERIAL_NUM_OPT="-s 210203356870" sh teststand_ac701.sh

.gitlab/ci/build.gitlab-ci.yml

@@ -15,6 +15,7 @@ build:
         -t $CONTAINER_IMAGE:$CI_PROJECT_NAME-$CI_COMMIT_SHORT_SHA \
         -t $CONTAINER_IMAGE:latest \
         .
+    docker run --rm $CONTAINER_IMAGE bash -c 'echo -n "Debian version: "; cat "/etc/debian_version"'
     docker push $CONTAINER_IMAGE:$CI_COMMIT_REF_NAME
     docker push $CONTAINER_IMAGE:$CI_PROJECT_NAME-$CI_COMMIT_SHORT_SHA
     docker push $CONTAINER_IMAGE:latest

.gitlab/ci/comms_top.gitlab-ci.yml

@@ -40,4 +40,4 @@ gige_sfp_ac701_run:
   dependencies:
     - gige_sfp_ac701
   script:
-    - cd projects/comms_top/gige_eth && make hwload_ac701 && make hwtest_ac701
+    - cd projects/comms_top/gige_eth && make hwload_ac701 SERIAL_NUM_OPT="-s 210203356870" && sleep 7 && make hwtest_ac701

.gitlab/ci/leep.gitlab-ci.yml

@@ -0,0 +1,4 @@
+leep_test2:
+  stage: test
+  script:
+    - make -C projects/common/leep && make -C projects/common/leep clean

.gitlab/ci/oscope.gitlab-ci.yml

@@ -5,6 +5,20 @@ oscope_top_test:
   script:
     - make Voscope_top_tb && make Voscope_top_leep && make clean
 
+# We know the design doesn't yet get evaluated as CDC-clean, at least in part
+# due to Verilog inout ports being poorly supported by our tools.
+# Please take out the error bypass (echo) if this ever gets fixed.
+oscope_cdc:
+  before_script:
+    - cd projects/oscope/marble_family
+  stage: test
+  script:
+    - make dep && make oscope_prep_yosys.json && (make oscope_prep_cdc.txt || echo "Found CDC violation, as expected; continuing")
+  artifacts:
+    expire_in: 1 week
+    paths:
+      - projects/oscope/marble_family/oscope_prep_cdc.txt
+
 oscope_top_bmb7:
   before_script:
     - cd projects/oscope/bmb7_cu && ls /non-free
@@ -29,17 +43,15 @@ oscope_top_marble:
     paths:
       - projects/oscope/marble_family/oscope_top.bit
 
+# LITEX_INSTALL_PATH is defined in the Docker image
 marble_ddr3_test:
   stage: synthesis
   before_script:
-    - apt-get update && apt-get install -y ninja-build && pip3 install meson==0.64.1
-    - mkdir /litex_setup_dir
-    - (BD=$PWD && cd /litex_setup_dir && sh $BD/build-tools/litex_meta.sh)
-    - cd /litex_setup_dir/litex-boards/litex_boards/targets
+    - cd $LITEX_INSTALL_PATH/litex-boards/litex_boards/targets
   script:
     - XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE PATH=$XILINX_VIVADO/bin:$PATH && python3 berkeleylab_marble.py --build
     - echo $CI_PROJECT_DIR
-    - cp /litex_setup_dir/litex-boards/litex_boards/targets/build/berkeleylab_marble/gateware/berkeleylab_marble.bit $CI_PROJECT_DIR/
+    - cp $LITEX_INSTALL_PATH/litex-boards/litex_boards/targets/build/berkeleylab_marble/gateware/berkeleylab_marble.bit $CI_PROJECT_DIR/
   artifacts:
     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
     expire_in: 1 week
@@ -50,9 +62,6 @@ marble_ddr3_test:
 litex_trigger_capture:
   stage: synthesis
   before_script:
-    - apt-get update && apt-get install -y ninja-build && pip3 install meson==0.64.1
-    - mkdir /litex_setup_dir
-    - (BD=$PWD && cd /litex_setup_dir && sh $BD/build-tools/litex_meta.sh)
     - cd projects/trigger_capture
   script:
     XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE PATH=$XILINX_VIVADO/bin:$PATH && make marble.bit

CONTRIBUTING.md

@@ -105,7 +105,7 @@ a git commit ID (or similar) instead.
 PDF and object files often take extra effort to make reproducible.
 
 FPGA bitfiles are not typically shown to be reproducible, but Xilinx
-[acknowledges](https://support.xilinx.com/s/article/61599) that is a
+[acknowledges](https://adaptivesupport.amd.com/s/article/61599?language=en_US) that is a
 reasonable goal (they call it "repeatable").
 Our toolchain has demonstrated this working in at least couple of cases.
 
@@ -121,7 +121,7 @@ We're not the first group to deal with this topic. The following are
 useful resources:
 
 1. [Linux kernel coding style guide](https://www.kernel.org/doc/html/v4.10/process/coding-style.html) many of the concepts it discusses have general applicability.
-2. [Google python guide](http://google.github.io/styleguide/pyguide.html) and [PEP8](https://www.python.org/dev/peps/pep-0008/)
+2. [Google python guide](https://google.github.io/styleguide/pyguide.html) and [PEP8](https://www.python.org/dev/peps/pep-0008/)
 3. [GNU Coding Standards: Makefile Conventions](https://www.gnu.org/prep/standards/html_node/Makefile-Conventions.html)
 
 Please spell-check your code, comments, and documentation.
@@ -164,7 +164,7 @@ to represent logical indentation level has advantages; people's setting of tab
 width can systematically and locally adjust the visual indentation level. Just
 like Wikipedia's English vs. American spelling policy, don't gratuitously
 change the tab vs. spaces convention of a file.  See also
-[Silicon Valley - S03E06 - Tabs versus Spaces](https://www.youtube.com/watch?v=SsoOG6ZeyUI) (2:50).
+[Silicon Valley - S03E06 - Tabs versus Spaces](https://www.youtube.com/watch?v=cowtgmZuai0) (2:01).
 
 Special case for python files:
   No tabs, per [PEP8](https://www.python.org/dev/peps/pep-0008/)

Dockerfile

@@ -1,4 +1,4 @@
-FROM debian:bookworm-slim as testing_base_bookworm
+FROM debian:12.8-slim AS testing_base_bookworm
 
 # Vivado needs libtinfo5, at least for Artix?
 RUN apt-get update && \
@@ -114,3 +114,33 @@ RUN apt-get update && \
         libidn12 && \
     rm -rf /var/lib/apt/lists/* && \
     ln -s libidn.so.12 /usr/lib/x86_64-linux-gnu/libidn.so.11
+
+# Install litex
+RUN apt-get update && \
+    apt-get install -y \
+        ninja-build \
+        gcc-aarch64-linux-gnu \
+        ghdl && \
+    rm -rf /var/lib/apt/lists/* && \
+    pip3 install \
+        meson
+
+COPY build-tools/litex_meta.sh /
+
+ENV LITEX_INSTALL_PATH=/litex
+
+RUN mkdir ${LITEX_INSTALL_PATH} && \
+    cd ${LITEX_INSTALL_PATH} && \
+    sh /litex_meta.sh
+
+# Install sv2v
+RUN apt-get update && \
+    apt-get install -y \
+        haskell-stack && \
+    rm -rf /var/lib/apt/lists/* && \
+    git clone https://github.com/zachjs/sv2v /sv2v && \
+    cd /sv2v && \
+    git checkout 7808819c48c167978aeb5ef34c6e5ed416e90875 && \
+    make && \
+    rm -rf $HOME/.stack && \
+    cp bin/sv2v /usr/local/bin/

README.md

@@ -1,7 +1,7 @@
 Overview
 ========
 
-Bedrock generated documentation: https://berkeleylab.github.io/Bedrock
+Bedrock generated documentation: https://berkeleylab.github.io/Bedrock/
 
 [Bedrock](https://gitlab.lbl.gov/hdl-libraries/bedrock) is largely an accumulation
 of Verilog codebase written over the past several years at LBNL. It contains
@@ -33,9 +33,9 @@ A few comments regarding the codebase
 1. All software is set up to easily run on *nix systems.
 2. Currently everything is [built using GNU Make](build-tools/makefile.md).
 We are on an active lookout for other methods, if they're actually better for us.
-3. iverilog is used for simulation. We are slowly starting to use [Verilator](https://www.veripool.org/wiki/verilator) as well
+3. iverilog is used for simulation. We are slowly starting to use [Verilator](https://www.veripool.org/verilator/) as well
 (see badger)
-4. Xilinx tools are used for synthesis, and starting to support [YoSys](http://www.clifford.at/yosys/) (again see badger)
+4. Xilinx tools are used for synthesis, and starting to support [YoSys](https://yosyshq.net/yosys/) (again see badger)
 5. This repository is connected to Gitlab CI. All simulation based tests run
 automatically upon every commit on the continuous integration server. This helps
 us move faster (without breaking things).  A helpful subset of those tests

badger/README.md

@@ -139,7 +139,7 @@ Demonstrating both Packet Badger functionality, and the test framework's
 ability to attach the simulation to the host's Ethernet subsystem.
 
 Your development machine needs to provide a traditional unix-y environment,
-e.g., make, cc, python, awk, cmp.  Also some version of [Icarus Verilog](http://iverilog.icarus.com/); see [status.md](status.md) for more details.
+e.g., make, cc, python, awk, cmp.  Also some version of [Icarus Verilog](https://steveicarus.github.io/iverilog/); see [status.md](status.md) for more details.
 
 In one shell session (Linux terminal), try:
 

badger/crc8e_guts.v

@@ -7,7 +7,7 @@ module crc8e_guts(
 	output [7:0] d_out,
 	output zero
 );
-// http://en.wikipedia.org/wiki/Cyclic_redundancy_check
+// https://en.wikipedia.org/wiki/Cyclic_redundancy_check
 parameter wid=32;
 parameter init=32'hffffffff;
 

badger/doc/Makefile

@@ -1,6 +1,7 @@
 # Commentary in ../tests/Makefile
 XCIRCUIT = xcircuit
 XVFB = xvfb-run -a -s "-screen 0 1440x900x24"
+PANDOC = pandoc
 
 all: svg
 .PHONY: svg html
@@ -14,10 +15,10 @@ html: ../index.html ../status.html
 	echo "page load $<; svg; exit" > .xcircuitrc; $(XVFB) $(XCIRCUIT); rm .xcircuitrc
 
 ../index.html: ../README.md
-	pandoc -t html $< | sed -e 's,status\.md,status.html,g' > $@
+	$(PANDOC) -t html $< | sed -e 's,status\.md,status.html,g' > $@
 
 ../status.html: ../status.md
-	pandoc -t html -o $@ $<
+	$(PANDOC) -t html -o $@ $<
 
 clean:
 	rm -f *.svg *.html

badger/tests/Makefile

@@ -38,7 +38,6 @@ VLATOR_LINT_IGNORE += -Wno-UNUSED -Wno-DECLFILENAME
 # Configuration not covered (yet?) by Bedrock's top_rules.mk
 VCD_ARGS = $(VCD_ARGS_$@)
 VVP_FLAGS = ${VVP_FLAGS_$@} ${VCD_ARGS_$@}
-PERL = perl
 XCIRCUIT = xcircuit
 # XXX consider converting this to something more compatible with Bedrock's VIVADO_SYNTH.
 VIVADOEXEC = vivado
@@ -89,10 +88,10 @@ crc_selfcheck: crc_selfcheck.o crc32.o
 derive_tb: crc_genguts.vh
 
 crc_genguts.vh: crc_derive
-	./$^ 16 0x1021 32 > $@
+	./$< 16 0x1021 32 > $@
 
 crc8e_guts.vh: crc_derive
-	./$^ -lsb 32 0x04C11DB7 8 > $@
+	./$< -lsb 32 0x04C11DB7 8 > $@
 
 # New feature compared to PSPEPS: no include file (or path) needed!
 # crc8e_guts.v is pre-filled in.  The following steps give its derivation

badger/tests/ac701/ac701_rgmii.xdc

@@ -15,7 +15,7 @@ set_property -dict {PACKAGE_PIN U15 IOSTANDARD HSTL_I_18} [get_ports {RGMII_TXD[
 set_property -dict {PACKAGE_PIN T18 IOSTANDARD HSTL_I_18} [get_ports {RGMII_TXD[2]}]
 set_property -dict {PACKAGE_PIN T17 IOSTANDARD HSTL_I_18} [get_ports {RGMII_TXD[3]}]
 
-# https://www.xilinx.com/support/answers/53092.html
+# https://adaptivesupport.amd.com/s/article/53092?language=en_US
 set_property IOB TRUE [get_ports {RGMII_TXD[*]}]
 set_property IOB TRUE [get_ports RGMII_TX_CTRL]
 set_property IOB TRUE [get_ports {RGMII_RXD[*]}]

badger/tests/badger.tcl

@@ -8,7 +8,7 @@ proc project_rpt {dest_dir} {
     report_datasheet -v -file $dest_dir/imp_datasheet.rpt
     report_cdc -v -details -file $dest_dir/cdc_report.rpt
     report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -file $dest_dir/imp_timing.rpt
-    # http://xillybus.com/tutorials/vivado-timing-constraints-error
+    # https://xillybus.com/tutorials/vivado-timing-constraints-error
     if {! [string match -nocase {*timing constraints are met*} [report_timing_summary -no_header -no_detailed_paths -return_string]]} {
         puts "Timing constraints weren't met. Please check your design."
         exit 2

badger/tests/cluster_run.gold

@@ -1,9 +1,9 @@
 a3633a315dc8a61e6c2c81b0433258e71dcb43ad
 a3633a315dc8a61e6c2c81b0433258e71dcb43ad
 a3633a315dc8a61e6c2c81b0433258e71dcb43ad
-scratch_out  00001e61
-scratch_in_r  00001e61
-scratch_out  000022b8
-scratch_in_r  000022b8
-scratch_out  0000270f
-scratch_in_r  0000270f
+scratch_out  1e61
+scratch_in_r  1e61
+scratch_out  22b8
+scratch_in_r  22b8
+scratch_out  270f
+scratch_in_r  270f

badger/tests/crc8e_guts_x.v

@@ -7,7 +7,7 @@ module crc8e_guts(
 	output [7:0] d_out,
 	output zero
 );
-// http://en.wikipedia.org/wiki/Cyclic_redundancy_check
+// https://en.wikipedia.org/wiki/Cyclic_redundancy_check
 parameter wid=32;
 parameter init=32'hffffffff;
 

badger/tests/gtkw_print.tcl

@@ -4,6 +4,6 @@ set n1 [ string length $fn ]
 set n2 [ string last ".vcd" $fn ]
 if { $n2+4==$n1 } { set fpdf [ string range $fn 0 [ expr $n2-1 ] ] } else { set fpdf $fn }
 append fpdf ".pdf"
-# https://github.com/acklinr/gtkwave/blob/master/examples/des.tcl
+# https://github.com/gtkwave/gtkwave/blob/master/examples/des.tcl
 gtkwave::/File/Print_To_File PDF {Letter (8.5" x 11")} Full $fpdf
 gtkwave::/File/Quit

badger/tests/kc705/ODDR.v

@@ -1,5 +1,5 @@
 // pathetic model of Xilinx DDR output cell
-// ignores set and reset inputs
+// ignores set and reset inputs, and the SRTYPE and DDR_CLK_EDGE parameters
 module ODDR (
 	input S,
 	input R,
@@ -14,10 +14,11 @@ parameter DDR_CLK_EDGE = "SAME_EDGE";
 parameter INIT = 0;
 parameter SRTYPE = "SYNC";
 
-reg qx=INIT, hold=INIT;
-always @(posedge C) if (CE) qx <= D1;
-always @(posedge C) if (CE) hold <= D2;
-always @(negedge C) qx <= hold;
-assign Q = qx;
+reg hold1=INIT, hold2=INIT;
+always @(posedge C) if (CE) begin
+	hold1 <= D1;
+	hold2 <= D2;
+end
+assign Q = C ? hold1 : hold2;
 
 endmodule

badger/tests/kc705/kc705_gmii.xdc

@@ -26,7 +26,7 @@ set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS25} [get_ports {GMII_TXD[5]
 set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS25} [get_ports {GMII_TXD[6]}]
 set_property -dict {PACKAGE_PIN J28 IOSTANDARD LVCMOS25} [get_ports {GMII_TXD[7]}]
 
-# https://www.xilinx.com/support/answers/53092.html
+# https://adaptivesupport.amd.com/s/article/53092?language=en_US
 set_property IOB TRUE [get_ports GMII_TXD[*]]
 set_property IOB TRUE [get_ports GMII_TX_EN]
 set_property IOB TRUE [get_ports GMII_RXD[*]]

badger/tests/teststand_ac701.sh

@@ -4,7 +4,7 @@
 # Tested useful for the CI test stand (mohs) at LBNL.
 # Can also act as a template for other use cases.
 set -e
-xc3sprog -c jtaghs1_fast ac701_rgmii_vtest.bit
+xc3sprog -c jtaghs1_fast $SERIAL_NUM_OPT ac701_rgmii_vtest.bit
 echo "So far so good"
 sleep 8
 echo "Hope links are up"

badger/tests/udp_model.c

@@ -110,7 +110,7 @@ void udp_receiver(int *in_octet, int *in_valid, int *in_count, int thinking)
 
 struct udp_state *udp_setup_r(unsigned short udp_port_, int badger_client_)
 {
-	struct udp_state *ust = US_P calloc(sizeof (struct udp_state), 1);
+	struct udp_state *ust = US_P calloc(1, sizeof (struct udp_state));
 	ust->sleepctr=0;
 	ust->sleepmax=10;
 	fprintf(stderr, "udp_receiver initializing UDP port %u. Interface mode: ", udp_port_);
@@ -121,8 +121,8 @@ struct udp_state *udp_setup_r(unsigned short udp_port_, int badger_client_)
 	}
 	ust->badger_client = badger_client_;
 	/* following could be combined by making second argument to calloc a 2? */
-	struct pbuf *inbuf  = ust->inbuf  = PBUF_P calloc(sizeof(struct pbuf), 1);
-	struct pbuf *outbuf = ust->outbuf = PBUF_P calloc(sizeof(struct pbuf), 1);
+	struct pbuf *inbuf  = ust->inbuf  = PBUF_P calloc(1, sizeof(struct pbuf));
+	struct pbuf *outbuf = ust->outbuf = PBUF_P calloc(1, sizeof(struct pbuf));
 	if (!inbuf || !outbuf) {
 		perror("calloc");
 		exit(1);