gige_top.v: Minor clean-up

BerkeleyLab · Dec 10, 2024 · a667fe7 · a667fe7
1 parent 93093b0
commit a667fe7
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diff --git a/projects/comms_top/gige_eth/Makefile b/projects/comms_top/gige_eth/Makefile
@@ -17,7 +17,7 @@ VERILOG_DEFINE_FLAGS =
 include $(COMMS_TOP_DIR)/rules.mk
 include $(BUILD_DIR)/top_rules.mk
 
-all: gen $(APP_NAME).bit
+all: $(APP_NAME).bit
 
 $(APP_NAME).bit: $(IP_TCL)
 

diff --git a/projects/comms_top/gige_eth/gige_top.v b/projects/comms_top/gige_eth/gige_top.v
@@ -59,6 +59,7 @@ module gige_top (
    gtp_sys_clk_mmcm i_gtp_sys_clk_mmcm (
       .clk_in  (sys_clk_fast),
       .sys_clk (sys_clk), // Buffered 50 MHz
+      .reset   (1'b0),
       .locked  ()
    );
 `else