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BoChen-Ye/README.md
  • 👋 Hi, I’m Bochen, a Master student in TU/e, Netherlands.
  • 👀 I’m interested in ASIC/SoC/FPGA Design.
  • 🤔 I'm also looking for PhD position or full-time postion at company in related area.
  • 🔭 I’m currently working on a new protocol @ NXP. Before that, I am a intern @ Synopsys for ECC hardware codec.
  • 🌱 I plan to learn SoC, ASIC accelerator for deep learning, Neuromorphic hardware, Multi-core Architecture with NoC.
  • 💞️ I’m looking to collaborate on RTL design/verification.
  • 📫 How to reach me: b.ye@student.tue.nl / y19966505415@163.com

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  1. Tiny_SoC Public

    This is my hobby project, which contain my rsic-v core and my convolutional layer with AMBA bus

    Verilog 3

  2. Tiny_LeViT_Hardware_Accelerator Public

    This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.

    SystemVerilog 11

  3. OpenSoCFabric Public

    Forked from schoeberl/OpenSoCFabric

    OpenSoC Fabric - A Network-On-Chip Generator

    Scala 4

  4. RISC-V-five-stage-CPU Public

    This is a project base on book 'Digital design and computer architure RISC-V edition'. I use Verilog to build RISC-V CPU.

    Verilog 3

  5. BoChen-Ye.github.io Public

    Forked from RayeRen/acad-homepage.github.io

    AcadHomepage: A Modern and Responsive Academic Personal Homepage

    SCSS 1