end_wait_cycles

Type

Integer

Default

0

Description

Specifies the number of clock cycles to wait after the end condition.

Impact

The settings are designed to record additional clock cycles even after the end condition via specific signals is fullfilled.

Examples

"simulation": {
    "end_condition": {
        "signals": {
            "name": "done",
            "value": "1'b1"
        }
    },
    "end_wait_cycles": 2
}

In this example, the simulation terminates one clock cycle after the done signal is set to one.