Add time and instret to perf counter delegation

Currently, we can only delegate the cycle register in Miralis when delegating the perf counter. This commit adds the two other registers and delegates the perf counters on the VisionFive2 board in the release build.

src/virt/emulator.rs

@@ -494,6 +494,7 @@ impl VirtContext {
                 let instr = unsafe { get_raw_faulting_instr(&self.trap_info) };
                 log::warn!("IllegalInstruction {:x}", instr);
                 assert!(Arch::read_csr(Csr::Mcounteren) >= 7,"Good");
+                assert!(Arch::read_csr(Csr::Mcounteren) >= 7,"Good2");
                 self.emulate_jump_trap_handler()
             }
             _ => self.emulate_jump_trap_handler(),