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SN32 USB LLD: flexibility updates #410

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Merged
fpoussin merged 9 commits into from
Oct 22, 2024
Merged

SN32 USB LLD: flexibility updates #410

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1af0960
sn32: usb: update registers for max 7+1 endpoints
dexter93 Aug 10, 2024
bafbd84
sn32: usb: respect read only registers
dexter93 Aug 10, 2024
ddd5df1
sn32: usb: dynamically handle NAK/ACK EPs
dexter93 Aug 10, 2024
ec0f1e8
sn32: usb: add undocumented register bits
dexter93 Aug 10, 2024
bdb8a5b
sn32: usb: add direct sram access support
dexter93 Jun 12, 2024
c761cc4
sn32: usb: Update supported chip list and provide configs
dexter93 Aug 10, 2024
1651d4a
sn32: usb: use the vendor provided address mask
dexter93 Aug 10, 2024
568afac
sn32: usb: add special init for 240
dexter93 Aug 10, 2024
1b165fc
sn32: usb: prefer UINT32_MAX over hardcoded value
dexter93 Aug 10, 2024
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46 changes: 33 additions & 13 deletions os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ static const USBEndpointConfig ep0config = {
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/

uint32_t msk_EP_NAK, msk_EP_ACK;
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
Expand Down Expand Up @@ -137,6 +137,11 @@ static void sn32_usb_read_fifo(usbep_t ep, uint8_t *buf, size_t sz, bool intr) {
if (off + chunk > sz)
chunk = sz - off;

#if (SN32_USB_DIRECT_SRAM == TRUE)
volatile uint32_t *sram;
sram = (volatile uint32_t *)(SN32_USBRAM_BASE + off + ep_offset);
data = *sram;
#else
if(intr) {
SN32_USB->RWADDR = off + ep_offset;
SN32_USB->RWSTATUS = 0x02;
Expand All @@ -149,7 +154,7 @@ static void sn32_usb_read_fifo(usbep_t ep, uint8_t *buf, size_t sz, bool intr) {
while (SN32_USB->RWSTATUS2 & 0x02);
data = SN32_USB->RWDATA2;
}

#endif
//dest, src, size
memcpy(buf, &data, chunk);

Expand Down Expand Up @@ -180,6 +185,11 @@ static void sn32_usb_write_fifo(usbep_t ep, const uint8_t *buf, size_t sz, bool
//dest, src, size
memcpy(&data, buf, chunk);

#if (SN32_USB_DIRECT_SRAM == TRUE)
volatile uint32_t *sram;
sram = (volatile uint32_t *)(SN32_USBRAM_BASE + off + ep_offset);
*sram = data;
#else
if(intr) {
SN32_USB->RWADDR = off + ep_offset;
SN32_USB->RWDATA = data;
Expand All @@ -192,7 +202,7 @@ static void sn32_usb_write_fifo(usbep_t ep, const uint8_t *buf, size_t sz, bool
SN32_USB->RWSTATUS2 = 0x01;
while (SN32_USB->RWSTATUS2 & 0x01);
}

#endif
off += chunk;
buf += chunk;
}
Expand Down Expand Up @@ -306,7 +316,7 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
/////////////////////////////////////////////////
/* Device Status Interrupt (EPnACK) */
/////////////////////////////////////////////////
if (iwIntFlag & (mskEP6_ACK|mskEP5_ACK|mskEP4_ACK|mskEP3_ACK|mskEP2_ACK|mskEP1_ACK)) {
if (iwIntFlag & msk_EP_ACK) {
// Determine the interrupting endpoint, direction, and clear the interrupt flag
for(usbep_t ep = 1; ep <= USB_MAX_ENDPOINTS; ep++) {
if (iwIntFlag & mskEPn_ACK(ep)){
Expand All @@ -315,9 +325,8 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
}
}
}
if (iwIntFlag & (mskEP6_NAK|mskEP5_NAK|mskEP4_NAK|mskEP3_NAK|mskEP2_NAK|mskEP1_NAK)) {
SN32_USB->INSTSC = (mskEP6_NAK|mskEP5_NAK|mskEP4_NAK|mskEP3_NAK|mskEP2_NAK|mskEP1_NAK);

if (iwIntFlag & msk_EP_NAK) {
SN32_USB->INSTSC = msk_EP_NAK;
}

}
Expand Down Expand Up @@ -451,6 +460,9 @@ void usb_lld_start(USBDriver *usbp) {
/* Powers up the transceiver while holding the USB in reset state.*/
SN32_USB->SGCTL = (mskBUS_DRVEN|mskBUS_J_STATE);
SN32_USB->CFG = (mskVREG33_EN|mskPHY_EN|mskDPPU_EN|mskSIE_EN|mskESD_EN);
# if defined(SN32F240)
SN32_USB->CFG |= (mskUSBRAM_EN|mskVREG33DIS_EN);
# endif
/* Set up hardware configuration.*/
SN32_USB->PHYPRM = 0x80000000;
SN32_USB->PHYPRM2 = 0x00004004;
Expand All @@ -470,10 +482,18 @@ void usb_lld_start(USBDriver *usbp) {
if (usbp->config->sof_cb != NULL) {
SN32_USB->INTEN |= mskUSB_SOF_IE;
}
//SN32_USB->INTEN |= (mskEP1_NAK_EN|mskEP2_NAK_EN|mskEP3_NAK_EN|mskEP4_NAK_EN);
#if (USB_ENDPOINTS_NUMBER > 4)
//SN32_USB->INTEN |= (mskEP5_NAK_EN|mskEP6_NAK_EN);
#endif /* (USB_ENDPOINTS_NUMBER > 4) */
/* Calculate EP ACK, NAK, NAK_EN flags.*/
msk_EP_NAK = 0;
msk_EP_ACK = 0;
//uint32_t msk_EP_NAK_EN = 0;
for(usbep_t ep = 1; ep <= USB_MAX_ENDPOINTS; ep++) {
msk_EP_NAK |= mskEPn_NAK(ep);
msk_EP_ACK |= mskEPn_ACK(ep);
// msk_EP_NAK_EN |= mskEPn_NAK_EN(ep);
}
/* Enable NAK EP interrupts.*/
// Disabled for now.
// SN32_USB->INTEN |= msk_EP_NAK_EN;
}
}

Expand Down Expand Up @@ -506,7 +526,7 @@ void usb_lld_stop(USBDriver *usbp) {
*/
void usb_lld_reset(USBDriver *usbp) {
/* Post reset initialization.*/
SN32_USB->INSTSC = (0xFFFFFFFF);
SN32_USB->INSTSC = (UINT32_MAX);

/* Set the address to zero during enumeration.*/
usbp->address = 0;
Expand All @@ -529,7 +549,7 @@ void usb_lld_reset(USBDriver *usbp) {
*/
void usb_lld_set_address(USBDriver *usbp) {

SN32_USB->ADDR = usbp->address & 0x7F;
SN32_USB->ADDR = usbp->address & mskUADDR;
}

/**
Expand Down
7 changes: 7 additions & 0 deletions os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.h
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,13 @@
#if !defined(SN32_USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
#define SN32_USB_HOST_WAKEUP_DURATION 2
#endif

/**
* @brief USB driver using SRAM direct.
*/
#if !defined(SN32_USB_DIRECT_SRAM) || defined(__DOXYGEN__)
#define SN32_USB_DIRECT_SRAM FALSE
#endif
/** @} */

/*===========================================================================*/
Expand Down
85 changes: 50 additions & 35 deletions os/hal/ports/SN32/LLD/SN32F2xx/USB/sn32_usb.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,45 +32,51 @@
* @brief Number of the available endpoints.
* @details This value does not include the endpoint 0 which is always present.
*/
#define HAL_MAX_ENDPOINTS 6
#define HAL_MAX_ENDPOINTS 7
#if (defined(SN32F240B) || defined(SN32F260))
#define USB_ENDPOINTS_NUMBER 4
#define SN32_USB_PMA_SIZE 256
#elif (defined(SN32F280) || defined(SN32F290))
#define USB_ENDPOINTS_NUMBER HAL_MAX_ENDPOINTS
#define SN32_USB_PMA_SIZE 512
# define USB_ENDPOINTS_NUMBER 4
# define SN32_USB_PMA_SIZE 256
#elif defined(SN32F240C)
# define USB_ENDPOINTS_NUMBER HAL_MAX_ENDPOINTS
# define SN32_USB_PMA_SIZE 512
#elif (defined(SN32F240) || defined(SN32F280) || defined(SN32F290))
# define USB_ENDPOINTS_NUMBER 6
# define SN32_USB_PMA_SIZE 512
#else
#error "USB driver not supported in the selected device"
# error "USB driver not supported in the selected device"
#endif

/**
* @brief USB registers block.
*/
typedef struct {
volatile uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */
volatile uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */
volatile uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear Register */
volatile uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */
volatile uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */
volatile uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */
volatile uint32_t EPCTL[HAL_MAX_ENDPOINTS +1]; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0-6 Control Registers */
volatile uint32_t RESERVED[2];
volatile uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */
volatile uint32_t RESERVED1[2];
volatile uint32_t EPBUFOS[HAL_MAX_ENDPOINTS]; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1-6 Buffer Offset Registers */
volatile uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */
volatile uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */
volatile uint32_t RESERVED3;
volatile uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter 2 Register */
volatile uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */
volatile uint32_t RESERVED4;
volatile uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */
volatile uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */
volatile uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */
volatile uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */
volatile uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */
volatile uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */
} sn32_usb_t; /*!< Size = 144 (0x90) */
volatile uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */
volatile const uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */
volatile uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear Register */
volatile uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */
volatile uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */
volatile uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */
volatile uint32_t EPCTL[USB_ENDPOINTS_NUMBER +1]; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0-7 Control Registers */
volatile const uint32_t RESERVED[HAL_MAX_ENDPOINTS - USB_ENDPOINTS_NUMBER + 1];
volatile uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */
volatile const uint32_t RESERVED1[2];
volatile uint32_t EPBUFOS[USB_ENDPOINTS_NUMBER]; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1-7 Buffer Offset Registers */
#if (USB_ENDPOINTS_NUMBER != HAL_MAX_ENDPOINTS)
volatile uint32_t RESERVED2[HAL_MAX_ENDPOINTS - USB_ENDPOINTS_NUMBER - 1];
#endif
volatile const uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */
volatile uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */
volatile const uint32_t RESERVED3;
volatile uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter 2 Register */
volatile uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */
volatile const uint32_t RESERVED4;
volatile uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */
volatile uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */
volatile uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */
volatile uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */
volatile uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */
volatile uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */
} sn32_usb_t; /*!< Size = 144 (0x90) */

/** @} */

Expand All @@ -93,10 +99,19 @@
* @brief Pointer to the USB RAM.
*/
#define SN32_USBRAM ((sn32_usb_pma_t *)SN32_USBRAM_BASE)
#define mskEPn_NAK(ep) (0x1<<(ep -1))
#define mskEPn_ACK(ep) (0x1<<(8+(ep-1)))
#define mskEPn_DIR(ep) (0x1<<(ep-1))
#define mskEPn_DATA_TOGGLE(ep) (0x1<<(ep-1))
/**
* @brief USB EP handling.
*/
/* USB Interrupt Event Status Bit Definitions <USB_INSTS/USB_INSTSC> */
#define mskEPn_NAK(ep) (0x1<<(ep -1))
#define mskEPn_ACK(ep) (0x1<<(8+(ep-1)))
/* USB Configuration Bit Definitions <USB_CFG> */
#define mskEPn_DIR(ep) (0x1<<(ep-1))
/* USB Endpoint Data Toggle Bit Definitions <USB_EPTOGGLE> */
#define mskEPn_DATA_TOGGLE(ep) (0x1<<(ep-1))
/* USB Interrupt Enable Bit Definitions <USB_INTEN> */
#define mskEPn_NAK_EN(ep) mskEPn_NAK(ep)
#define mskEPnACK_EN (0x1<<USB_ENDPOINTS_NUMBER)

#define EPCTL_SET_STAT_ACK(ep, bBytecnt) \
SN32_USB->EPCTL[ep] = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_ACK|bBytecnt)
Expand Down
38 changes: 2 additions & 36 deletions os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5,35 +5,12 @@
#define __USBHW_H__

/* USB Interrupt Enable Bit Definitions <USB_INTEN> */
#define mskEP1_NAK_EN (0x1<<0)
#define mskEP2_NAK_EN (0x1<<1)
#define mskEP3_NAK_EN (0x1<<2)
#define mskEP4_NAK_EN (0x1<<3)
#define mskEP5_NAK_EN (0x1<<4)
#define mskEP6_NAK_EN (0x1<<5)
#define mskEPnACK_EN (0x1<<6)

#define mskBUSWK_IE (0x1<<28)
#define mskUSB_IE (0x1<<29)
#define mskUSB_SOF_IE (0x1<<30)
#define mskBUS_IE (0x1U<<31)

/* USB Interrupt Event Status Bit Definitions <USB_INSTS/USB_INSTSC> */
#define mskEP1_NAK (0x1<<0)
#define mskEP2_NAK (0x1<<1)
#define mskEP3_NAK (0x1<<2)
#define mskEP4_NAK (0x1<<3)
#define mskEP5_NAK (0x1<<4)
#define mskEP6_NAK (0x1<<5)

#define mskEP1_ACK (0x1<<8)
#define mskEP2_ACK (0x1<<9)
#define mskEP3_ACK (0x1<<10)
#define mskEP4_ACK (0x1<<11)
#define mskEP5_ACK (0x1<<12)
#define mskEP6_ACK (0x1<<13)


#define mskERR_TIMEOUT (0x1<<17)
#define mskERR_SETUP (0x1<<18)
#define mskEP0_OUT_STALL (0x1<<19)
Expand All @@ -52,13 +29,8 @@
#define mskUADDR (0x7F<<0)

/* USB Configuration Bit Definitions <USB_CFG> */
#define mskEP1_DIR (0x1<<0)
#define mskEP2_DIR (0x1<<1)
#define mskEP3_DIR (0x1<<2)
#define mskEP4_DIR (0x1<<3)
#define mskEP5_DIR (0x1<<4)
#define mskEP6_DIR (0x1<<5)

#define mskVREG33DIS_EN (0x1<<24)
#define mskUSBRAM_EN (0x1<<25)
#define mskDIS_PDEN (0x1<<26)
#define mskESD_EN (0x1<<27)
#define mskSIE_EN (0x1<<28)
Expand All @@ -85,12 +57,6 @@
#define mskEPn_ENDP_STATE_STALL (0x3<<29)
#define mskEPn_ENDP_EN (0x1U<<31)

/* USB Endpoint Data Toggle Bit Definitions <USB_EPTOGGLE> */
#define mskEP1_CLEAR_DATA0 (0x1<<0)
#define mskEP2_CLEAR_DATA0 (0x1<<1)
#define mskEP3_CLEAR_DATA0 (0x1<<2)
#define mskEP4_CLEAR_DATA0 (0x1<<3)

/* USB Endpoint n Buffer Offset Bit Definitions <USB_EPnBUFOS> */
#define mskEPn_OFFSET (0x1FF<<0)

Expand Down