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Merged
merged 8 commits into from
Sep 16, 2025
Merged

Changes for automatic generation of the simulator #57

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b099336
Use chipflow-lib interface-type signatures
robtaylor Jul 25, 2025
44e20c4
update mcu_soc events_reference.json for peripheral names to match de…
robtaylor Jul 27, 2025
bb19413
Update mcu_soc tests to match design's names
robtaylor Jul 28, 2025
027de80
Attach generated software to flash for simulation
robtaylor Jul 28, 2025
086a8ce
Fix mcu_soc to use attached_simulation_data
robtaylor Jul 31, 2025
97804f4
Remove amaranth-cv32e40p dependency - now included in chipflow-digita…
robtaylor Jul 30, 2025
be2a4dc
delete old simulator code
robtaylor Sep 10, 2025
5aa0108
Make gitignore a bit more useful
robtaylor Sep 10, 2025
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7 changes: 6 additions & 1 deletion .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -2,12 +2,17 @@
__pycache__/
*.egg-info
/dist
.coverage

# pdm
/.pdm-plugins
/.pdm-python
/.pdm-build
/.venv
/.env*
/.env.*
/overrides.txt


# pytest
/.pytest_cache
Expand All @@ -25,4 +30,4 @@ __pycache__/
*.gtkw

# misc
log
log
43 changes: 19 additions & 24 deletions mcu_soc/design/design.py
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Original file line number Diff line number Diff line change
@@ -1,3 +1,5 @@
from pprint import pformat

from chipflow_lib.platforms.sim import SimPlatform
from chipflow_lib.software.soft_gen import SoftwareGenerator

Expand All @@ -11,34 +13,21 @@
from chipflow_digital_ip.base import SoCID
from chipflow_digital_ip.memory import QSPIFlash
from amaranth_soc.wishbone.sram import WishboneSRAM
from chipflow_digital_ip.io import GPIOPeripheral
from chipflow_digital_ip.io import UARTPeripheral
from chipflow_digital_ip.io import SPISignature, SPIPeripheral
from chipflow_digital_ip.io import I2CSignature, I2CPeripheral

from amaranth_cv32e40p.cv32e40p import CV32E40P, DebugModule
from chipflow_lib.platforms import InputIOSignature, OutputIOSignature
from chipflow_digital_ip.io import GPIOPeripheral, UARTPeripheral, SPIPeripheral, I2CPeripheral
from chipflow_digital_ip.processors import CV32E40P, OBIDebugModule
from chipflow_lib.platforms import GPIOSignature, UARTSignature, SPISignature, I2CSignature, QSPIFlashSignature, JTAGSignature, attach_simulation_data
from .ips.pwm import PWMPins, PWMPeripheral
# from .ips.pdm import PDMPeripheral

__all__ = ["JTAGSignature", "MySoC"]

JTAGSignature = wiring.Signature({
"trst": Out(InputIOSignature(1)),
"tck": Out(InputIOSignature(1)),
"tms": Out(InputIOSignature(1)),
"tdi": Out(InputIOSignature(1)),
"tdo": Out(OutputIOSignature(1)),
})

__all__ = ["MySoC"]

class MySoC(wiring.Component):
def __init__(self):
# Top level interfaces

interfaces = {
"flash": Out(QSPIFlash.Signature()),
"cpu_jtag": Out(JTAGSignature)
"flash": Out(QSPIFlashSignature()),
"cpu_jtag": Out(JTAGSignature())
}

self.user_spi_count = 3
Expand All @@ -51,10 +40,10 @@ def __init__(self):
self.gpio_width = 8

for i in range(self.user_spi_count):
interfaces[f"user_spi_{i}"] = Out(SPISignature)
interfaces[f"user_spi_{i}"] = Out(SPISignature())

for i in range(self.i2c_count):
interfaces[f"i2c_{i}"] = Out(I2CSignature)
interfaces[f"i2c_{i}"] = Out(I2CSignature())

for i in range(self.motor_count):
interfaces[f"motor_pwm{i}"] = Out(PWMPins.Signature())
Expand All @@ -63,10 +52,10 @@ def __init__(self):
# interfaces[f"pdm_ao_{i}"] = Out(PDMPins.Signature())

for i in range(self.uart_count):
interfaces[f"uart_{i}"] = Out(UARTPeripheral.Signature())
interfaces[f"uart_{i}"] = Out(UARTSignature())

for i in range(self.gpio_banks):
interfaces[f"gpio_{i}"] = Out(GPIOPeripheral.Signature(pin_count=self.gpio_width))
interfaces[f"gpio_{i}"] = Out(GPIOSignature(pin_count=self.gpio_width))

super().__init__(interfaces)

Expand Down Expand Up @@ -126,7 +115,7 @@ def elaborate(self, platform):
m.submodules.cpu = cpu

# Debug
debug = DebugModule()
debug = OBIDebugModule()
wb_arbiter.add(debug.initiator)
wb_decoder.add(debug.target, name="debug", addr=self.debug_base)
m.d.comb += cpu.debug_req.eq(debug.debug_req)
Expand All @@ -148,6 +137,7 @@ def elaborate(self, platform):
csr_decoder.add(spiflash.csr_bus, name="spiflash", addr=self.csr_spiflash_base - self.csr_base)
m.submodules.spiflash = spiflash

print(f"spiflash = {spiflash}")
connect(m, flipped(self.flash), spiflash.pins)

sw.add_periph("spiflash", "SPIFLASH", self.csr_spiflash_base)
Expand Down Expand Up @@ -250,7 +240,12 @@ def elaborate(self, platform):
#sw.add_periph("gpio", "BTN_GPIO", self.csr_btn_gpio_base)

sw.generate("build/software/generated")
attach_simulation_data(self.flash, file_name="build/software/software.bin", offset=self.bios_start)

print(f"CSR resources :\n{pformat(list(csr_decoder.bus.memory_map.all_resources()), indent=2)}")
print(f"CSR memory map:\n{pformat(csr_decoder.bus.memory_map._namespace._assignments, indent=2)}")
print(f"CSR decoder subs:\n{pformat(csr_decoder._subs, indent=2)}")
print(f"Wishbone memory map:\n{pformat(wb_decoder.bus.memory_map._namespace._assignments, indent=2)}")
return m


Expand Down
85 changes: 0 additions & 85 deletions mcu_soc/design/sim/main.cc
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18 changes: 9 additions & 9 deletions mcu_soc/design/tests/events_reference.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"events": [
{ "timestamp": 0, "peripheral": "spi_0", "event": "deselect", "payload": "" },
{ "timestamp": 0, "peripheral": "spi_1", "event": "deselect", "payload": "" },
{ "timestamp": 0, "peripheral": "spi_2", "event": "deselect", "payload": "" },
{ "timestamp": 0, "peripheral": "user_spi_0", "event": "deselect", "payload": "" },
{ "timestamp": 0, "peripheral": "user_spi_1", "event": "deselect", "payload": "" },
{ "timestamp": 0, "peripheral": "user_spi_2", "event": "deselect", "payload": "" },
{ "timestamp": 58290, "peripheral": "uart_0", "event": "tx", "payload": 240 },
{ "timestamp": 75894, "peripheral": "uart_0", "event": "tx", "payload": 159 },
{ "timestamp": 93498, "peripheral": "uart_0", "event": "tx", "payload": 144 },
Expand Down Expand Up @@ -120,9 +120,9 @@
{ "timestamp": 3751546, "peripheral": "uart_0", "event": "tx", "payload": 73 },
{ "timestamp": 3759502, "peripheral": "uart_0", "event": "tx", "payload": 58 },
{ "timestamp": 3767458, "peripheral": "uart_0", "event": "tx", "payload": 32 },
{ "timestamp": 3772632, "peripheral": "spi_0", "event": "select", "payload": "" },
{ "timestamp": 3774292, "peripheral": "spi_0", "event": "data", "payload": 90 },
{ "timestamp": 3778120, "peripheral": "spi_0", "event": "deselect", "payload": "" },
{ "timestamp": 3772632, "peripheral": "user_spi_0", "event": "select", "payload": "" },
{ "timestamp": 3774292, "peripheral": "user_spi_0", "event": "data", "payload": 90 },
{ "timestamp": 3778120, "peripheral": "user_spi_0", "event": "deselect", "payload": "" },
{ "timestamp": 3792610, "peripheral": "uart_0", "event": "tx", "payload": 48 },
{ "timestamp": 3802482, "peripheral": "uart_0", "event": "tx", "payload": 48 },
{ "timestamp": 3812354, "peripheral": "uart_0", "event": "tx", "payload": 48 },
Expand All @@ -132,9 +132,9 @@
{ "timestamp": 3851842, "peripheral": "uart_0", "event": "tx", "payload": 54 },
{ "timestamp": 3861714, "peripheral": "uart_0", "event": "tx", "payload": 51 },
{ "timestamp": 3873714, "peripheral": "uart_0", "event": "tx", "payload": 32 },
{ "timestamp": 3875772, "peripheral": "spi_0", "event": "select", "payload": "" },
{ "timestamp": 3877588, "peripheral": "spi_0", "event": "data", "payload": 1193046 },
{ "timestamp": 3881260, "peripheral": "spi_0", "event": "deselect", "payload": "" },
{ "timestamp": 3875772, "peripheral": "user_spi_0", "event": "select", "payload": "" },
{ "timestamp": 3877588, "peripheral": "user_spi_0", "event": "data", "payload": 1193046 },
{ "timestamp": 3881260, "peripheral": "user_spi_0", "event": "deselect", "payload": "" },
{ "timestamp": 3895750, "peripheral": "uart_0", "event": "tx", "payload": 48 },
{ "timestamp": 3905622, "peripheral": "uart_0", "event": "tx", "payload": 48 },
{ "timestamp": 3915494, "peripheral": "uart_0", "event": "tx", "payload": 48 },
Expand Down
12 changes: 6 additions & 6 deletions mcu_soc/design/tests/input.json
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Expand Up @@ -9,14 +9,14 @@
{ "type": "wait", "peripheral": "uart_0", "event": "tx", "payload": 35},
{ "type": "action", "peripheral": "uart_1", "event": "tx", "payload": 42},

{ "type": "action", "peripheral": "spi_0", "event": "set_data", "payload": 99},
{ "type": "action", "peripheral": "user_spi_0", "event": "set_data", "payload": 99},

{ "type": "wait", "peripheral": "spi_0", "event": "select", "payload": ""},
{ "type": "wait", "peripheral": "spi_0", "event": "data", "payload": 90 },
{ "type": "wait", "peripheral": "spi_0", "event": "deselect", "payload": ""},
{ "type": "wait", "peripheral": "user_spi_0", "event": "select", "payload": ""},
{ "type": "wait", "peripheral": "user_spi_0", "event": "data", "payload": 90 },
{ "type": "wait", "peripheral": "user_spi_0", "event": "deselect", "payload": ""},

{ "type": "action", "peripheral": "spi_0", "event": "set_width", "payload": 21},
{ "type": "action", "peripheral": "spi_0", "event": "set_data", "payload": 773615},
{ "type": "action", "peripheral": "user_spi_0", "event": "set_width", "payload": 21},
{ "type": "action", "peripheral": "user_spi_0", "event": "set_data", "payload": 773615},

{ "type": "wait", "peripheral": "i2c_0", "event": "start", "payload": "" },
{ "type": "wait", "peripheral": "i2c_0", "event": "address", "payload": 160 },
Expand Down
13 changes: 6 additions & 7 deletions minimal/design/design.py
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,7 @@

from minerva.core import Minerva

from chipflow_lib.platforms import InputIOSignature, OutputIOSignature, BidirIOSignature, Sky130DriveMode
# from .ips.pdm import PDMPeripheral
from chipflow_lib.platforms import Sky130DriveMode, GPIOSignature, UARTSignature, QSPIFlashSignature, attach_simulation_data

__all__ = ["MySoC"]

Expand All @@ -26,10 +25,10 @@ def __init__(self):
# Top level interfaces

super().__init__({
"flash": Out(QSPIFlash.Signature()),
"uart_0": Out(UARTPeripheral.Signature()),
"gpio_0": Out(GPIOPeripheral.Signature(pin_count=8)),
"gpio_open_drain": Out(GPIOPeripheral.Signature(pin_count=4, sky130_drive_mode=Sky130DriveMode.OPEN_DRAIN_STRONG_UP))
"flash": Out(QSPIFlashSignature()),
"uart_0": Out(UARTSignature()),
"gpio_0": Out(GPIOSignature(pin_count=8)),
"gpio_open_drain": Out(GPIOSignature(pin_count=4, sky130_drive_mode=Sky130DriveMode.OPEN_DRAIN_STRONG_UP))
})

# Memory regions:
Expand Down Expand Up @@ -136,7 +135,7 @@ def elaborate(self, platform):
sw.add_periph("soc_id", "SOC_ID", self.csr_soc_id_base)

sw.generate("build/software/generated")

attach_simulation_data(self.flash, file_name="build/software/software.bin", offset=self.bios_start)
return m


Expand Down
67 changes: 0 additions & 67 deletions minimal/design/sim/main.cc
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