Multifunction Counter on FPGA (MultiCounter)

Description

This project implements a multifunction counter (MultiCounter) in VHDL, targeted for a Xilinx Artix-7 FPGA (specifically the XC7A35T-ICPG236C model on the Digilent Basys 3 board). The system is capable of acquiring a 10-bit binary number from switches, displaying it on a four-digit 7-segment display, and operating in several counting modes (incremental, incremental with repetitions, decremental) timed at 1 Hz.

The project was developed using Xilinx Vivado ML Edition.

Author

• Francesco Lo Verde
• Computer Engineering - Curriculum: Robotics
• University Of Perugia (Università Degli Studi Di Perugia)
• Student ID: 377960
• Email: francesco.loverde@studenti.unipg.it

Key Features

• User Input:
  • 10-bit reference number (0-999) settable via switches.
  • Counting mode selection via 3 switches (operationSwitches).
  • Buttons for general reset, counter reset, and repetition display.
  • Switch to enable/disable the display.
• Output:
  • Display of the current value or reference number on 4 7-segment displays.
  • Status LEDs to indicate clock lock and display activity.
• Counting Modes (timed at 1 Hz):
  1. Direct Display ("000"): Shows the value set by the switches.
  2. Incremental with Auto-Reset ("001"): Counts from 0 to the reference value, holds for 3 seconds, then resets.
  3. Incremental with Repetitions ("010"): Counts from 0 to the reference value, increments a repetition counter, and restarts. Repetitions can be viewed via a button.
  4. Decremental ("100"): Counts from the reference value down to 0, then stops.
• Clock Management:
  • Derivation of multiple clocks (80MHz, 50MHz, 6MHz) from a 100MHz system clock using the IP Clocking Wizard.
  • Generation of low-frequency clocks (4kHz for display refresh, 1Hz for counting) using custom dividers.
• Synchronization: Asynchronous inputs (buttons, switches) are synchronized to ensure operational stability.

Project Structure (Main VHDL Modules)

• MultiCounter (Top-level entity)
• ClockManager (Primary clock manager)
• multiClock (IP for multiple clock generation)
• Clock_50Mhz_To_Clock_1Hz (Divider for 1Hz clock)
• Clock_6Mhz_To_Clock_4KHz (Divider for 4kHz display clock)
• BinaryToDisplayConverter (Converts binary to 7-segment display signals, manages multiplexing and display clock)
• DecimalToSevenSegment (Converts decimal digit to 7-segment pattern)

Vivado Project Structure

When the project is opened in Vivado, the "Sources" panel hierarchy should look like this:

• Design Sources
  • MultiCounter (Behavioral) (MultiCounter.vhd) [Top Level]
    • ClockManager_Inst: ClockManager (Behavioral) (ClockManager.vhd)
    • Binary_Display_Inst: BinaryToDisplayConverter (Behavioral) (BinaryToDisplayConverter.vhd)
      • ClockManager_Inst: ClockManager (Behavioral) (ClockManager.vhd)
      • MultiClock_Inst: multiClock (IP Core from multiClock.xci)
      • Clock_4KHz_Inst: Clock_6Mhz_To_Clock_4KHz (Behavioral) (Clock_6Mhz_To_Clock_4KHz.vhd)
      • DecimalToSevenSegment_Hundreds: DecimalToSevenSegment (Behavioral) (DecimalToSevenSegment.vhd)
      • DecimalToSevenSegment_Tens: DecimalToSevenSegment (Behavioral) (DecimalToSevenSegment.vhd)
      • DecimalToSevenSegment_Units: DecimalToSevenSegment (Behavioral) (DecimalToSevenSegment.vhd)
    • Clock_50MHz_Inst: multiClock (IP Core from multiClock.xci)
    • Clock_1Hz_Inst: Clock_50Mhz_To_Clock_1Hz (Behavioral) (Clock_50Mhz_To_Clock_1Hz.vhd)
• Constraints
  • Master_Basys3.xdc
• Simulation Sources
  • Fast_MultiCounter_TB (Behavioral) (Fast_MultiCounter_TB.vhd)
    • UUT: MultiCounter (Behavioral) (instantiating MultiCounter.vhd)

(Note: Ensure that for IP cores like multiClock, only the .xci file is version controlled, not the generated output products. Vivado will regenerate these based on the .xci file.)

Documentation

For more details on the design, implementation, and testing, please refer to the full report: Progettazione_e_Implementazione_di_un_Contatore_Multifunzione_su_FPGA.pdf (or the actual PDF filename).