[FIX] fixing instr combine

Cr0a3 · Oct 25, 2024 · 4d9c480 · 4d9c480
1 parent 6740d36
commit 4d9c480
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Showing 4 changed files with 55 additions and 9 deletions.
diff --git a/src/Target/x64/lower/downcast.rs b/src/Target/x64/lower/downcast.rs
@@ -1,7 +1,21 @@
 use crate::CodeGen::MachineInstr;
 //use crate::Target::x64Reg;
 use crate::Target::x64::asm::instr::*;
+use crate::Target::x64::X64Reg;
 
-pub(crate) fn x64_lower_downcast(_sink: &mut Vec<X64MCInstr>, _instr: &MachineInstr) {
-    todo!()
+pub(crate) fn x64_lower_downcast(sink: &mut Vec<X64MCInstr>, instr: &MachineInstr) {
+    let out = instr.out.expect("downcast expects output").into();
+    let op = match instr.operands.get(0).expect("downcast expects operand") {
+        crate::CodeGen::MachineOperand::Imm(i) => Operand::Imm(*i as i64),
+        crate::CodeGen::MachineOperand::Reg(reg) => match reg {
+            crate::CodeGen::Reg::x64(reg) => Operand::Reg(reg.sub_ty(instr.meta)),
+            _ => panic!("x64 backend expects x64 registers")
+        }
+        crate::CodeGen::MachineOperand::Stack(off) => Operand::Mem(X64Reg::Rbp - *off as u32),
+    };
+
+    sink.extend_from_slice(&[
+        X64MCInstr::with2(Mnemonic::Mov, Operand::Reg(X64Reg::Rax.sub_ty(instr.meta)), op),
+        X64MCInstr::with2(Mnemonic::Mov, out, Operand::Reg(X64Reg::Rax.sub_ty(instr.meta))),
+    ]);
 }
diff --git a/src/Target/x64/optimizer.rs b/src/Target/x64/optimizer.rs
@@ -82,6 +82,10 @@ fn X64MergeMove(instr0: &X64MCInstr, instr1: &X64MCInstr) -> Option<Vec<X64MCIns
         return None;
     }
 
+    if !instr0.is_op2_reg() {
+        return None;
+    }
+
     if !instr1.is_mov() {
         return None;
     }
@@ -125,13 +129,20 @@ fn X64MergeAdd(instr0: &X64MCInstr, instr1: &X64MCInstr, instr2: &X64MCInstr) ->
         return None;
     }
 
+    if !instr0.is_op2_reg() {
+        return None;
+    }
+
     if !(instr1.is_add1(&Operand::Reg(X64Reg::Rax)) || 
        instr1.is_add1(&Operand::Reg(X64Reg::Eax)) || 
        instr1.is_add1(&Operand::Reg(X64Reg::Ax))  || 
        instr1.is_add1(&Operand::Reg(X64Reg::Al)))   {
         return None;
     }    
 
+    if !instr1.is_op2_reg() {
+        return None;
+    }
 
     if !instr2.is_mov() {
         return None;
@@ -144,9 +155,27 @@ fn X64MergeAdd(instr0: &X64MCInstr, instr1: &X64MCInstr, instr2: &X64MCInstr) ->
         return None;
     }
 
-    let out = instr2.op1.clone();
-    let ls = instr0.op2.clone();
-    let rs = instr1.op2.clone();
+    let mut out = instr2.op1.clone();
+    let mut ls = instr0.op2.clone();
+    let mut rs = instr1.op2.clone();
+
+    if let Some(Operand::Reg(reg)) = out {
+        if reg.is_gr8() {
+            out = Some(Operand::Reg(reg.sub16()))
+        }
+    }
+
+    if let Some(Operand::Reg(reg)) = ls {
+        if reg.is_gr8() {
+            ls = Some(Operand::Reg(reg.sub64()))
+        }
+    }
+
+    if let Some(Operand::Reg(reg)) = rs {
+        if reg.is_gr8() {
+            rs = Some(Operand::Reg(reg.sub64()))
+        }
+    }
 
     Some(vec![X64MCInstr {
         mnemonic: Mnemonic::Lea,

diff --git a/tests/IR/cmp/cmp4.yl b/tests/IR/cmp/cmp4.yl
@@ -9,12 +9,13 @@ define u8 @is_greater_or_equal(u32 %0, u32 %1) {
     ret u8 %2
 }
 
-define u8 @main() {
+define i32 @main() {
   entry:
     %0 = u32 5
     %1 = u32 5
     %2 = call u8 is_greater_or_equal u32 %0 u32 %1
-    ret u8 %2
+    %3 = cast u8 %2 to i32
+    ret i32 %3
 }
 
 # EXIT_CODE=1
diff --git a/tests/IR/cmp/cmp5.yl b/tests/IR/cmp/cmp5.yl
@@ -9,7 +9,7 @@ define u8 @is_smaller_or_equal(u32 %0, u32 %1) {
     ret u8 %2
 }
 
-define u8 @main() {
+define i32 @main() {
   entry:
     %0 = u32 5
     %1 = u32 5
@@ -22,7 +22,9 @@ define u8 @main() {
 
     %6 = add u8 %2, %5
 
-    ret u8 %6
+    %7 = cast u8 %2 to i32
+
+    ret i32 %7
 }
 
 # EXIT_CODE=2