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Merge branch 'EttusResearch:master' into master
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nzqo authored Nov 30, 2024
2 parents 3073ae4 + 87c4ff6 commit 469afcc
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8 changes: 7 additions & 1 deletion .ci/docker/uhd-builder-ubuntu1804.Dockerfile
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,6 @@ RUN apt-get update && \
sudo \
# Install UHD dependencies
abi-dumper \
cmake \
doxygen \
dpdk \
libboost-all-dev \
Expand Down Expand Up @@ -85,3 +84,10 @@ RUN python3 -m pip install \
click-plugins \
zmq \
scipy

RUN wget https://cmake.org/files/v3.12/cmake-3.12.4-Linux-x86_64.tar.gz -O /tmp/cmake.tar.gz && \
(echo "486edd6710b5250946b4b199406ccbf8f567ef0e23cfe38f7938b8c78a2ffa5f /tmp/cmake.tar.gz" | sha256sum --check --status ) && \
tar -zxvf /tmp/cmake.tar.gz -C /opt && \
cp -r /opt/cmake-3.12.4-Linux-x86_64/bin/* /usr/local/bin/ && \
cp -r /opt/cmake-3.12.4-Linux-x86_64/share/* /usr/local/share/ && \
rm /tmp/cmake.tar.gz
2 changes: 1 addition & 1 deletion .ci/templates/job-analyze-changeset.yml
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ jobs:
$AGENT_TEMPDIRECTORY/ac_venv/$VENV_BIN_DIR/python3 tools/changeset_testlist.py \
--target-branch $TARGET_BRANCH \
--set-azdo-var UhdTestList \
--list-tests $EXTRA_ARGS
--list-tests --verbose $EXTRA_ARGS
name: gen_testlist
displayName: Generate Test-List
env:
Expand Down
4 changes: 2 additions & 2 deletions .ci/templates/job-uhd-rf-tests-pebbles.yml
Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,8 @@ jobs:
devType: 'n3xx'
devModel: 'n310'
devName: pebbles-n310-0
devSerial: '3176DDF'
devHostname: 'ni-n3xx-3176DDF'
devSerial: '$(n310_devSerial)'
devHostname: 'ni-n3xx-$(n310_devSerial)'
devBus: 'ip'
devAddr: '192.168.40.17'
sfpAddrs: '192.168.10.17,192.168.40.17'
Expand Down
39 changes: 21 additions & 18 deletions .ci/templates/job-uhd-streaming-tests-beauty.yml
Original file line number Diff line number Diff line change
Expand Up @@ -46,55 +46,58 @@ jobs:
beauty-X310-0:
dutName: 'beauty-X310-0'
dutType: 'X310'
dutAddr: '192.168.10.3'
dutSecondAddr: '192.168.20.3'
dutAddr: '$(x310_dutAddr)'
dutSecondAddr: '$(x310_dutSecondAddr)'
dutFPGA: 'XG'
dutNameId: ''
dutNumRecvFrames: ''
dutNumSendFrames: ''
jtagSerial: '251635138E94'
sfpInt0: 'ens4f0'
sfpInt1: 'ens4f1'
sfpInt0: '$(x310_sfpInt0)'
sfpInt1: '$(x310_sfpInt1)'
# beauty-X410-0 X4_200:
# dutName: 'beauty-X410-0'
# dutFamily: 'x4xx'
# dutType: 'x410'
# dutAddr: '192.168.10.2'
# dutSecondAddr: '192.168.20.2'
# dutAddr: '$(x410_dutAddr)'
# dutSecondAddr: '$(x410_dutSecondAddr)'
# dutFPGA:'X4_200'
# dutNameId: ''
# dutEmbeddedImagesArtifact: 'x4xx-images'
# uartSerial: '$(x410_uartSerial)'
# dutNumRecvFrames: ''
# dutNumSendFrames: ''
# sfpInt0: 'ens6f0'
# sfpInt1: 'ens6f1'
# sfpInt0: '$(x410_sfpInt0)'
# sfpInt1: '$(x410_sfpInt1)'
beauty-X410-0 CG_400:
dutName: 'beauty-X410-0'
dutFamily: 'x4xx'
dutType: 'x410'
dutAddr: '192.168.110.2'
dutSecondAddr: '192.168.120.2'
dutAddr: '$(x410_dutAddr)'
dutSecondAddr: '$(x410_dutSecondAddr)'
dutFPGA: 'CG_400'
dutNameId: ''
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '2516351E2C9A'
uartSerial: '$(x410_uartSerial)'
dutNumRecvFrames: ''
dutNumSendFrames: ''
sfpInt0: 'ens6f0'
sfpInt1: 'ens6f1'
sfpInt0: '$(x410_sfpInt0)'
sfpInt1: '$(x410_sfpInt1)'
beauty-X410-0 UC_200:
dutName: 'beauty-X410-0'
dutFamily: 'x4xx'
dutType: 'x410'
dutAddr: '192.168.120.2'
dutSecondAddr: '192.168.120.2'
# UC image: device is reachable only via dutSecondAddr
dutAddr: '$(x410_dutSecondAddr)'
dutSecondAddr: '$(x410_dutSecondAddr)'
dutFPGA: 'UC_200'
dutNameId: ''
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '2516351E2C9A'
uartSerial: '$(x410_uartSerial)'
dutNumRecvFrames: ''
dutNumSendFrames: ''
sfpInt0: 'ens6f0'
sfpInt1: 'ens6f1'
sfpInt0: '$(x410_sfpInt0)'
sfpInt1: '$(x410_sfpInt1)'
# beauty-E320-0:
# dutName: 'beauty-E320-0'
# dutType: 'E320'
Expand Down
20 changes: 10 additions & 10 deletions .ci/templates/job-uhd-streaming-tests-x440.yml
Original file line number Diff line number Diff line change
Expand Up @@ -39,27 +39,27 @@ jobs:
dutName: 'streaming-X440-0'
dutFamily: 'x4xx'
dutType: 'x440'
dutAddr: '192.168.110.2'
dutSecondAddr: '192.168.120.2'
dutAddr: '$(x440_dutAddr)'
dutSecondAddr: '$(x440_dutSecondAddr)'
dutFPGA: 'CG_400'
dutNameId: ''
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '251635271947'
uartSerial: '$(x440_uartSerial)'
dutNumRecvFrames: ''
dutNumSendFrames: ''
sfpInt0: 'enp1s0f0np0'
sfpInt1: 'enp1s0f1np1'
sfpInt0: '$(x440_sfpInt0)'
sfpInt1: '$(x440_sfpInt1)'
X440-0 CG_1600:
dutName: 'streaming-X440-0'
dutFamily: 'x4xx'
dutType: 'x440'
dutAddr: '192.168.110.2'
dutSecondAddr: '192.168.120.2'
dutAddr: '$(x440_dutAddr)'
dutSecondAddr: '$(x440_dutSecondAddr)'
dutFPGA: 'CG_1600'
dutNameId: ''
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '251635271947'
uartSerial: '$(x440_uartSerial)'
dutNumRecvFrames: ''
dutNumSendFrames: ''
sfpInt0: 'enp1s0f0np0'
sfpInt1: 'enp1s0f1np1'
sfpInt0: '$(x440_sfpInt0)'
sfpInt1: '$(x440_sfpInt1)'
109 changes: 87 additions & 22 deletions .ci/templates/stages-uhd-pipeline.yml
Original file line number Diff line number Diff line change
Expand Up @@ -253,21 +253,16 @@ stages:
cache_sstate: ${{ parameters.cache_sstate }}
cache_downloads: False
machines:
${{ if parameters.build_e310_sg1 }}:
e310_sg1:
machineName: e310_sg1
${{ if parameters.build_e310_sg3 }}:
e310_sg3:
machineName: e310_sg3
${{ if parameters.build_e320 }}:
e320:
machineName: e320
${{ if parameters.build_n3xx }}:
n3xx:
machineName: n3xx
${{ if parameters.build_x4xx }}:
x4xx:
machineName: x4xx
- ${{ if parameters.build_e310_sg1 }}:
- e310_sg1
- ${{ if parameters.build_e310_sg3 }}:
- e310_sg3
- ${{ if parameters.build_e320 }}:
- e320
- ${{ if parameters.build_n3xx }}:
- n3xx
- ${{ if parameters.build_x4xx }}:
- x4xx
auto_conf: $AUTO_CONF
run_from_external_repo: true
prebuild_steps:
Expand Down Expand Up @@ -380,7 +375,7 @@ stages:
installer: nsis

- stage: devtest_uhd_x3xx_b2xx_stage
displayName: devtest UHD x3xx b2xx
displayName: Dev Test UHD x3xx b2xx
dependsOn:
- build_uhd_stage_linux
- analyze_changeset
Expand All @@ -404,7 +399,7 @@ stages:
testDevices: 'x3xx,b2xx'

- stage: devtest_uhd_n3xx_e320_stage
displayName: devtest UHD n3xx e320
displayName: Dev Test UHD n3xx e320
dependsOn:
- build_uhd_stage_linux
- build_uhd_embedded_system_images
Expand All @@ -428,8 +423,8 @@ stages:
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
testDevices: 'n3xx,e320'

- stage: test_uhd_x4xx_stage
displayName: Test UHD x4xx
- stage: test_uhd_x4xx_sdrtest0_stage
displayName: RF Test UHD x4xx sdr-test0
dependsOn:
- build_uhd_stage_linux
- build_uhd_embedded_system_images
Expand Down Expand Up @@ -463,6 +458,32 @@ stages:
testOS: ubuntu1804
uhdFpgaArtifactSource: uhd_fpga_pipeline
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}

- stage: test_uhd_x4xx_pebbles_stage
displayName: RF Test UHD x4xx pebbles
dependsOn:
- build_uhd_stage_linux
- build_uhd_embedded_system_images
- build_gnuradio_stage_linux
- analyze_changeset
# This will make $(UhdTestList) available to jobs/steps/tasks, but not for the
# condition.
variables:
UhdTestList: $[stageDependencies.analyze_changeset.analyze.outputs['gen_testlist.UhdTestList']]
condition: >
and(
succeeded(),
or(
${{ parameters.skip_analyze_changeset }},
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.rf.all'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.rf.x4xx'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.rf.x410'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.rf.x440'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'devtest.all'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'devtest.x410'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'devtest.x440')
))
jobs:
- template: tests/job-uhd-x410-hardware-tests-pebbles.yml
parameters:
testOS: ubuntu1804
Expand All @@ -475,6 +496,32 @@ stages:
uhdFpgaArtifactSource: uhd_fpga_pipeline
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
testLength: ${{ parameters.testLength }}

- stage: test_uhd_x4xx_saison_stage
displayName: RF Test UHD x4xx saison
dependsOn:
- build_uhd_stage_linux
- build_uhd_embedded_system_images
- build_gnuradio_stage_linux
- analyze_changeset
# This will make $(UhdTestList) available to jobs/steps/tasks, but not for the
# condition.
variables:
UhdTestList: $[stageDependencies.analyze_changeset.analyze.outputs['gen_testlist.UhdTestList']]
condition: >
and(
succeeded(),
or(
${{ parameters.skip_analyze_changeset }},
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.rf.all'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.rf.x4xx'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.rf.x410'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.rf.x440'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'devtest.all'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'devtest.x410'),
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'devtest.x440')
))
jobs:
- template: tests/job-uhd-x440-hardware-tests-saison.yml
parameters:
testOS: ubuntu2204
Expand All @@ -484,7 +531,7 @@ stages:
testLength: ${{ parameters.testLength }}

- stage: test_uhd_rf_test_stage
displayName: Run rf tests n3xx
displayName: RF Test UHD n3xx pebbles
dependsOn:
- analyze_changeset
- build_uhd_stage_linux
Expand All @@ -509,8 +556,8 @@ stages:
testOS: ubuntu1804
testDevices: 'n3xx'

- stage: test_streaming_stage
displayName: Test UHD Streaming
- stage: test_streaming_beauty_stage
displayName: Test UHD Streaming beauty
dependsOn:
- analyze_changeset
- build_uhd_stage_linux
Expand All @@ -533,6 +580,24 @@ stages:
uhdFpgaArtifactSource: uhd_fpga_pipeline
fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
testLength: ${{ parameters.testLength }}

- stage: test_streaming_x440_stage
displayName: Test UHD Streaming x440
dependsOn:
- analyze_changeset
- build_uhd_stage_linux
- build_uhd_embedded_system_images
condition: >
and(
succeeded('build_uhd_stage_linux'),
succeeded('build_uhd_embedded_system_images'),
${{ parameters.run_streaming_tests }},
or(
${{ parameters.skip_analyze_changeset }},
contains(dependencies.analyze_changeset.outputs['analyze.gen_testlist.UhdTestList'], 'hw.streaming')
)
)
jobs:
- template: job-uhd-streaming-tests-x440.yml
parameters:
testOS: ubuntu2204
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ jobs:
devtestPattern: 'x4x0'
dutFPGA: 'X4_200'
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '2516351DDCC0'
uartSerial: $(x410_uartSerial)
pipelineAgent: pebbles-agent-1
pytestAtsConfig: uhd_oss_ats
pytestDUT: 'x410'
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,6 @@ jobs:
devtestPattern: 'x410'
dutFPGA: 'X4_200'
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '2516351FE64E'
uartSerial: $(x410_uartSerial)
pytestDUT: 'x410'
pipelineAgent: sdr-test0
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ jobs:
devtestPattern: 'x4x0'
dutFPGA: 'X4_400'
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '251635284FC9'
uartSerial: $(x440_uartSerial)
pipelineAgent: pebbles-agent-1
pytestAtsConfig: uhd_oss_ats
pytestDUT: 'x440'
Expand Down
2 changes: 1 addition & 1 deletion .ci/templates/tests/job-uhd-x440-hardware-tests-saison.yml
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ jobs:
devtestPattern: 'x4x0'
dutFPGA: 'X4_400'
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '251635284FCA'
uartSerial: $(x440_uartSerial)
pipelineAgent: saison-agent-1
pytestAtsConfig: saison_multichan_ats
pytestDUT: 'x440'
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,6 @@ jobs:
master_clock_rate: '125e6'
dutFPGA: 'X4_400'
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '25163525D2B3'
uartSerial: $(x440_uartSerial)
pytestDUT: 'x440'
pipelineAgent: sdr-test0
Original file line number Diff line number Diff line change
Expand Up @@ -2,13 +2,13 @@ pebbles-n310-0-group:
console-scu:
cls: USBSerialPort
match:
ID_SERIAL: 'Silicon_Labs_CP2105_Dual_USB_to_UART_Bridge_Controller_0097D46F'
ID_SERIAL: 'Silicon_Labs_CP2105_Dual_USB_to_UART_Bridge_Controller_00B56895'
ID_USB_INTERFACE_NUM: '01'
speed: 115200
console-linux:
cls: USBSerialPort
match:
ID_SERIAL: 'Silicon_Labs_CP2105_Dual_USB_to_UART_Bridge_Controller_0097D46F'
ID_SERIAL: 'Silicon_Labs_CP2105_Dual_USB_to_UART_Bridge_Controller_00B56895'
ID_USB_INTERFACE_NUM: '00'
speed: 115200
USBSDMuxDevice:
Expand Down
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