CPU SAP-1

Simple-As-Possible cpu design in VHDL to run on a FPGA.

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
cpu-sap-1.srcs		cpu-sap-1.srcs
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
cpu-sap-1.xpr		cpu-sap-1.xpr
tb_top_behav.wcfg		tb_top_behav.wcfg

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