Instruction Set Architecture (ISA)

Typical Instruction

Size

1-4 Bytes (8-32 Bits)

Typical instruction layout

Condition | Opcode

Condition | Opcode | Destination Register

Condition | Opcode | Destination Register | 8-bit Immediate

Condition | Opcode | Destination Register | Source/Operand 1 | Immediate/Operand 2

Condition | Opcode | Destination Register Pair | 16-bit Immediate

Condition | Opcode | 16-bit Immediate

Conditions

Condition Name	Machine Code	Notes
	0000	No condition applied
c	0001	Handle carryout
nc	1001	Handle no carryout
z	0010	Check if equal
nz	1010	Check if not equal
s	0011	Check negative signed
ns	1011	Check positive signed
p	0100	Check odd
np	1100	Check even
o	0101	Handle overflow
no	1101	Skip overflow handling
	0110	Unused
	1110	Unused complement
	0111	Unused
	1111	Unused complement
	1000	Unused special

Instruction Set

The upper bit of the opcode is reserved for indicating whether the instruction is regular or min instruction. When this bit is 0, a smaller instruction is decoded. When the this bit is 1, a normal larger instruction is decoded.

Min Instructions

These instructions only require a single byte. These can also all be conditional!

Note the registers listed here are implicit. The accumulator is intended to be an often used register.

Opcode	Machine Code	Description
nop	0x0	No operation
ret	0x1	Jump back to popped address from stack
ei	0x2	Enable interrupt
di	0x3	Disable interrupt
wait	0x4	Cpu in wait mode (stop execution)
inc r5	0x5	Increment accumulator
push r5	0x6	Push accumulator to stack
pop r5	0x7	Pop accumulator from stack

Memory Instructions

Typical Memory Operations

These types of operations include fetching and storing data in memory and registers, including immediate values. All of these operations are normal operations that require 3 bytes.

Opcode	Machine Code	Destination (4-bit)	Source (4/8-bit)	Description
mov	0x00	Destination Register	Source Register	Moves values between registers.
ld	0x01	Destination Register	Source Address (Register Pair)	Fetch data from memory at a given address.
str	0x02	Destination Address (Register Pair)	Source Register	Store data to memory at a given address.
movw	0x03	Destination Register Pair	Source Register Pair	Moves values between registers in wide bit mode.
ldi	0x04	Destination Register	8-bit immediate	Load immediate into register
sti	0x05	Destination Address (Register Pair)	8-bit immediate	Load immediate into memory location This was a stupid idea.

Stack Operations

These operations affect the stack pointer and require only 2 bytes.

Opcode	Machine Code	Target (4-bit)	Description
push	0x6	Source Register	Pushes contents of a register onto the stack
pop	0x7	Destination Register	Pop contents of the stack into a register

Control Flow Instructions

These instructions affect the flow of the program and allow for branching when paired with condition codes.

Opcode	Min Bit	Machine Code	Address (4/16-bit)	Description
jp	1	0x08	16-bit Immediate	Jump to a given immediate address
jmp	1	0x09	Destination Address (Register Pair)	Jump to address pointed to by a register pair
call	1	0x0a	16-bit Immediate	Push next instruction location onto the stack, jump to given immediate address
calr	1	0x0b	Destination Address (Register Pair)	Push next instruction location onto the stack, jump to address pointed to by a register pair
ret	0	0x1	N/A	Jump back to popped address from stack

ALU Instructions

ALU operations are only register to register (with the exception of load equivalent address operations).

Two Operand Operations

All of these operations require 3 bytes.

Opcode	Machine Code	Destination	Operand 1	Operand 2	Operation Summary
add	0x10	Destination Register	Base Number	Number to add	d <= op1 + op2
sub	0x11	Destination Register	Base Number	Number to subtract from base	d <= op1 - op2
mul	0x12	Destination Register	Base Number	Multiplicand	d <= op1 * op2
div	0x13	Destination Register	Dividend	Divisor	d <= op1 / op2
xor	0x14	Destination Register			d <= op1 xor op2
or	0x15	Destination Register			d <= op1 or op2
and	0x16	Destination Register			d <= op1 and op2
lsl	0x17	Destination Register			d <= op1 << op2
asl	0x17	Destination Register			d <= op1 << op2
lsr	0x18	Destination Register			d <= op1 >> op2 (Logical)
asr	0x19	Destination Register			d <= op1 >> op2 (Arithmetic)
addw	0x1a	Destination Register Pair	Base Number (Register Pair)	Number to add (Register Pair)	d <= op1 + op (16-bit)
subw	0x1b	Destination Register Pair	Base Number (Register Pair)	Number to subtract from base	d <= op1 - op2 (16-bit)

Operation On Destination

These operations store the result in the same register the operation is performed on. These require 2 bytes.

Opcode	Machine Code	Source/Destination	Operation Summary
not	0x1c	Register	r <= ~r
inc	0x1d	Register	r <= r + 1
dec	0x1e	Register	r <= r - 1
incw	0x1f	Register Pair	r <= r + 1
decw	0x20	Register Pair	r <= r - 1

Special Operations

Compare

Two bytes long, preserves the operand.

Opcode	Machine Code	Operand	Operation Summary
cmp	0x21	Register	Set flags (see below)
cmpw	0x22	Register Pair	Set flags (see below)

Check equal values, store in 1 if equal z

Unsigned greater than, store 1 in c

Unsigned less than, store 0 in c

Signed greater than, store 1 in s

Signed less than, store 0 in s

Load Effective Address

A whopping 4 bytes large! Usable for address operations or 16-bit add and multiply operations.

Opcode	Machine Code	Destination	Index Shift Multiply	Index	Offset	Operation Summary
lea	0x23	Register Pair	0 to 15 (4-bit Immediate)	Register Pair	8-bit Immediate	d <= d + (i << m) + o