Email: hassantaqi1812@gmail.com
Phone: +962 786 069 347
Location: Amman, Jordan

I am a fifth-year Computer Engineering student with extensive experience in FPGA and ASIC development. My expertise spans Verilog, SystemVerilog, UVM, and tools like Quartus and ModelSim. I am proficient in hardware verification, simulation, and emulation, and skilled in C++, Python, and computer architecture. My passion lies in hands-on projects and contributing to innovative hardware designs in dynamic engineering teams.

• Hardware Description Languages: Verilog, SystemVerilog
• Verification & Testing: UVM, testbenches, waveform simulations
• Programming & Scripting: C++, Python, TCL
• Hardware Design: ASIC and FPGA development, pipelining, hazard detection
• Timing Analysis: Static timing analysis, linting, CDC, RDC
• Linux & Tools: Quartus, ModelSim, VCS, Verdi

Designed and implemented a super-scalar MIPS processor with features like pipelining, branch prediction, and DFX on FPGA. Achieved first place in the Jordan Semiconductor Design Competition.

Developed a pipelined processor and cycle-accurate simulator with hazard detection and forwarding. Created UVM testbenches for functional verification, including automation tools.

Designed a RISC-V architecture with microprogramming to enhance performance and flexibility using Verilog.

Developed an assembler in C++ for translating machine code into assembly language. This project strengthened my C++ programming and system-level software development skills.

• 1st Place - Jordan Semiconductor Design Competition (Ctrl Elite Team)
• Co-lead of GDSC-HU (Google Developers Student Club)
• Public Relations Manager - IEEE-HU Chapter