The models can be compiled by compiler, the runtime is generated and managed by Vitis, and the hardware is implemented on Xilinx U280 FPGA board.
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including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware verilog code that can be implemented on FPGA
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I-Doctor/gnn-acceleration-framework-with-FPGA
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including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware verilog code that can be implemented on FPGA
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