GitHub - JJ-best/Winter_Lab4_uart_transmitter

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
HLS		HLS
Verilog		Verilog
README.md		README.md

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buad-rate generator HLS waveform.

uart-transmitter HLS waveform

verilog simulation
count == 1(start-bit)
count == 0(stop-bit)

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