A collection of custom-designed CMOS logic circuits implemented as part of VLSI coursework. Includes schematics, layout designs, simulation waveforms, and LVS checks.
This repository showcases fundamental digital circuits designed and simulated using VLSI methodologies. All circuits were implemented at the transistor level, with schematic capture, layout generation, functional simulation, and LVS verification.
- Logic Gates: NOT, NOR, NAND, XOR (2-input, 3-input)
- Arithmetic Units: Half Adder, Full Adder, 8-bit Ripple Carry Adder
Each circuit includes:
- 📐 Schematic
- 📊 Simulation Waveform
- 🧱 Layout
- ✅ Layout vs. Schematic (LVS)
This collection of VLSI circuit designs demonstrates hands-on proficiency in custom CMOS digital design using schematic capture, layout, simulation, and verification techniques. From basic logic gates to an 8-bit ripple carry adder, each project reflects a growing understanding of scalable, transistor-level circuit construction.
These foundational designs lay the groundwork for more advanced projects such as sequential logic, memory cells, and digital datapaths — all of which I aim to explore in future coursework and projects.