QFlow:An Open Source Digital Synthesis Flow

GTK waveform and IVerilog are mere tools to generate waveforms of the code executed and are used for analysis of the outputs.But, while we design an Open Core there is much more than the analysis of the output.The creation of an Open Core is complete only when it can be represented as a physical circuit.

A digital synthesis flow is a set of tools and methods used to turn a circuit design written in a high-level behavioral language like verilog or VHDL into a physical circuit.To represent a code in the form of a physical circuit involves many steps ,viz., logic optimization,placement,routing,mapping,synthesis and layout viewer.All these processes can be performed using a tool called QFlow.

QFlow is an open source digital synthesis flow tool used to represent the given high definition code in the form of a physical circuit.To perform each of the processes mentioned in the synthesis flow QFlow has its own dependencies namely Graywolf,Magic,Yosys,Vesta and QRouter.

The Dependencies of QFlow:

The principal need for the synthesis tool is that it must be able to map a logic circuit to a standard cell library. Firstly, the logic synthesis is done using Yosys tool.Digital standard cell libraries are a major component of the flow onto which the logics obtained after logic synthesis are mapped.Yosys is a framework for Verilog RTL synthesis. It provides a basic set of synthesis algorithms for various application domains. Selected features and typical applications: * Process almost any synthesizable Verilog-2005 design * Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc. * Built-in formal methods for checking properties and equivalence * Mapping to ASIC standard cell libraries (in Liberty File Format) * Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs * Foundation and/or front-end for custom flows Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the Yosys C++ code base.The logic optimisation is then performed using abc tool.This tool takes the BLIF format description and creates a netlist representation using a set of standard cells described in the "genlib" format, performing logic optimization along the way.

After mapping onto a standard cell library, a design needs to be placed and routed. The placement stage determines a rough estimate of the routing required, and tries to put all the cells into a block, ordering them to minimize the total amount of wiring connecting all the pins together. A placement tool is known as Graywolf.

The final step in creating a digital standard-cell layout is the detail route, describing exactly how the physical wiring should be generated to connect together all the pins in the design. An open source detail router has been pointedly missing.An open source digital synthesis tool flow for chip design would never be created without one.This tool is called Qrouter,which is the final link in the open source synthesis chain.The Static timing analysis is done using Vesta and the final layout is viewed using Magic Viewer.