Make vivado happy

KastnerRG · Jul 22, 2024 · 17922b5 · 17922b5
1 parent f53935b
commit 17922b5
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Showing 16 changed files with 27 additions and 26 deletions.
diff --git a/deepsocflow/rtl/axi_cgra4ml.v b/deepsocflow/rtl/axi_cgra4ml.v
@@ -210,8 +210,8 @@ wire [AXI_WIDTH   -1:0] m_axis_output_tdata;
 wire [AXI_WIDTH/8 -1:0] m_axis_output_tkeep;
 wire [W_BPT-1:0] m_bytes_per_transfer;
 
-wire [AXI_ADDR_WIDTH-1:0] reg_wr_addr_ctrl = AXI_ADDR_WIDTH'((reg_wr_addr-AXIL_BASE_ADDR) >> 2);
-wire [AXI_ADDR_WIDTH-1:0] reg_rd_addr_ctrl = AXI_ADDR_WIDTH'((reg_rd_addr-AXIL_BASE_ADDR) >> 2);
+wire [AXIL_ADDR_WIDTH-1:0] reg_wr_addr_ctrl = (reg_wr_addr-AXIL_BASE_ADDR) >> 2;
+wire [AXIL_ADDR_WIDTH-1:0] reg_rd_addr_ctrl = (reg_rd_addr-AXIL_BASE_ADDR) >> 2;
 
 
 
@@ -270,11 +270,11 @@ dma_controller #(
     .rstn(rstn),
     .reg_wr_en(reg_wr_en),
     .reg_wr_ack(reg_wr_ack),
-    .reg_wr_addr(reg_wr_addr_ctrl),
+    .reg_wr_addr(reg_wr_addr_ctrl[AXI_ADDR_WIDTH-1:0]),
     .reg_wr_data(reg_wr_data),
     .reg_rd_en(reg_rd_en),
     .reg_rd_ack(reg_rd_ack),
-    .reg_rd_addr(reg_rd_addr_ctrl),
+    .reg_rd_addr(reg_rd_addr_ctrl[AXI_ADDR_WIDTH-1:0]),
     .reg_rd_data(reg_rd_data),
     .o_ready(m_axis_output_tready),
     .o_valid(m_axis_output_tvalid),

diff --git a/deepsocflow/rtl/ext/alex_axi_dma_rd.v → deepsocflow/rtl/ext/alex_axi_dma_rd.sv b/deepsocflow/rtl/ext/alex_axi_dma_rd.v → deepsocflow/rtl/ext/alex_axi_dma_rd.sv
@@ -26,7 +26,7 @@ THE SOFTWARE.
 
 `resetall
 `timescale 1ns / 1ps
-`default_nettype none
+
 `include "../defines.svh"
 
 /*

diff --git a/deepsocflow/rtl/ext/alex_axi_dma_wr.v → deepsocflow/rtl/ext/alex_axi_dma_wr.sv b/deepsocflow/rtl/ext/alex_axi_dma_wr.v → deepsocflow/rtl/ext/alex_axi_dma_wr.sv
@@ -26,7 +26,7 @@ THE SOFTWARE.
 
 `resetall
 `timescale 1ns / 1ps
-`default_nettype none
+
 `include "../defines.svh"
 
 /*

diff --git a/deepsocflow/rtl/ext/alex_axilite_ram.v → deepsocflow/rtl/ext/alex_axilite_ram.sv b/deepsocflow/rtl/ext/alex_axilite_ram.v → deepsocflow/rtl/ext/alex_axilite_ram.sv
diff --git a/deepsocflow/rtl/ext/alex_axilite_rd.v → deepsocflow/rtl/ext/alex_axilite_rd.sv b/deepsocflow/rtl/ext/alex_axilite_rd.v → deepsocflow/rtl/ext/alex_axilite_rd.sv
diff --git a/deepsocflow/rtl/ext/alex_axilite_wr.v → deepsocflow/rtl/ext/alex_axilite_wr.sv b/deepsocflow/rtl/ext/alex_axilite_wr.v → deepsocflow/rtl/ext/alex_axilite_wr.sv
diff --git a/deepsocflow/rtl/ext/alex_axis_adapter.sv b/deepsocflow/rtl/ext/alex_axis_adapter.sv
@@ -26,7 +26,7 @@ THE SOFTWARE.
 
 `resetall
 `timescale 1ns / 1ps
-`default_nettype none
+
 `include "../defines.svh"
 
 /*

diff --git a/deepsocflow/rtl/ext/xilinx_sdp.sv b/deepsocflow/rtl/ext/xilinx_sdp.sv
@@ -1,6 +1,7 @@
 // Asymmetric port RAM
 // Read Wider than Write. Read Statement in loop
 //asym_ram_sdp_read_wider.v
+`timescale 1ns / 1ps
 
 module asym_ram_sdp_read_wider (
     clkA,

diff --git a/deepsocflow/tcl/fpga/vivado.tcl b/deepsocflow/tcl/fpga/vivado.tcl
@@ -3,15 +3,15 @@ add_files  [glob $CONFIG_DIR/*.svh] [glob $RTL_DIR/*] [glob $RTL_DIR/ext/*]
 update_compile_order -fileset sources_1
 
 set_property top axi_cgra4ml [current_fileset]
-create_bd_cell -type module -reference axi_cgra4ml rtl_oc_top_0
+create_bd_cell -type module -reference axi_cgra4ml axi_cgra4ml_0
 
 # Connect full AXI ports
-connect_bd_intf_net [get_bd_intf_pins rtl_oc_top_0/m_axi_output] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD]
-connect_bd_intf_net [get_bd_intf_pins rtl_oc_top_0/m_axi_pixel] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC1_FPD]
-connect_bd_intf_net [get_bd_intf_pins rtl_oc_top_0/m_axi_weights] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+connect_bd_intf_net [get_bd_intf_pins axi_cgra4ml_0/m_axi_output] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD]
+connect_bd_intf_net [get_bd_intf_pins axi_cgra4ml_0/m_axi_pixel] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC1_FPD]
+connect_bd_intf_net [get_bd_intf_pins axi_cgra4ml_0/m_axi_weights] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
 
 # Connect AXI-lite port with automation
-apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {Auto} Clk_slave {Auto} Clk_xbar {Auto} Master {/zynq_ultra_ps_e_0/M_AXI_HPM1_FPD} Slave {/rtl_oc_top_0/s_axil} ddr_seg {Auto} intc_ip {New AXI Interconnect} master_apm {0}}  [get_bd_intf_pins rtl_oc_top_0/s_axil]
+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {Auto} Clk_slave {Auto} Clk_xbar {Auto} Master {/zynq_ultra_ps_e_0/M_AXI_HPM1_FPD} Slave {/axi_cgra4ml_0/s_axil} ddr_seg {Auto} intc_ip {New AXI Interconnect} master_apm {0}}  [get_bd_intf_pins axi_cgra4ml_0/s_axil]
 # Clk automations
 apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (250 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}}  [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk]
 apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (250 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}}  [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk]
@@ -24,8 +24,8 @@ set_property top design_1_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Set AXl-lite and full_AXI addresses
-set_property range 256M [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_rtl_oc_top_0_reg0}]
-set_property offset ${CONFIG_BASEADDR} [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_rtl_oc_top_0_reg0}]
+set_property range 256M [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_axi_cgra4ml_0_reg0}]
+set_property offset ${CONFIG_BASEADDR} [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_axi_cgra4ml_0_reg0}]
 assign_bd_address
 save_bd_design
 

diff --git a/deepsocflow/test/sv/ext/axi_addr.v b/deepsocflow/test/sv/ext/axi_addr.v
@@ -41,7 +41,7 @@
 ////////////////////////////////////////////////////////////////////////////////
 //
 //
-`default_nettype none
+
 // }}}
 module	axi_addr #(
 		// {{{

diff --git a/run/param_test.py b/run/param_test.py
@@ -215,10 +215,10 @@ def product_dict(**kwargs):
                                         max_n_bundles        = [ 64      ],
                                         ram_weights_depth    = [ 20      ],
                                         ram_edges_depth      = [ 288     ],
-                                        axi_width            = [ 32      ],
+                                        axi_width            = [ 128      ],
                                         config_baseaddr      = ["B0000000"],
                                         mem_baseaddr         = ["20000000"],
-                                        target_cpu_int_bits  = [ 32      ],
+                                        target_cpu_int_bits  = [ 32       ],
                                         valid_prob           = [ 0.01    ],
                                         ready_prob           = [ 0.1     ],
                                         data_dir             = ['vectors'],

diff --git a/run/work/config_fw.h b/run/work/config_fw.h
@@ -29,7 +29,7 @@ Bundle_t bundles [N_BUNDLES] = {
 #define B_TYPE      int16_t
 #define O_TYPE      float
 #define B_WORDS     98
-#define AXI_WIDTH   32
+#define AXI_WIDTH   128
 #define MEM_BASEADDR    0x20000000
 #define CONFIG_BASEADDR 0xB0000000
 #define DATA_DIR   "../vectors"

diff --git a/run/work/config_hw.svh b/run/work/config_hw.svh
@@ -25,7 +25,7 @@
 `define DELAY_MUL           3            // constant, for now 
 `define DELAY_W_RAM         2            // constant, for now 
 
-`define AXI_WIDTH           32        
+`define AXI_WIDTH           128       
 `define HEADER_WIDTH        64        
 `define AXI_MAX_BURST_LEN   16        
 `define CONFIG_BASEADDR     40'hB0000000  
diff --git a/run/work/config_hw.tcl b/run/work/config_hw.tcl
@@ -11,5 +11,5 @@ set DELAY_W_RAM        2
 set RAM_WEIGHTS_DEPTH  20
 set RAM_EDGES_DEPTH    288
 set KH_MAX             9
-set AXI_WIDTH          32
+set AXI_WIDTH          128
 set CONFIG_BASEADDR    0xB0000000
diff --git a/run/work/hardware.json b/run/work/hardware.json
@@ -15,7 +15,7 @@
     "max_n_bundles": 64,
     "ram_weights_depth": 20,
     "ram_edges_depth": 288,
-    "axi_width": 32,
+    "axi_width": 128,
     "header_width": 64,
     "config_baseaddr": "B0000000",
     "mem_baseaddr": "20000000",

diff --git a/run/work/sources.txt b/run/work/sources.txt
@@ -5,13 +5,8 @@ D:\dnn-engine\deepsocflow\test\sv\ext\skidbuffer.v
 D:\dnn-engine\deepsocflow\test\sv\ext\zipcpu_axi2ram.v
 D:\dnn-engine\deepsocflow\rtl\axi_cgra4ml.v
 D:\dnn-engine\deepsocflow\rtl\dnn_engine.v
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_ram.v
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_rd.v
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_wr.v
 D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_pipeline_register.v
 D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_register.v
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axi_dma_rd.v
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axi_dma_wr.v
 D:\dnn-engine\deepsocflow\rtl\ext\xilinx_spwf.v
 D:\dnn-engine\deepsocflow\rtl\axis_out_shift.sv
 D:\dnn-engine\deepsocflow\rtl\axis_pixels.sv
@@ -22,8 +17,13 @@ D:\dnn-engine\deepsocflow\rtl\dma_controller.sv
 D:\dnn-engine\deepsocflow\rtl\n_delay.sv
 D:\dnn-engine\deepsocflow\rtl\proc_engine.sv
 D:\dnn-engine\deepsocflow\rtl\ram.sv
+D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_ram.sv
+D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_rd.sv
+D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_wr.sv
 D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_adapter.sv
 D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_adapter_any.sv
+D:\dnn-engine\deepsocflow\rtl\ext\alex_axi_dma_rd.sv
+D:\dnn-engine\deepsocflow\rtl\ext\alex_axi_dma_wr.sv
 D:\dnn-engine\deepsocflow\rtl\ext\xilinx_sdp.sv
 D:\dnn-engine\run\work\config_hw.svh
 D:\dnn-engine\run\work\config_tb.svh