Skip to content

Commit

Permalink
Stable AXI-IP, working in xsim, verilator and FPGA
Browse files Browse the repository at this point in the history
  • Loading branch information
zhenghuama committed Jul 19, 2024
2 parents 44782c8 + 28eabae commit 3e75fda
Show file tree
Hide file tree
Showing 35 changed files with 5,587 additions and 33 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/verify.yml
Original file line number Diff line number Diff line change
Expand Up @@ -96,4 +96,4 @@ jobs:

# mkdir -p run/work_resnet
# cd run/work_resnet
# python ../resnet_50.py
# python ../resnet_50.py
5 changes: 5 additions & 0 deletions deepsocflow/c/example.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
#include "runtime.h"

int example_main (){
return 0;
}
2 changes: 1 addition & 1 deletion deepsocflow/c/xilinx_example.c
Original file line number Diff line number Diff line change
Expand Up @@ -16,4 +16,4 @@ int main()
hardware_cleanup();

return 0;
}
}
3 changes: 1 addition & 2 deletions deepsocflow/py/model.py
Original file line number Diff line number Diff line change
Expand Up @@ -335,7 +335,6 @@ def verify_inference(self, SIM, SIM_PATH):
'''
hw.simulate(SIM=SIM, SIM_PATH=SIM_PATH)


'''
CHECK ERROR
'''
Expand Down Expand Up @@ -400,4 +399,4 @@ def predict_performance(self):

time = clocks_total / (self.hw.FREQ * 1e6)
mem_bytes = mem_bits / 8
return time, mem_bytes
return time, mem_bytes
54 changes: 27 additions & 27 deletions deepsocflow/rtl/counter.sv
Original file line number Diff line number Diff line change
@@ -1,28 +1,28 @@
`timescale 1ns/1ps

module counter #(parameter W = 8)(
input logic clk, rstn_g, rst_l, en,
input logic [W-1:0] max_in,
output logic [W-1:0] count,
output logic last, last_clk, first
);
logic [W-1:0] max;
wire [W-1:0] count_next = last ? max : count - 1;

always_ff @(posedge clk)
if (!rstn_g)
{count, max, last} <= '0;
else if (rst_l) begin
count <= max_in;
max <= max_in;
last <= max_in==0;
end
else if (en) begin
last <= count_next == 0;
count <= count_next;
end

assign last_clk = en && last && rstn_g && !rst_l;
assign first = count == max;

`timescale 1ns/1ps

module counter #(parameter W = 8)(
input logic clk, rstn_g, rst_l, en,
input logic [W-1:0] max_in,
output logic [W-1:0] count,
output logic last, last_clk, first
);
logic [W-1:0] max;
wire [W-1:0] count_next = last ? max : count - 1;

always_ff @(posedge clk)
if (!rstn_g)
{count, max, last} <= '0;
else if (rst_l) begin
count <= max_in;
max <= max_in;
last <= max_in==0;
end
else if (en) begin
last <= count_next == 0;
count <= count_next;
end

assign last_clk = en && last && rstn_g && !rst_l;
assign first = count == max;

endmodule
2 changes: 1 addition & 1 deletion deepsocflow/tcl/asic/outputGen.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -11,4 +11,4 @@ write_sdf -view WC_VIEW ../asic/outputs/${design}_WC.sdf
setAnalysisMode -hold
set_analysis_view -setup BC_VIEW -hold BC_VIEW
do_extract_model -view BC_VIEW -format dotlib ${design}_BC.lib
write_sdf -view BC_VIEW ../asic/outputs/${design}_BC.sdf
write_sdf -view BC_VIEW ../asic/outputs/${design}_BC.sdf
1 change: 1 addition & 0 deletions deepsocflow/test/py/.gitattributes
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
**/*.ipynb linguist-vendored
123 changes: 123 additions & 0 deletions deepsocflow/test/py/performance.ipynb
Original file line number Diff line number Diff line change
@@ -0,0 +1,123 @@
{
"cells": [
{
"cell_type": "code",
"execution_count": 1,
"metadata": {},
"outputs": [
{
"name": "stderr",
"output_type": "stream",
"text": [
"c:\\ProgramData\\Miniconda3\\envs\\qkeras\\lib\\site-packages\\numpy\\_distributor_init.py:30: UserWarning: loaded more than 1 DLL from .libs:\n",
"c:\\ProgramData\\Miniconda3\\envs\\qkeras\\lib\\site-packages\\numpy\\.libs\\libopenblas.FB5AE2TYXYH2IJRDKGDGQ3XBKLKTF43H.gfortran-win_amd64.dll\n",
"c:\\ProgramData\\Miniconda3\\envs\\qkeras\\lib\\site-packages\\numpy\\.libs\\libopenblas64__v0.3.21-gcc_10_3_0.dll\n",
" warnings.warn(\"loaded more than 1 DLL from .libs:\"\n"
]
}
],
"source": [
"from tensorflow.keras.applications import resnet50\n",
"import keras\n",
"import numpy as np\n",
"\n",
"model = resnet50.ResNet50(include_top=True, weights='imagenet', input_shape=(224, 224, 3))"
]
},
{
"cell_type": "code",
"execution_count": 2,
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
"clocks=51317730.0, mb=96.698956, time_per_image=0.026, fps=38.97, mb_per_image=96.70, latency=0.205\n"
]
}
],
"source": [
"ROWS = 8\n",
"COLS = 96\n",
"KH_MAX = 7\n",
"XB = 1\n",
"YB = 3\n",
"KB = 1\n",
"XN = ROWS\n",
"MHZ = 250\n",
"\n",
"total_clocks = 0\n",
"total_mem = 0\n",
"\n",
"for i, layer in enumerate(model.layers):\n",
" if isinstance(layer, keras.layers.convolutional.conv2d.Conv2D):\n",
"\n",
" YH, YW, CO = layer.output.shape[1:]\n",
" KH, KW, CI, _ = layer.kernel.shape\n",
" SH, SW = layer.strides\n",
" XH = YH*SH\n",
" XW = YW*SW\n",
"\n",
" elif isinstance(layer, keras.layers.core.dense.Dense):\n",
" XH = XN\n",
" CI, CO = layer.kernel.shape\n",
" XW = KH = KW = 1\n",
" \n",
" else:\n",
" continue\n",
" \n",
" L = np.ceil(XH/ROWS)\n",
" IT = np.ceil(CO/np.floor(COLS/KW))\n",
"\n",
" clocks = IT * (1+ XN*L*XW*(1+CI*KH))\n",
" mem_access = \\\n",
" XB * (IT * XN * L * XW * CI * (ROWS + KH_MAX-1)) +\\\n",
" KB * (IT * CI * KH * COLS) +\\\n",
" YB * (IT * XN * L * XW * np.floor(COLS/KW) * ROWS)\n",
" \n",
" if layer.name in ['conv2_block1_0_conv', 'conv3_block1_0_conv', 'conv4_block1_0_conv', 'conv5_block1_0_conv']:\n",
" continue\n",
" total_mem += YB * (IT * XN * L * XW * np.floor(COLS/KW) * ROWS)\n",
"\n",
" total_clocks += clocks\n",
" total_mem += mem_access\n",
"\n",
"\n",
"time = total_clocks/MHZ/1e6/XN\n",
"mem_access = total_mem/1024/XN/1024\n",
"\n",
"print(f'clocks={total_clocks}, mb={mem_access:0f}, time_per_image={time:.3f}, fps={1/time:.2f}, mb_per_image={mem_access:.2f}, latency={XN*time:.3f}')"
]
},
{
"cell_type": "code",
"execution_count": null,
"metadata": {},
"outputs": [],
"source": []
}
],
"metadata": {
"kernelspec": {
"display_name": "qkeras",
"language": "python",
"name": "python3"
},
"language_info": {
"codemirror_mode": {
"name": "ipython",
"version": 3
},
"file_extension": ".py",
"mimetype": "text/x-python",
"name": "python",
"nbconvert_exporter": "python",
"pygments_lexer": "ipython3",
"version": "3.10.9"
},
"orig_nbformat": 4
},
"nbformat": 4,
"nbformat_minor": 2
}
Loading

0 comments on commit 3e75fda

Please sign in to comment.