Reorganize tcl files

KastnerRG · Nov 19, 2023 · f8f4f90 · f8f4f90
1 parent 0511986
commit f8f4f90
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Showing 18 changed files with 7 additions and 16 deletions.
diff --git a/deepsocflow/asic/constraints/dnn_engine.sdc b/deepsocflow/asic/constraints/dnn_engine.sdc
diff --git a/deepsocflow/asic/constraints/proc_engine_out.sdc b/deepsocflow/asic/constraints/proc_engine_out.sdc
diff --git a/deepsocflow/py/hardware.py b/deepsocflow/py/hardware.py
@@ -220,7 +220,7 @@ def export_vivado_tcl(self, board='zcu104', rtl_dir_abspath=None, scripts_dir_ab
         if rtl_dir_abspath is None:
             rtl_dir_abspath = self.MODULE_DIR + '/rtl'
         if scripts_dir_abspath is None:
-            scripts_dir_abspath = self.MODULE_DIR + '/fpga/scripts'
+            scripts_dir_abspath = self.MODULE_DIR + '/tcl/fpga'
         if board_tcl_abspath is None:
             board_tcl_abspath = f'{scripts_dir_abspath}/{board}.tcl'
 

diff --git a/deepsocflow/asic/scripts/clock.tcl → deepsocflow/tcl/asic/clock.tcl b/deepsocflow/asic/scripts/clock.tcl → deepsocflow/tcl/asic/clock.tcl
diff --git a/...socflow/asic/scripts/initialFloorplan.tcl → deepsocflow/tcl/asic/initialFloorplan.tcl b/...socflow/asic/scripts/initialFloorplan.tcl → deepsocflow/tcl/asic/initialFloorplan.tcl
diff --git a/deepsocflow/asic/scripts/loadDesignTech.tcl → deepsocflow/tcl/asic/loadDesignTech.tcl b/deepsocflow/asic/scripts/loadDesignTech.tcl → deepsocflow/tcl/asic/loadDesignTech.tcl
diff --git a/deepsocflow/asic/scripts/outputGen.tcl → deepsocflow/tcl/asic/outputGen.tcl b/deepsocflow/asic/scripts/outputGen.tcl → deepsocflow/tcl/asic/outputGen.tcl
diff --git a/deepsocflow/asic/scripts/pinPlacement.tcl → deepsocflow/tcl/asic/pinPlacement.tcl b/deepsocflow/asic/scripts/pinPlacement.tcl → deepsocflow/tcl/asic/pinPlacement.tcl
diff --git a/deepsocflow/asic/scripts/placement.tcl → deepsocflow/tcl/asic/placement.tcl b/deepsocflow/asic/scripts/placement.tcl → deepsocflow/tcl/asic/placement.tcl
diff --git a/deepsocflow/asic/scripts/pnr.tcl → deepsocflow/tcl/asic/pnr.tcl b/deepsocflow/asic/scripts/pnr.tcl → deepsocflow/tcl/asic/pnr.tcl
diff --git a/deepsocflow/asic/scripts/reportDesign.tcl → deepsocflow/tcl/asic/reportDesign.tcl b/deepsocflow/asic/scripts/reportDesign.tcl → deepsocflow/tcl/asic/reportDesign.tcl
diff --git a/deepsocflow/asic/scripts/route.tcl → deepsocflow/tcl/asic/route.tcl b/deepsocflow/asic/scripts/route.tcl → deepsocflow/tcl/asic/route.tcl
diff --git a/deepsocflow/asic/scripts/run_dc.tcl → deepsocflow/tcl/asic/run_dc.tcl b/deepsocflow/asic/scripts/run_dc.tcl → deepsocflow/tcl/asic/run_dc.tcl
diff --git a/deepsocflow/asic/scripts/run_genus.tcl → deepsocflow/tcl/asic/run_genus.tcl b/deepsocflow/asic/scripts/run_genus.tcl → deepsocflow/tcl/asic/run_genus.tcl
@@ -1,6 +1,6 @@
 set TOP proc_engine_out
-set FREQ_MHZ 1000
-set clock_cycle [expr 1000/$FREQ_MHZ]
+set FREQ 1000
+set clock_cycle [expr 1000/$FREQ]
 set io_delay [expr $clock_cycle/5]
 
 #--------- CONFIG
@@ -28,7 +28,10 @@ check_design > ${REPORT_DIR}/check_design.rpt
 uniquify $TOP
 
 #--------- CONSTRAINTS
-read_sdc ../constraints/$TOP.sdc
+create_clock -name aclk -period $clock_cycle [get_ports aclk]
+set_false_path -from [get_ports "aresetn"]
+set_input_delay -clock [get_clocks aclk] -add_delay -max $io_delay [all_inputs]
+set_output_delay -clock [get_clocks aclk] -add_delay -max $io_delay [all_outputs]
 
 #--------- RETIME OPTIONS
 set_db retime_async_reset true

diff --git a/deepsocflow/asic/scripts/view.tcl → deepsocflow/tcl/asic/view.tcl b/deepsocflow/asic/scripts/view.tcl → deepsocflow/tcl/asic/view.tcl
diff --git a/deepsocflow/fpga/scripts/pynq_z2.tcl → deepsocflow/tcl/fpga/pynq_z2.tcl b/deepsocflow/fpga/scripts/pynq_z2.tcl → deepsocflow/tcl/fpga/pynq_z2.tcl
diff --git a/deepsocflow/fpga/scripts/vivado.tcl → deepsocflow/tcl/fpga/vivado.tcl b/deepsocflow/fpga/scripts/vivado.tcl → deepsocflow/tcl/fpga/vivado.tcl
diff --git a/deepsocflow/fpga/scripts/zcu104.tcl → deepsocflow/tcl/fpga/zcu104.tcl b/deepsocflow/fpga/scripts/zcu104.tcl → deepsocflow/tcl/fpga/zcu104.tcl