CMOS-NAND-gate-2-input-NAND-gate

This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.

Key Features:

• Schematic Design: CMOS-based realization of a 2-input NAND gate using PMOS and NMOS transistors.
• Simulation Analysis:
• Transient Analysis: Verification of the NAND gate's logic functionality across different input combinations.
• DC Analysis: Input-output voltage characteristics and threshold voltage calculations.
• Performance Metrics: Propagation delay (rise and fall times). Power dissipation and energy efficiency. Noise margin evaluation.
• Waveform Outputs: Graphical results validating logical operation and performance parameters.
• Tools Used: Cadence Virtuoso for design, simulation, and parameter extraction. Calculator tool for delay, power, and voltage level analysis.
• Applications: Fundamental building block for larger digital circuits like multiplexers, adders, and flip-flops. Used in combinational and sequential logic design.