Scan insertion and design of a LBIST wrapper for a RISC-V core for stuck-at fault model

CUDA C simple application for Nvidia's GPU

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

Some stuff I did during the Data Science and Engineering Master of Science at Politecnico di Torino.

Check syntax in Vim/Neovim asynchronously and fix files, with Language Server Protocol (LSP) support

A tree explorer plugin for vim.

An automatic test pattern generation (ATPG) and fault simulation system.

A High-performance Timing Analysis Tool for VLSI Systems

Optimized Parallel Tiled Approach to perform 2D Convolution by taking advantage of the lower latency, higher bandwidth shared memory as well as global constant memory cached aggresively within GPU …

STM32 core support for Arduino

2D Image Convolution in CUDA by using Shared & Constant Memory.

minimum gcc blinky with makefile for STM32F411RE (on NUCLEO-F411RE demo board)

🌊 Digital timing diagram rendering engine

DE1-SOC

HW assignment of Testing and Fault Tolerance course

Electronic flight control system for the moth class sailboat developed by Polito Sailing Team

An open-source microcontroller system based on RISC-V

GNU toolchain for RISC-V, including GCC

Utilize OpenMP and CUDA to speed up LeNet-5 digit recognition CNN. In OpneMP, training with 11x speed up and 11x in testing. With the help of CUDA, the training is speed up by 3x and 57x speed up i…

Bare metal STM32F4 examples for various modules

🚜 Collect of CAN IDs and its payloads for various car brands/models in one place. Might be useful for Cyber Security Researchers, Reverse Engineers, and Automotive Electronics Enthusiasts.