Merge pull request #33 from MaximSpeczyk/refined-draft

HardwareEngineering/PCB/VendingMachine.kicad_prl

@@ -0,0 +1,77 @@
+{
+  "board": {
+    "active_layer": 0,
+    "active_layer_preset": "",
+    "auto_track_width": true,
+    "hidden_netclasses": [],
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "images": 0.6,
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": false,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      8,
+      9,
+      10,
+      11,
+      12,
+      13,
+      15,
+      16,
+      17,
+      18,
+      19,
+      20,
+      21,
+      22,
+      23,
+      24,
+      25,
+      26,
+      27,
+      28,
+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36,
+      39,
+      40
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 0
+  },
+  "meta": {
+    "filename": "VendingMachine.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}

HardwareEngineering/VHDL Project/Debugged/VM.vhd

@@ -0,0 +1,123 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity VM is
+
+port (
+
+ clk, reset: in std_logic;
+ coin_in, pickItem: in std_logic_vector(3 downto 0);
+selectedItem, dispense: out std_logic_vector(3 downto 0);
+refundOutLed: out std_logic
+
+
+);
+
+end entity;
+
+architecture VMarch of VM is
+
+signal total, refund, price, product : integer := 0;
+type state is( idle, selected, review, output);
+signal current_state, next_state : state;
+signal greaterEqual : std_logic := '0';
+
+begin
+
+memory: process (clk, reset)
+begin
+
+	if (reset ='1') then
+		current_state <= idle;
+	elsif (rising_edge(clk)) then
+		current_state <= next_state;
+	end if;
+
+end process;
+
+logic: process (coin_in, pickItem, current_state)
+begin
+
+
+	case (current_state) is
+
+  		 when idle => if ( pickItem = "0001" ) then
+			                 next_state <=  selected; 
+					 product <= 1;
+					 price <=4;
+
+			      elsif ( pickItem = "0010" ) then
+			                 next_state <=  selected; 
+					 product <= 2;
+					 price <=3;
+			      elsif ( pickItem = "0011" ) then
+			                 next_state <=  selected; 
+					 product <= 3;
+					 price <=2;
+			      else
+					next_state <=  idle; 
+					 product <= 0;
+					 price <=0;
+			     end if;
+
+		 when selected => if ( coin_in = "0101" ) then
+					total <= 5;
+					 next_state <=  review; 
+
+
+				  elsif ( coin_in = "0100" ) then
+					 total <= 4;
+					 next_state <=  review; 
+
+				  elsif ( coin_in = "0011" ) then
+					 total <= 3;
+					 next_state <=  review; 
+
+				  elsif ( coin_in = "0010") then
+					 total <= 2;
+					 next_state <=  review; 
+			          else
+					total <= 0;
+					next_state <=  selected;
+				  end if;
+
+
+		 when review => if  (total >= price) then
+					 refund <= total - price;
+					 refundOutLed <= '1';
+					 next_state <=  output;
+				else	
+					refund <= 0;
+					refundOutLed <= '0';
+					next_state <=  selected; 
+
+				  end if;
+
+	  	when output => 
+				     if (product = 1) then
+					   dispense <= "0001";
+				     	   next_state <=  idle;
+				     elsif  (product = 2) then
+					   dispense <= "0010";
+				     	   next_state <=  idle;
+				     elsif  (product = 3) then
+					   dispense <= "0011";
+				     	   next_state <=  idle;
+				     else
+					   next_state <=  selected;
+				     end if;
+
+
+
+		end case;
+
+
+
+
+
+
+end process;
+
+end architecture;

HardwareEngineering/VHDL Project/Debugged/VM.vhd.bak

@@ -0,0 +1,123 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+entity VM is
+
+port (
+
+ clk, reset: in std_logic;
+ coin_in, pickItem: in std_logic_vector(3 downto 0);
+selectedItem, dispense: out std_logic_vector(3 downto 0);
+refundOutLed: out std_logic;
+
+
+);
+
+end entity;
+
+architecture VMarch of VM is
+
+signal total, refund, price, product : integer := 0;
+type state is( idle, selected, review, output);
+signal current_state, next_state : state;
+signal greaterEqual : std_logic := '0';
+
+begin
+
+memory: process (clk, reset)
+begin
+
+	if (reset ='1') then
+		current_state <= idle;
+	elsif (rising_edge(clk)) then
+		current_state <= next_state;
+	end if;
+
+end process;
+
+logic: process (coin_in, pickItem, current_state)
+begin
+
+
+	case (current_state) is
+
+  		 when idle => if ( pickItem = "0001" ) then
+			                 next_state <=  selected; 
+					 product <= 1;
+					 price <=4;
+
+			      elsif ( pickItem = "0010" ) then
+			                 next_state <=  selected; 
+					 product <= 2;
+					 price <=3;
+			      elsif ( pickItem = "0011" ) then
+			                 next_state <=  selected; 
+					 product <= 3;
+					 price <=2;
+			      else
+					next_state <=  idle; 
+					 product <= 0;
+					 price <=0;
+			     end if;
+
+		 when selected => if ( coin_in = "0101" ) then
+					total <= 5;
+					 next_state <=  review; 
+
+
+				  elsif ( coin_in = "0100" ) then
+					 total <= 4;
+					 next_state <=  review; 
+
+				  elsif ( coin_in = "0011" ) then
+					 total <= 3;
+					 next_state <=  review; 
+
+				  elsif ( coin_in = "0010") then
+					 total <= 2;
+					 next_state <=  review; 
+			          else
+					total <= 0;
+					next_state <=  selected;
+				  end if;
+
+
+		 when review => if  (total >= price) then
+					 refund <= total - price;
+					 refundOutLed <= '1';
+					 next_state <=  output;
+				else	
+					refund <= 0;
+					refundOutLed <= '0';
+					next_state <=  selected; 
+
+				  end if;
+
+	  	when output => 
+				     if (product = 1) then
+					   dispense <= "0001";
+				     	   next_state <=  idle;
+				     elsif  (product = 2) then
+					   dispense <= "0010";
+				     	   next_state <=  idle;
+				     elsif  (product = 3) then
+					   dispense <= "0011";
+				     	   next_state <=  idle;
+				     else
+					   next_state <=  selected;
+				     end if;
+
+
+
+		end case;
+
+
+
+
+
+
+end process;
+
+end architecture;

HardwareEngineering/VHDL Project/Debugged/VM/VM.cache/wt/project.wpc

@@ -0,0 +1,4 @@
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+6d6f64655f636f756e7465727c4755494d6f6465:5
+eof:

HardwareEngineering/VHDL Project/Debugged/VM/VM.cache/wt/synthesis.wdf

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HardwareEngineering/VHDL Project/Debugged/VM/VM.cache/wt/synthesis_details.wdf

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