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Muhammed-Hamzaa/README.md

👋 Hello, I'm Muhammed Hamza!

🔭 I’m currently working on RISC-V 5 stage pipelined processor

🌱 I’m currently learning | Advance concepts in RISC-V ISA | FPGA | AI & ML with Python |

👯 I’m looking to collaborate on RISC-V

👨‍💻 All of my projects are available at https://github.com/Muhammed-Hamzaa

💬 Ask me about C++,Verilog,Python,RISC-V

📫 How to reach me hamzaghia14@gmail.com

🌐 Languages and Tools

HTML5 CSS3 JavaScript Python C C++ MySQL Oracle SQL Verilog Logisim Git GitHub Scratch Ubuntu FPGA Makefile

🤝 Let's Connect

muhammad-hamza

🤝 Let's Collaborate

I'm open to collaboration on interesting projects. If you have an idea or want to contribute to any of my projects, feel free to reach out.

Top Langs

Muhammed Hamza's GitHub Stats

GitHub Streak

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  1. Python_practice Python_practice Public

    Starting with basics of python

    Python

  2. rv32i rv32i Public

    singlecycle

    Verilog

  3. rv32i_pipelined rv32i_pipelined Public

    5 stage pipelined processor

    Verilog 1