Updated HW and SW to comply with ICD 1.4

FPGA_Developments/RMAP_Memory_FFEE_AEB_Area/Development/RMAP_Memory_FFEE_AEB_Area/farm_rmap_memory_ffee_aeb_area_top.vhd

@@ -18,7 +18,9 @@ use work.farm_rmap_mem_area_ffee_aeb_pkg.all;
 entity farm_rmap_memory_ffee_aeb_area_top is
     port(
         reset_i                     : in  std_logic                     := '0'; --          --                      reset_sink.reset
+        clk_50_i                    : in  std_logic                     := '0'; --          --                clock_sink_50mhz.clk
         clk_100_i                   : in  std_logic                     := '0'; --          --               clock_sink_100mhz.clk
+        sync_pulse_i                : in  std_logic                     := '0'; --          --          conduit_end_sync_pulse.sync_pulse_signal
         avs_rmap_0_address_i        : in  std_logic_vector(11 downto 0) := (others => '0'); --             avalon_rmap_slave_0.address
         avs_rmap_0_write_i          : in  std_logic                     := '0'; --          --                                .write
         avs_rmap_0_read_i           : in  std_logic                     := '0'; --          --                                .read
@@ -131,6 +133,10 @@ architecture rtl of farm_rmap_memory_ffee_aeb_area_top is
     signal s_memarea_wrdone            : std_logic;
     signal s_memarea_rdvalid           : std_logic;
     signal s_memarea_rddata            : std_logic_vector(31 downto 0);
+    -- sync period register signals
+    signal s_sync_period_cnt           : unsigned(63 downto 0);
+    signal s_clk50_delayed             : std_logic;
+    signal s_sync_pulse_delayed        : std_logic;
 
 begin
 
@@ -279,6 +285,52 @@ begin
             memarea_rddata_o       => s_memarea_rddata
         );
 
+    -- Processes
+
+    p_sync_period_register : process(a_avs_clock, a_reset) is
+    begin
+        if (a_reset = '1') then
+            s_rmap_mem_rd_area.aeb_hk_sync_period_1_2.sync_period <= (others => '0');
+            s_sync_period_cnt                                     <= (others => '0');
+            s_clk50_delayed                                       <= '0';
+            s_sync_pulse_delayed                                  <= '0';
+        elsif (rising_edge(a_avs_clock)) then
+
+            -- sync period register gets the amount of 50 MHz clock pulses between two sync pulses
+            -- updated every falling edge of sync pulse
+
+            -- check if a falling edge occured in the sync pulse
+            if ((sync_pulse_i = '0') and (s_sync_pulse_delayed = '1')) then
+                -- a falling edge occured in the sync pulse
+                -- update the sync period register
+                s_rmap_mem_rd_area.aeb_hk_sync_period_1_2.sync_period <= std_logic_vector(s_sync_period_cnt);
+                -- clear the sync period cnt
+                s_sync_period_cnt                                     <= (others => '0');
+            else
+                -- a falling edge did not occur in the sync pulse
+                -- check if a rising edge occured in the 50 MHz clock
+                if ((clk_50_i = '1') and (s_clk50_delayed = '0')) then
+                    -- a rising edge occured in the 50 MHz clock
+                    -- check if the sync period cnt will overflow
+                    if (s_sync_period_cnt = x"FFFFFFFFFFFFFFFF") then
+                        -- the sync period cnt will overflow
+                        -- clear the sync period cnt
+                        s_sync_period_cnt <= (others => '0');
+                    else
+                        -- the sync period cnt will not overflow
+                        -- increment the sync period cnt
+                        s_sync_period_cnt <= s_sync_period_cnt + 1;
+                    end if;
+                end if;
+            end if;
+
+            -- update delayed signals
+            s_clk50_delayed      <= clk_50_i;
+            s_sync_pulse_delayed <= sync_pulse_i;
+
+        end if;
+    end process p_sync_period_register;
+
     -- Signals Assignments --
 
     -- aeb housekeeping "adc1_rd_config_1" signals assignments

FPGA_Developments/RMAP_Memory_FFEE_AEB_Area/Development/RMAP_Memory_FFEE_AEB_Area_hw.tcl

@@ -4,7 +4,7 @@
 
 
 # 
-# RMAP_Memory_FFEE_AEB_Area "RMAP_Memory_FFEE_AEB_Area" v1.2
+# RMAP_Memory_FFEE_AEB_Area "RMAP_Memory_FFEE_AEB_Area" v1.4
 # rfranca 2020.04.04.23:17:08
 # 
 # 
@@ -20,7 +20,7 @@ package require -exact qsys 16.1
 # 
 set_module_property DESCRIPTION ""
 set_module_property NAME RMAP_Memory_FFEE_AEB_Area
-set_module_property VERSION 1.2
+set_module_property VERSION 1.4
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property AUTHOR rfranca
@@ -87,6 +87,20 @@ set_interface_property reset_sink SVD_ADDRESS_GROUP ""
 add_interface_port reset_sink reset_i reset Input 1
 
 
+# 
+# connection point clock_sink_50mhz
+# 
+add_interface clock_sink_50mhz clock end
+set_interface_property clock_sink_50mhz clockRate 50000000
+set_interface_property clock_sink_50mhz ENABLED true
+set_interface_property clock_sink_50mhz EXPORT_OF ""
+set_interface_property clock_sink_50mhz PORT_NAME_MAP ""
+set_interface_property clock_sink_50mhz CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink_50mhz SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink_50mhz clk_50_i clk Input 1
+
+
 # 
 # connection point clock_sink_100mhz
 # 
@@ -101,6 +115,21 @@ set_interface_property clock_sink_100mhz SVD_ADDRESS_GROUP ""
 add_interface_port clock_sink_100mhz clk_100_i clk Input 1
 
 
+# 
+# connection point conduit_end_sync_pulse
+# 
+add_interface conduit_end_sync_pulse conduit end
+set_interface_property conduit_end_sync_pulse associatedClock clock_sink_100mhz
+set_interface_property conduit_end_sync_pulse associatedReset reset_sink
+set_interface_property conduit_end_sync_pulse ENABLED true
+set_interface_property conduit_end_sync_pulse EXPORT_OF ""
+set_interface_property conduit_end_sync_pulse PORT_NAME_MAP ""
+set_interface_property conduit_end_sync_pulse CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end_sync_pulse SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end_sync_pulse sync_pulse_i sync_pulse_signal Input 1
+
+
 # 
 # connection point avalon_rmap_slave_0
 # 

FPGA_Developments/RMAP_Memory_FFEE_AEB_Area/Development/Testbench/RMAP_Memory_FFEE_AEB_Area_tb.cr.mti

@@ -114,13 +114,23 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 -- Compiling entity farm_tb_avs_write_ent
 -- Compiling architecture rtl of farm_tb_avs_write_ent
 
-} {} {}} ../Testbench/farm_tb_avs_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development_DLR2/FPGA_Developments/RMAP_Memory_FFEE_AEB_Area/Development/Testbench/farm_tb_avs_pkg.vhd
+} {} {}} ./testbench_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development_DLR2/FPGA_Developments/RMAP_Memory_FFEE_AEB_Area/Development/Testbench/testbench_top.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
 -- Loading package std_logic_1164
 -- Loading package NUMERIC_STD
--- Compiling package farm_tb_avs_pkg
+-- Loading package farm_avalon_mm_rmap_ffee_aeb_pkg
+-- Loading package farm_tb_avs_pkg
+-- Compiling entity testbench_top
+-- Compiling architecture RTL of testbench_top
+-- Loading package nrme_avalon_mm_rmap_nfee_pkg
+-- Loading entity rmap_avalon_stimuli
+-- Loading entity fee_0_rmap_stimuli
+-- Loading package farm_rmap_mem_area_ffee_aeb_pkg
+-- Loading entity farm_rmap_memory_ffee_aeb_area_top
+-- Loading entity farm_tb_avs_read_ent
+-- Loading entity farm_tb_avs_write_ent
 
 } {} {}} ../Testbench/farm_tb_avs_read_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development_DLR2/FPGA_Developments/RMAP_Memory_FFEE_AEB_Area/Development/Testbench/farm_tb_avs_read_ent.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
@@ -132,22 +142,12 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct
 -- Compiling entity farm_tb_avs_read_ent
 -- Compiling architecture rtl of farm_tb_avs_read_ent
 
-} {} {}} ./testbench_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development_DLR2/FPGA_Developments/RMAP_Memory_FFEE_AEB_Area/Development/Testbench/testbench_top.vhd
+} {} {}} ../Testbench/farm_tb_avs_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development_DLR2/FPGA_Developments/RMAP_Memory_FFEE_AEB_Area/Development/Testbench/farm_tb_avs_pkg.vhd
 Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
 -- Loading package STANDARD
 -- Loading package TEXTIO
 -- Loading package std_logic_1164
 -- Loading package NUMERIC_STD
--- Loading package farm_avalon_mm_rmap_ffee_aeb_pkg
--- Loading package farm_tb_avs_pkg
--- Compiling entity testbench_top
--- Compiling architecture RTL of testbench_top
--- Loading package nrme_avalon_mm_rmap_nfee_pkg
--- Loading entity rmap_avalon_stimuli
--- Loading entity fee_0_rmap_stimuli
--- Loading package farm_rmap_mem_area_ffee_aeb_pkg
--- Loading entity farm_rmap_memory_ffee_aeb_area_top
--- Loading entity farm_tb_avs_read_ent
--- Loading entity farm_tb_avs_write_ent
+-- Compiling package farm_tb_avs_pkg
 
 } {} {}}