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Solved problem with simultaneous memory access on DDR 1
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rodmarfran committed Nov 11, 2021
1 parent 2b9b6cc commit e0a6ac9
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Showing 41 changed files with 47,028 additions and 93,349 deletions.
44 changes: 22 additions & 22 deletions G3U_HW_V02_2GB/Qsys_Project/.qsys_edit/MebX_Qsys_Project.xml
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349 changes: 171 additions & 178 deletions G3U_HW_V02_2GB/Qsys_Project/.qsys_edit/MebX_Qsys_Project_schematic.nlv

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3 changes: 2 additions & 1 deletion G3U_HW_V02_2GB/Qsys_Project/.qsys_edit/preferences.xml
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Expand Up @@ -7,9 +7,10 @@
<irq preferredWidth="34" />
<name preferredWidth="354" />
<inputclock preferredWidth="289" />
<export preferredWidth="236" />
</columns>
</systemtable>
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<hdlexample language="VHDL" />
<generation synthesis="VHDL" />
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