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The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.

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NYU ProcDesign Core

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The NYU ProcDesign Core will be a RISCV-32I compatible core with a 5-stage pipeline.

The repo contains the modules and test for components that make up the core design.

The progress tracker for individual components can be found here.

You can find our getting started document here.

Core Components

The core modules include:

Branching Logic

The branch logic modules include:

Pipeline

The pipeline will have 5 stages:

  • Instruction Fetch (IF)
  • Instruction Decode (ID)
  • Execution (EX)
  • Memory Access (MEM)
  • Write Back (WB)

The pipeline will require 4 latch modules:

General Control and Hazards

Control Modules:

Caches

Cache Modules:

Current Draft of CPU Diagram

cpu

Further Reading

Development and Testing Guidelines

Offical RISCV Unprivileged Instruction Set Documentation

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The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.

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