bpu: bring bpu control signals into use (#1477)

OpenXiangShan · Feb 28, 2022 · 6ee06c7 · 6ee06c7
1 parent 6216e2e
commit 6ee06c7
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Showing 8 changed files with 23 additions and 7 deletions.
diff --git a/src/main/scala/xiangshan/frontend/BPU.scala b/src/main/scala/xiangshan/frontend/BPU.scala
@@ -172,7 +172,7 @@ class BasePredictorIO (implicit p: Parameters) extends XSBundle with HasBPUConst
   val out = Output(new BasePredictorOutput)
   // val flush_out = Valid(UInt(VAddrBits.W))
 
-  // val ctrl = Input(new BPUCtrl())
+  val ctrl = Input(new BPUCtrl)
 
   val s0_fire = Input(Bool())
   val s1_fire = Input(Bool())
@@ -234,14 +234,19 @@ class BpuToFtqIO(implicit p: Parameters) extends XSBundle {
 class PredictorIO(implicit p: Parameters) extends XSBundle {
   val bpu_to_ftq = new BpuToFtqIO()
   val ftq_to_bpu = Flipped(new FtqToBpuIO())
+  val ctrl = Input(new BPUCtrl)
 }
 
 @chiselName
 class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with HasPerfEvents with HasCircularQueuePtrHelper {
   val io = IO(new PredictorIO)
 
+  val ctrl = DelayN(io.ctrl, 1)
   val predictors = Module(if (useBPD) new Composer else new FakePredictor)
 
+  // ctrl signal
+  predictors.io.ctrl := ctrl
+
   val s0_fire, s1_fire, s2_fire, s3_fire = Wire(Bool())
   val s1_valid, s2_valid, s3_valid = RegInit(false.B)
   val s1_ready, s2_ready, s3_ready = Wire(Bool())

diff --git a/src/main/scala/xiangshan/frontend/Composer.scala b/src/main/scala/xiangshan/frontend/Composer.scala
@@ -45,6 +45,7 @@ class Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst wi
     c.io.s3_redirect := io.s3_redirect
 
     c.io.redirect := io.redirect
+    c.io.ctrl := DelayN(io.ctrl, 1)
 
     if (c.meta_size > 0) {
       metas = (metas << c.meta_size) | c.io.out.last_stage_meta(c.meta_size-1,0)

diff --git a/src/main/scala/xiangshan/frontend/FTB.scala b/src/main/scala/xiangshan/frontend/FTB.scala
@@ -422,7 +422,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
 
   val ftb_entry = RegEnable(ftbBank.io.read_resp, io.s1_fire)
   val s3_ftb_entry = RegEnable(ftb_entry, io.s2_fire)
-  val s1_hit = ftbBank.io.read_hits.valid
+  val s1_hit = ftbBank.io.read_hits.valid && io.ctrl.btb_enable
   val s2_hit = RegEnable(s1_hit, io.s1_fire)
   val s3_hit = RegEnable(s2_hit, io.s2_fire)
   val writeWay = ftbBank.io.read_hits.bits

diff --git a/src/main/scala/xiangshan/frontend/Frontend.scala b/src/main/scala/xiangshan/frontend/Frontend.scala
@@ -73,6 +73,9 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   val triggerEn = csrCtrl.trigger_enable
   ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8))
 
+  // bpu ctrl
+  bpu.io.ctrl := csrCtrl.bp_ctrl
+
 // pmp
   val pmp = Module(new PMP())
   val pmp_check = VecInit(Seq.fill(4)(Module(new PMPChecker(3, sameCycle = true)).io))

diff --git a/src/main/scala/xiangshan/frontend/RAS.scala b/src/main/scala/xiangshan/frontend/RAS.scala
@@ -180,7 +180,7 @@ class RAS(implicit p: Parameters) extends BasePredictor {
   val s2_is_jalr = s2_full_pred.is_jalr
   val s2_is_ret = s2_full_pred.is_ret
   // assert(is_jalr && is_ret || !is_ret)
-  when(s2_is_ret) {
+  when(s2_is_ret && io.ctrl.ras_enable) {
     s2_jalr_target := spec_top_addr
     // FIXME: should use s1 globally
   }
@@ -196,7 +196,7 @@ class RAS(implicit p: Parameters) extends BasePredictor {
   val s3_is_jalr = io.in.bits.resp_in(0).s3.full_pred.is_jalr
   val s3_is_ret = io.in.bits.resp_in(0).s3.full_pred.is_ret
   // assert(is_jalr && is_ret || !is_ret)
-  when(s3_is_ret) {
+  when(s3_is_ret && io.ctrl.ras_enable) {
     s3_jalr_target := s3_top.retAddr
     // FIXME: should use s1 globally
   }

diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
@@ -312,7 +312,9 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
         }
       }
 
-      io.out.resp.s3.full_pred.br_taken_mask(w) := RegEnable(s2_pred, io.s2_fire)
+      when (io.ctrl.sc_enable) {
+        io.out.resp.s3.full_pred.br_taken_mask(w) := RegEnable(s2_pred, io.s2_fire)
+      }
 
       val updateTageMeta = updateMeta
       when (updateValids(w) && updateSCMeta.scUsed(w)) {

diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala
@@ -687,7 +687,9 @@ class Tage(implicit p: Parameters) extends BaseTage {
     resp_meta.takens(i)     := RegEnable(s2_tageTakens(i), io.s2_fire)
     resp_meta.basecnts(i)   := RegEnable(s2_basecnts(i), io.s2_fire)
 
-    resp_s2.full_pred.br_taken_mask(i) := s2_tageTakens(i)
+    when (io.ctrl.tage_enable) {
+      resp_s2.full_pred.br_taken_mask(i) := s2_tageTakens(i)
+    }
 
     //---------------- update logics below ------------------//
     val hasUpdate = updateValids(i)

diff --git a/src/main/scala/xiangshan/frontend/uBTB.scala b/src/main/scala/xiangshan/frontend/uBTB.scala
@@ -160,7 +160,10 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
 
   XSDebug(p"uBTB entry, read_pc=${Hexadecimal(s0_pc)}\n")
 
-  io.out.resp.s1.minimal_pred.fromMicroBTBEntry(resp_valid && shouldNotFallThru && !lastCycleHasUpdate, dataMem.io.r.resp.data(0), s1_pc) // invalid when update
+  io.out.resp.s1.minimal_pred.fromMicroBTBEntry(
+    resp_valid && shouldNotFallThru && !lastCycleHasUpdate && io.ctrl.ubtb_enable,
+    dataMem.io.r.resp.data(0), s1_pc
+  ) // invalid when update
   io.out.resp.s1.is_minimal := true.B
 
   outMeta.ftPred := fallThruPredRAM.io.rdata