batch: export FPGA IO width macro and merge output data for connection

When using fpga, the IO width information is exported to the macro definition file, and the info and data in the out are merged to facilitate direct connection to the transmission module

src/main/scala/Gateway.scala

@@ -84,6 +84,7 @@ case class GatewayConfig(
   def vMacros: Seq[String] = {
     val macros = ListBuffer.empty[String]
     macros += s"CONFIG_DIFFTEST_STEPWIDTH ${stepWidth}"
+    macros += s"CONFIG_DIFFTEST_BATCH_IO_WITDH ${(batchArgByteLen._1 + batchArgByteLen._2) * 8}"
     if (isNonBlock) macros += "CONFIG_DIFFTEST_NONBLOCK"
     if (hasDeferredResult) macros += "CONFIG_DIFFTEST_DEFERRED_RESULT"
     if (hasInternalStep) macros += "CONFIG_DIFFTEST_INTERNAL_STEP"
@@ -271,12 +272,12 @@ object GatewaySink {
     }
     val out = Option.when(config.isFPGA) {
       IO(new Bundle {
-        val batch = Output(chiselTypeOf(io))
+        val data = Output(UInt())
         val enable = Output(Bool())
       })
     }
     if (config.isFPGA) {
-      out.get.batch := io
+      out.get.data := Cat(io.data, io.info)
       out.get.enable := control.enable
       dontTouch(out.get)
     }