Rename Async to Deferred, add related macros in Makefile. (#246)

Add non-block DPIC macros to Makefile, enabled by default.

Rename Async to Deferred, because when using only non-block DPIC,
we still need to synchronize at regular intervals. Hardware need to
pause until comparision is done.
It only means synchronization interal is extended, and result may be
deferred. But not turely async. We will try to add related implementation
later. So Hardware no need to wait for Comparison done.

Now we add macros to command line and each vfiles. We will try to gen it
at seperate macros.v later to make it configurable.

palladium.mk

@@ -15,7 +15,7 @@ PLDM_MACRO_FLAGS 	+= +define+RANDOMIZE_DELAY=0
 ifeq ($(RELEASE_WITH_ASSERT), 1)
 PLDM_MACRO_FLAGS 	+= +define+SYNTHESIS +define+TB_NO_DPIC
 else
-PLDM_MACRO_FLAGS 	+= +define+DIFFTEST
+PLDM_MACRO_FLAGS 	+= +define+DIFFTEST +define+TB_DPIC_NONBLOCK
 endif
 PLDM_MACRO_FLAGS 	+= $(PLDM_EXTRA_MACRO)
 
@@ -73,7 +73,7 @@ DPILIB_EMU    	 = $(PLDM_BUILD_DIR)/libdpi_emu.so
 PLDM_CSRC_DIR 	 = $(abspath ./src/test/csrc/vcs)
 PLDM_CXXFILES 	 = $(SIM_CXXFILES) $(shell find $(PLDM_CSRC_DIR) -name "*.cpp")
 PLDM_CXXFLAGS 	 = -m64 -c -fPIC -g -std=c++11 -I$(PLDM_IXCOM) -I$(PLDM_SIMTOOL)
-PLDM_CXXFLAGS 	 = $(SIM_CXXFLAGS) -I$(PLDM_CSRC_DIR) -DNUM_CORES=$(NUM_CORES)
+PLDM_CXXFLAGS 	 = $(SIM_CXXFLAGS) -I$(PLDM_CSRC_DIR) -DNUM_CORES=$(NUM_CORES) -DTB_DEFERRED_RESULT
 
 # XMSIM Flags
 XMSIM_FLAGS 	 = --xmsim -64 +xcprof -profile

src/main/scala/DPIC.scala

@@ -128,9 +128,11 @@ class DPIC[T <: DifftestBundle](gen: T, config: GatewayConfig) extends ExtModule
     // Initial for Palladium GFIFO
     val gfifoInitial =
       s"""
+         |`ifdef TB_DPIC_NONBLOCK
          |`ifdef PALLADIUM
          |initial $$ixc_ctrl("gfifo", "$dpicFuncName");
          |`endif
+         |`endif // TB_DPIC_NONBLOCK
          |""".stripMargin
     val modDef =
       s"""

src/test/csrc/vcs/vcs_main.cpp

@@ -90,7 +90,7 @@ extern "C" int simv_step() {
   }
 }
 
-#ifdef PALLADIUM
+#ifdef TB_DEFERRED_RESULT
 static int simv_result = 0;
 extern "C" void simv_nstep(uint8_t step) {
   if (simv_result)
@@ -113,4 +113,4 @@ extern "C" int simv_nstep(uint8_t step) {
   }
   return 0;
 }
-#endif // PALLADIUM
+#endif // TB_DEFERRED_RESULT

src/test/vsrc/vcs/AsyncControl.v → src/test/vsrc/vcs/DeferredControl.v

@@ -1,8 +1,11 @@
-`ifdef TB_ASYNC
+`ifdef TB_DPIC_NONBLOCK
+  `define TB_DEFERRED_RESULT
+`endif
 
 `define STEP_WIDTH 8
 
-module AsyncControl(
+`ifdef TB_DEFERRED_RESULT
+module DeferredControl(
   input clock,
   input reset,
   input [`STEP_WIDTH - 1:0] step,
@@ -12,9 +15,11 @@ module AsyncControl(
 import "DPI-C" function int simv_result_fetch();
 import "DPI-C" function void simv_nstep(int step);
 
+`ifdef TB_DPIC_NONBLOCK
 `ifdef PALLADIUM
 initial $ixc_ctrl("gfifo", "simv_nstep");
 `endif // PALLADIUM
+`endif TB_DPIC_NONBLOCK
 
 reg [63:0] fetch_cycles;
 initial fetch_cycles = 4999;
@@ -43,4 +48,4 @@ always @(posedge clock) begin
 end
 
 endmodule;
-`endif // TB_ASYNC
+`endif // TB_DEFERRED_RESULT

src/test/vsrc/vcs/top.v

@@ -13,7 +13,9 @@
 *
 * See the Mulan PSL v2 for more details.
 ***************************************************************************************/
-
+`ifdef TB_DPIC_NONBLOCK
+  `define TB_DEFERRED_RESULT
+`endif
 `define STEP_WIDTH 8
 
 module tb_top();
@@ -24,9 +26,9 @@ import "DPI-C" function void set_flash_bin(string bin);
 import "DPI-C" function void set_diff_ref_so(string diff_so);
 import "DPI-C" function void set_no_diff();
 import "DPI-C" function void simv_init();
-`ifndef TB_ASYNC
+`ifndef TB_DEFERRED_RESULT
 import "DPI-C" function int simv_nstep(int step);
-`endif // TB_ASYNC
+`endif // TB_DEFERRED_RESULT
 `endif // TB_NO_DPIC
 
 `ifdef PALLADIUM
@@ -186,15 +188,15 @@ always @(posedge clock) begin
   end
 end
 
-`ifdef TB_ASYNC
+`ifdef TB_DEFERRED_RESULT
 wire simv_result;
-AsyncControl async(
+DeferredControl deferred(
   .clock(clock),
   .reset(reset),
   .step(difftest_step_delay),
   .simv_result(simv_result)
 );
-`endif // TB_ASYNC
+`endif // TB_DEFERRED_RESULT
 `endif // TB_NO_DPIC
 
 reg [63:0] n_cycles;
@@ -216,7 +218,7 @@ always @(posedge clock) begin
     if (!n_cycles) begin
       simv_init();
     end
-`ifdef TB_ASYNC
+`ifdef TB_DEFERRED_RESULT
     else if (simv_result) begin
       $display("DIFFTEST FAILED at cycle %d", n_cycles);
       $finish();
@@ -229,7 +231,7 @@ always @(posedge clock) begin
         $finish();
       end
     end
-`endif // TB_ASYNC
+`endif // TB_DEFERRED_RESULT
 `endif // TB_NO_DPIC
   end
 end