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Use DPIC-function to return deferred result #250
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src/test/vsrc/vcs/DeferredControl.v
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if ((~simv_result) && (|step)) begin | ||
simv_nstep(step); | ||
end | ||
if (~reset && (~simv_result) && (|step)) begin |
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Better to use !
instead of ~
, step != 0
instead of |step
for logic operations.
Use one short sentence for the commit title please. See Chisel commits: https://github.com/chipsalliance/chisel/commits/main/ |
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src/test/vsrc/vcs/DeferredControl.v
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if ((~simv_result) && (|step)) begin | ||
simv_nstep(step); | ||
end | ||
if ((!reset) && (!simv_result) && (step != 0)) begin |
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No need for the extra braces ()
but it's ok
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The DPIC-task is contained in GFIFO function,which unsupport output. I will check whether it works |
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Before this commit, we fetch simv_result at 5000 cycles. Only when the result is not zero, it works and stop simulation. Now we use DPIC task to implement the return of simv_result when not zero, so only one DPIC task will be used to stop simulation. That will reduce the cost of fetch and get result return faster.
To return a value in GFIFO function, we can use SFIFO DPIC function to set it. |
Before this commit, we fetch simv_result at 5000 cycles. Only when the result is not zero, it works and stop simulation. Now we use DPIC function to implement the return of simv_result when not zero, so only one DPIC function will be used to stop simulation. That will reduce the cost of fetch and get result return faster.
Before this commit, we fetch simv_result at 5000 cycles. Only when the result is not zero, it works and stop simulation.
Now we use DPIC task to implement the return of simv_result when not zero, so only one DPIC task will be used to stop simulation. That will reduce the cost of fetch and get result return faster.