Gen C++ and Verilog macros by GatewayConfig #251
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klin02
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src/main/scala/Difftest.scala
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| def generateVeriogHeader(): Unit = { | ||
| val difftestVeriog = ListBuffer.empty[String] | ||
| vMacros.foreach(m => difftestVeriog += s"`define $m") | ||
| val outputDir = sys.env("NOOP_HOME") + "/build/rtl" |
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Generate files must be put in generated-src only to avoid confusions. build/rtl is only for chisel design files.
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Make the output directory a function shared by generateVeriogHeader and generateCppHeader
src/main/scala/Gateway.scala
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| @@ -32,16 +32,38 @@ case class GatewayConfig( | |||
| replaySize : Int = 256, | |||
| diffStateSelect: Boolean = false, | |||
| isBatch : Boolean = false, | |||
| batchSize : Int = 32 | |||
| batchSize : Int = 32, | |||
| isNonBlock : Boolean = false | |||
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Always add a , after the arguments. Then adding arguments will not modify the previous line. isNonBlock: Boolean = false,
src/main/scala/Gateway.scala
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| } | ||
| def vMacros: Seq[String] = { | ||
| val macros = ListBuffer.empty[String] | ||
| macros += s"TB_DIFF_STEP_WIDTH ${stepWidth}" |
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why not also use the CONFIG_DIFFTEST_* names?
One of the good naming practice is to avoid abbreviations if acceptable.
klin02
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CI fails because NutShell changes the RTL path. I'll fix it later |
Makefile
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| @@ -64,7 +64,8 @@ PLUGIN_CSRC_DIR = $(abspath ./src/test/csrc/plugin) | |||
| PLUGIN_INC_DIR = $(abspath $(PLUGIN_CSRC_DIR)/include) | |||
| SIM_CXXFLAGS += -I$(PLUGIN_INC_DIR) | |||
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| VSRC_DIR = $(abspath ./src/test/vsrc/common) | |||
| GEN_VSRC_DIR = $(BUILD_DIR)/generated-src | |||
| VSRC_DIR = $(abspath ./src/test/vsrc/common) $(GEN_VSRC_DIR) | |||
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No need to add $(GEN_VSRC_DIR) to VSRC_DIR?
VCS and verilator will search for the missing modules in include paths
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Sure, I will delete it. Now I have trouble using cross-directory include on Palladium，and I am asking Palladium engineer for help.
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what about passing all verilog files, including the generated ones, to palladium?
klin02
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Currently all macros in Gateway can be decided by GatewayConfig, we move macros inside Config for better comprehension. Difftest-related macros in Verilog can be configured in generated DifftestMacros.v, which should be included by all files use those macros. Some redundant passing of config and return val of collect is removed. Some macros are renamed for similar format. Makefile and mk are changed to include generated/DifftestMacros.v
poemonsense
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Currently all macros in Gateway can be decided by GatewayConfig, we move macros inside Config for better comprehension. Difftest-related macros in Verilog can be configured in generated DifftestMacros.v, which should be included by all files use those macros. Some redundant passing of config and return val of collect is removed. Some macros are renamed for similar format. Makefile and mk are changed to include generated/DifftestMacros.v
Currently all macros in Gateway can be decided by GatewayConfig, we move macros inside Config for better comprehension. Difftest-related macros in Verilog can be configured in generated DifftestMacros.v, which should be included by all files use those macros. Some redundant passing of config and return val of collect is removed. Some macros are renamed for similar format. Makefile and mk are changed to include generated/DifftestMacros.v
Currently all macros in Gateway can be decided by GatewayConfig, we move macros inside Config for better comprehension.
Difftest-related macros in Verilog can be configured in generated DifftestMacros.v, which should be included by all files use those macros.
Some redundant passing of config and return val of collect is removed. Some macros are renamed for similar format.