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refactor(difftest): reuse common nstep logic for emu/simv/fpga #621

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Merged
merged 1 commit into from
May 13, 2025

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klin02
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@klin02 klin02 commented May 12, 2025

Previously, we use various difftest/simv/fpga_nstep functions for Verilator/VCS/FPGA, resulting in duplicated code and inconsistent simulation conditions.

For example, in the multi-core scenario, VCS/FPGA warmedup and exceed at the same number of instructions for each core, while Verilator warmup and exceed when a certain core reaching instrs.

This change reuse the common difftest_nstep as the comparison logic and aligned the simulation conditions of VCS/FPGA with those of Verilator.

We also the issues of VCS where SIMV_WARMUP did not return correctly to DUT and where the number of instructions was calculated incorrectly during soft warmup.

@klin02 klin02 force-pushed the common-nstep branch 2 times, most recently from 8361368 to 154d958 Compare May 13, 2025 02:45
Previously, we use various difftest/simv/fpga_nstep functions for
Verilator/VCS/FPGA, resulting in duplicated code and inconsistent
simulation conditions.

For example, in the multi-core scenario, VCS/FPGA warmedup and exceed
at the same number of instructions for each core, while Verilator
warmup and exceed when a certain core reaching instrs.

This change reuse the common difftest_nstep as the comparison logic
and aligned the simulation conditions of VCS/FPGA with those of
Verilator.

We also the issues of VCS where SIMV_WARMUP did not return
correctly to DUT and where the number of instructions was calculated
incorrectly during soft warmup.
@xiaokamikami
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The changes now make the code look cleaner. Good commit

@klin02 klin02 merged commit 9dd0042 into master May 13, 2025
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@klin02 klin02 deleted the common-nstep branch May 13, 2025 07:55
BNWeee pushed a commit to OpenXiangShan-Nanhu/difftest that referenced this pull request May 14, 2025
…iangShan#621)

Previously, we use various difftest/simv/fpga_nstep functions for
Verilator/VCS/FPGA, resulting in duplicated code and inconsistent
simulation conditions.

For example, in the multi-core scenario, VCS/FPGA warmedup and exceed
at the same number of instructions for each core, while Verilator
warmup and exceed when a certain core reaching instrs.

This change reuse the common difftest_nstep as the comparison logic
and aligned the simulation conditions of VCS/FPGA with those of
Verilator.

We also the issues of VCS where SIMV_WARMUP did not return
correctly to DUT and where the number of instructions was calculated
incorrectly during soft warmup.
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3 participants